tegra.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <fdtdec.h>
  8. #include <log.h>
  9. #include <panel.h>
  10. #include <part.h>
  11. #include <pwm.h>
  12. #include <video.h>
  13. #include <asm/cache.h>
  14. #include <asm/system.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/funcmux.h>
  19. #include <asm/arch/pinmux.h>
  20. #include <asm/arch/pwm.h>
  21. #include <asm/arch/display.h>
  22. #include <asm/arch-tegra/timer.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. /* Information about the display controller */
  25. struct tegra_lcd_priv {
  26. int width; /* width in pixels */
  27. int height; /* height in pixels */
  28. enum video_log2_bpp log2_bpp; /* colour depth */
  29. struct display_timing timing;
  30. struct udevice *panel;
  31. struct disp_ctlr *disp; /* Display controller to use */
  32. fdt_addr_t frame_buffer; /* Address of frame buffer */
  33. unsigned pixel_clock; /* Pixel clock in Hz */
  34. };
  35. enum {
  36. /* Maximum LCD size we support */
  37. LCD_MAX_WIDTH = 1366,
  38. LCD_MAX_HEIGHT = 768,
  39. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  40. };
  41. static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
  42. {
  43. unsigned h_dda, v_dda;
  44. unsigned long val;
  45. val = readl(&dc->cmd.disp_win_header);
  46. val |= WINDOW_A_SELECT;
  47. writel(val, &dc->cmd.disp_win_header);
  48. writel(win->fmt, &dc->win.color_depth);
  49. clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
  50. BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
  51. val = win->out_x << H_POSITION_SHIFT;
  52. val |= win->out_y << V_POSITION_SHIFT;
  53. writel(val, &dc->win.pos);
  54. val = win->out_w << H_SIZE_SHIFT;
  55. val |= win->out_h << V_SIZE_SHIFT;
  56. writel(val, &dc->win.size);
  57. val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
  58. val |= win->h << V_PRESCALED_SIZE_SHIFT;
  59. writel(val, &dc->win.prescaled_size);
  60. writel(0, &dc->win.h_initial_dda);
  61. writel(0, &dc->win.v_initial_dda);
  62. h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
  63. v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
  64. val = h_dda << H_DDA_INC_SHIFT;
  65. val |= v_dda << V_DDA_INC_SHIFT;
  66. writel(val, &dc->win.dda_increment);
  67. writel(win->stride, &dc->win.line_stride);
  68. writel(0, &dc->win.buf_stride);
  69. val = WIN_ENABLE;
  70. if (win->bpp < 24)
  71. val |= COLOR_EXPAND;
  72. writel(val, &dc->win.win_opt);
  73. writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
  74. writel(win->x, &dc->winbuf.addr_h_offset);
  75. writel(win->y, &dc->winbuf.addr_v_offset);
  76. writel(0xff00, &dc->win.blend_nokey);
  77. writel(0xff00, &dc->win.blend_1win);
  78. val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
  79. val |= GENERAL_UPDATE | WIN_A_UPDATE;
  80. writel(val, &dc->cmd.state_ctrl);
  81. }
  82. static int update_display_mode(struct dc_disp_reg *disp,
  83. struct tegra_lcd_priv *priv)
  84. {
  85. struct display_timing *dt = &priv->timing;
  86. unsigned long val;
  87. unsigned long rate;
  88. unsigned long div;
  89. writel(0x0, &disp->disp_timing_opt);
  90. writel(1 | 1 << 16, &disp->ref_to_sync);
  91. writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
  92. writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
  93. &disp->back_porch);
  94. writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
  95. &disp->front_porch);
  96. writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
  97. val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
  98. val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
  99. writel(val, &disp->data_enable_opt);
  100. val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
  101. val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
  102. val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
  103. writel(val, &disp->disp_interface_ctrl);
  104. /*
  105. * The pixel clock divider is in 7.1 format (where the bottom bit
  106. * represents 0.5). Here we calculate the divider needed to get from
  107. * the display clock (typically 600MHz) to the pixel clock. We round
  108. * up or down as requried.
  109. */
  110. rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
  111. div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
  112. debug("Display clock %lu, divider %lu\n", rate, div);
  113. writel(0x00010001, &disp->shift_clk_opt);
  114. val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
  115. val |= div << SHIFT_CLK_DIVIDER_SHIFT;
  116. writel(val, &disp->disp_clk_ctrl);
  117. return 0;
  118. }
  119. /* Start up the display and turn on power to PWMs */
  120. static void basic_init(struct dc_cmd_reg *cmd)
  121. {
  122. u32 val;
  123. writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
  124. writel(0x0000011a, &cmd->cont_syncpt_vsync);
  125. writel(0x00000000, &cmd->int_type);
  126. writel(0x00000000, &cmd->int_polarity);
  127. writel(0x00000000, &cmd->int_mask);
  128. writel(0x00000000, &cmd->int_enb);
  129. val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
  130. val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
  131. val |= PM1_ENABLE;
  132. writel(val, &cmd->disp_pow_ctrl);
  133. val = readl(&cmd->disp_cmd);
  134. val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
  135. writel(val, &cmd->disp_cmd);
  136. }
  137. static void basic_init_timer(struct dc_disp_reg *disp)
  138. {
  139. writel(0x00000020, &disp->mem_high_pri);
  140. writel(0x00000001, &disp->mem_high_pri_timer);
  141. }
  142. static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
  143. 0x00000000,
  144. 0x00000000,
  145. 0x00000000,
  146. 0x00000000,
  147. };
  148. static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
  149. 0x00000000,
  150. 0x01000000,
  151. 0x00000000,
  152. 0x00000000,
  153. };
  154. static const u32 rgb_data_tab[PIN_REG_COUNT] = {
  155. 0x00000000,
  156. 0x00000000,
  157. 0x00000000,
  158. 0x00000000,
  159. };
  160. static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
  161. 0x00000000,
  162. 0x00000000,
  163. 0x00000000,
  164. 0x00000000,
  165. 0x00210222,
  166. 0x00002200,
  167. 0x00020000,
  168. };
  169. static void rgb_enable(struct dc_com_reg *com)
  170. {
  171. int i;
  172. for (i = 0; i < PIN_REG_COUNT; i++) {
  173. writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
  174. writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
  175. writel(rgb_data_tab[i], &com->pin_output_data[i]);
  176. }
  177. for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
  178. writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
  179. }
  180. static int setup_window(struct disp_ctl_win *win,
  181. struct tegra_lcd_priv *priv)
  182. {
  183. win->x = 0;
  184. win->y = 0;
  185. win->w = priv->width;
  186. win->h = priv->height;
  187. win->out_x = 0;
  188. win->out_y = 0;
  189. win->out_w = priv->width;
  190. win->out_h = priv->height;
  191. win->phys_addr = priv->frame_buffer;
  192. win->stride = priv->width * (1 << priv->log2_bpp) / 8;
  193. debug("%s: depth = %d\n", __func__, priv->log2_bpp);
  194. switch (priv->log2_bpp) {
  195. case VIDEO_BPP32:
  196. win->fmt = COLOR_DEPTH_R8G8B8A8;
  197. win->bpp = 32;
  198. break;
  199. case VIDEO_BPP16:
  200. win->fmt = COLOR_DEPTH_B5G6R5;
  201. win->bpp = 16;
  202. break;
  203. default:
  204. debug("Unsupported LCD bit depth");
  205. return -1;
  206. }
  207. return 0;
  208. }
  209. /**
  210. * Register a new display based on device tree configuration.
  211. *
  212. * The frame buffer can be positioned by U-Boot or overridden by the fdt.
  213. * You should pass in the U-Boot address here, and check the contents of
  214. * struct tegra_lcd_priv to see what was actually chosen.
  215. *
  216. * @param blob Device tree blob
  217. * @param priv Driver's private data
  218. * @param default_lcd_base Default address of LCD frame buffer
  219. * @return 0 if ok, -1 on error (unsupported bits per pixel)
  220. */
  221. static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
  222. void *default_lcd_base)
  223. {
  224. struct disp_ctl_win window;
  225. struct dc_ctlr *dc;
  226. priv->frame_buffer = (u32)default_lcd_base;
  227. dc = (struct dc_ctlr *)priv->disp;
  228. /*
  229. * A header file for clock constants was NAKed upstream.
  230. * TODO: Put this into the FDT and fdt_lcd struct when we have clock
  231. * support there
  232. */
  233. clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
  234. 144 * 1000000);
  235. clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
  236. 600 * 1000000);
  237. basic_init(&dc->cmd);
  238. basic_init_timer(&dc->disp);
  239. rgb_enable(&dc->com);
  240. if (priv->pixel_clock)
  241. update_display_mode(&dc->disp, priv);
  242. if (setup_window(&window, priv))
  243. return -1;
  244. update_window(dc, &window);
  245. return 0;
  246. }
  247. static int tegra_lcd_probe(struct udevice *dev)
  248. {
  249. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  250. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  251. struct tegra_lcd_priv *priv = dev_get_priv(dev);
  252. const void *blob = gd->fdt_blob;
  253. int ret;
  254. /* Initialize the Tegra display controller */
  255. funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
  256. if (tegra_display_probe(blob, priv, (void *)plat->base)) {
  257. printf("%s: Failed to probe display driver\n", __func__);
  258. return -1;
  259. }
  260. pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
  261. pinmux_tristate_disable(PMUX_PINGRP_GPU);
  262. ret = panel_enable_backlight(priv->panel);
  263. if (ret) {
  264. debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
  265. return ret;
  266. }
  267. mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
  268. DCACHE_WRITETHROUGH);
  269. /* Enable flushing after LCD writes if requested */
  270. video_set_flush_dcache(dev, true);
  271. uc_priv->xsize = priv->width;
  272. uc_priv->ysize = priv->height;
  273. uc_priv->bpix = priv->log2_bpp;
  274. debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
  275. plat->size);
  276. return 0;
  277. }
  278. static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
  279. {
  280. struct tegra_lcd_priv *priv = dev_get_priv(dev);
  281. const void *blob = gd->fdt_blob;
  282. struct display_timing *timing;
  283. int node = dev_of_offset(dev);
  284. int panel_node;
  285. int rgb;
  286. int ret;
  287. priv->disp = dev_read_addr_ptr(dev);
  288. if (!priv->disp) {
  289. debug("%s: No display controller address\n", __func__);
  290. return -EINVAL;
  291. }
  292. rgb = fdt_subnode_offset(blob, node, "rgb");
  293. if (rgb < 0) {
  294. debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
  295. __func__, dev->name, rgb);
  296. return -EINVAL;
  297. }
  298. ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
  299. if (ret) {
  300. debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
  301. __func__, dev->name, ret);
  302. return -EINVAL;
  303. }
  304. timing = &priv->timing;
  305. priv->width = timing->hactive.typ;
  306. priv->height = timing->vactive.typ;
  307. priv->pixel_clock = timing->pixelclock.typ;
  308. priv->log2_bpp = VIDEO_BPP16;
  309. /*
  310. * Sadly the panel phandle is in an rgb subnode so we cannot use
  311. * uclass_get_device_by_phandle().
  312. */
  313. panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
  314. if (panel_node < 0) {
  315. debug("%s: Cannot find panel information\n", __func__);
  316. return -EINVAL;
  317. }
  318. ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
  319. &priv->panel);
  320. if (ret) {
  321. debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
  322. dev->name, ret);
  323. return ret;
  324. }
  325. return 0;
  326. }
  327. static int tegra_lcd_bind(struct udevice *dev)
  328. {
  329. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  330. const void *blob = gd->fdt_blob;
  331. int node = dev_of_offset(dev);
  332. int rgb;
  333. rgb = fdt_subnode_offset(blob, node, "rgb");
  334. if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
  335. return -ENODEV;
  336. plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  337. (1 << LCD_MAX_LOG2_BPP) / 8;
  338. return 0;
  339. }
  340. static const struct video_ops tegra_lcd_ops = {
  341. };
  342. static const struct udevice_id tegra_lcd_ids[] = {
  343. { .compatible = "nvidia,tegra20-dc" },
  344. { }
  345. };
  346. U_BOOT_DRIVER(tegra_lcd) = {
  347. .name = "tegra_lcd",
  348. .id = UCLASS_VIDEO,
  349. .of_match = tegra_lcd_ids,
  350. .ops = &tegra_lcd_ops,
  351. .bind = tegra_lcd_bind,
  352. .probe = tegra_lcd_probe,
  353. .ofdata_to_platdata = tegra_lcd_ofdata_to_platdata,
  354. .priv_auto_alloc_size = sizeof(struct tegra_lcd_priv),
  355. };