ssd2828.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) 2015 Siarhei Siamashka <siarhei.siamashka@gmail.com>
  4. */
  5. /*
  6. * Support for the SSD2828 bridge chip, which can take pixel data coming
  7. * from a parallel LCD interface and translate it on the flight into MIPI DSI
  8. * interface for driving a MIPI compatible TFT display.
  9. *
  10. * Implemented as a utility function. To be used from display drivers, which are
  11. * responsible for driving parallel LCD hardware in front of the video pipeline.
  12. */
  13. #ifndef _SSD2828_H
  14. #define _SSD2828_H
  15. struct ctfb_res_modes;
  16. struct ssd2828_config {
  17. /*********************************************************************/
  18. /* SSD2828 configuration */
  19. /*********************************************************************/
  20. /*
  21. * The pins, which are used for SPI communication. This is only used
  22. * for configuring SSD2828, so the performance is irrelevant (only
  23. * around a hundred of bytes is moved). Also these can be any arbitrary
  24. * GPIO pins (not necessarily the pins having hardware SPI function).
  25. * Moreover, the 'sdo' pin may be even not wired up in some devices.
  26. *
  27. * These configuration variables need to be set as pin numbers for
  28. * the standard u-boot GPIO interface (gpio_get_value/gpio_set_value
  29. * functions). Note that -1 value can be used for the pins, which are
  30. * not really wired up.
  31. */
  32. int csx_pin;
  33. int sck_pin;
  34. int sdi_pin;
  35. int sdo_pin;
  36. /* SSD2828 reset pin (shared with LCD panel reset) */
  37. int reset_pin;
  38. /*
  39. * The SSD2828 has its own dedicated clock source 'tx_clk' (connected
  40. * to TX_CLK_XIO/TX_CLK_XIN pins), which is necessary at least for
  41. * clocking SPI after reset. The exact clock speed is not strictly,
  42. * defined, but the datasheet says that it must be somewhere in the
  43. * 8MHz - 30MHz range (see "TX_CLK Timing" section). It can be also
  44. * used as a reference clock for PLL. If the exact clock frequency
  45. * is known, then it can be specified here. If it is unknown, or the
  46. * information is not trustworthy, then it can be set to 0.
  47. *
  48. * If unsure, set to 0.
  49. */
  50. int ssd2828_tx_clk_khz;
  51. /*
  52. * This is not a property of the used LCD panel, but more like a
  53. * property of the SSD2828 wiring. See the "SSD2828QN4 RGB data
  54. * arrangement" table in the datasheet. The SSD2828 pins are arranged
  55. * in such a way that 18bpp and 24bpp configurations are completely
  56. * incompatible with each other.
  57. *
  58. * Depending on the color depth, this must be set to 16, 18 or 24.
  59. */
  60. int ssd2828_color_depth;
  61. /*********************************************************************/
  62. /* LCD panel configuration */
  63. /*********************************************************************/
  64. /*
  65. * The number of lanes in the MIPI DSI interface. May vary from 1 to 4.
  66. *
  67. * This information can be found in the LCD panel datasheet.
  68. */
  69. int mipi_dsi_number_of_data_lanes;
  70. /*
  71. * Data transfer bit rate per lane. Please note that it is expected
  72. * to be higher than the pixel clock rate of the used video mode when
  73. * multiplied by the number of lanes. This is perfectly normal because
  74. * MIPI DSI handles data transfers in periodic bursts, and uses the
  75. * idle time between bursts for sending configuration information and
  76. * commands. Or just for saving power.
  77. *
  78. * The necessary Mbps/lane information can be found in the LCD panel
  79. * datasheet. Note that the transfer rate can't be always set precisely
  80. * and it may be rounded *up* (introducing no more than 10Mbps error).
  81. */
  82. int mipi_dsi_bitrate_per_data_lane_mbps;
  83. /*
  84. * Setting this to 1 enforces packing of 18bpp pixel data in 24bpp
  85. * envelope when sending it over the MIPI DSI link.
  86. *
  87. * If unsure, set to 0.
  88. */
  89. int mipi_dsi_loosely_packed_pixel_format;
  90. /*
  91. * According to the "Example for system sleep in and out" section in
  92. * the SSD2828 datasheet, some LCD panel specific delays are necessary
  93. * after MIPI DCS commands EXIT_SLEEP_MODE and SET_DISPLAY_ON.
  94. *
  95. * For example, Allwinner uses 100 milliseconds delay after
  96. * EXIT_SLEEP_MODE and 200 milliseconds delay after SET_DISPLAY_ON.
  97. */
  98. int mipi_dsi_delay_after_exit_sleep_mode_ms;
  99. int mipi_dsi_delay_after_set_display_on_ms;
  100. };
  101. /*
  102. * Initialize the SSD2828 chip. It needs the 'ssd2828_config' structure
  103. * and also the video mode timings.
  104. *
  105. * The right place to insert this function call is after the parallel LCD
  106. * interface is initialized and before turning on the backlight. This is
  107. * advised in the "Example for system sleep in and out" section of the
  108. * SSD2828 datasheet. And also SS2828 may use 'pclk' as the clock source
  109. * for PLL, which means that the input signal must be already there.
  110. */
  111. int ssd2828_init(const struct ssd2828_config *cfg,
  112. const struct ctfb_res_modes *mode);
  113. #endif