mxsfb.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX23/i.MX28 LCDIF driver
  4. *
  5. * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <env.h>
  11. #include <log.h>
  12. #include <asm/cache.h>
  13. #include <dm/device_compat.h>
  14. #include <linux/delay.h>
  15. #include <linux/errno.h>
  16. #include <malloc.h>
  17. #include <video.h>
  18. #include <video_fb.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/imx-regs.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/mach-imx/dma.h>
  23. #include <asm/io.h>
  24. #include "videomodes.h"
  25. #define PS2KHZ(ps) (1000000000UL / (ps))
  26. #define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
  27. #define BITS_PP 18
  28. #define BYTES_PP 4
  29. struct mxs_dma_desc desc;
  30. /**
  31. * mxsfb_system_setup() - Fine-tune LCDIF configuration
  32. *
  33. * This function is used to adjust the LCDIF configuration. This is usually
  34. * needed when driving the controller in System-Mode to operate an 8080 or
  35. * 6800 connected SmartLCD.
  36. */
  37. __weak void mxsfb_system_setup(void)
  38. {
  39. }
  40. /*
  41. * ARIES M28EVK:
  42. * setenv videomode
  43. * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  44. * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  45. *
  46. * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
  47. * setenv videomode
  48. * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
  49. * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  50. */
  51. static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
  52. struct display_timing *timings, int bpp)
  53. {
  54. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  55. const enum display_flags flags = timings->flags;
  56. uint32_t word_len = 0, bus_width = 0;
  57. uint8_t valid_data = 0;
  58. uint32_t vdctrl0;
  59. #if CONFIG_IS_ENABLED(CLK)
  60. struct clk per_clk;
  61. int ret;
  62. ret = clk_get_by_name(dev, "per", &per_clk);
  63. if (ret) {
  64. dev_err(dev, "Failed to get mxs clk: %d\n", ret);
  65. return;
  66. }
  67. ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
  68. if (ret < 0) {
  69. dev_err(dev, "Failed to set mxs clk: %d\n", ret);
  70. return;
  71. }
  72. ret = clk_enable(&per_clk);
  73. if (ret < 0) {
  74. dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
  75. return;
  76. }
  77. #else
  78. /* Kick in the LCDIF clock */
  79. mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
  80. #endif
  81. /* Restart the LCDIF block */
  82. mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
  83. switch (bpp) {
  84. case 24:
  85. word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  86. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
  87. valid_data = 0x7;
  88. break;
  89. case 18:
  90. word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  91. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
  92. valid_data = 0x7;
  93. break;
  94. case 16:
  95. word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
  96. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
  97. valid_data = 0xf;
  98. break;
  99. case 8:
  100. word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
  101. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
  102. valid_data = 0xf;
  103. break;
  104. }
  105. writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
  106. LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
  107. &regs->hw_lcdif_ctrl);
  108. writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
  109. &regs->hw_lcdif_ctrl1);
  110. mxsfb_system_setup();
  111. writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
  112. timings->hactive.typ, &regs->hw_lcdif_transfer_count);
  113. vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
  114. LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
  115. LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
  116. timings->vsync_len.typ;
  117. if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
  118. vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
  119. if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
  120. vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
  121. if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
  122. vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
  123. if(flags & DISPLAY_FLAGS_DE_HIGH)
  124. vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
  125. writel(vdctrl0, &regs->hw_lcdif_vdctrl0);
  126. writel(timings->vback_porch.typ + timings->vfront_porch.typ +
  127. timings->vsync_len.typ + timings->vactive.typ,
  128. &regs->hw_lcdif_vdctrl1);
  129. writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
  130. (timings->hback_porch.typ + timings->hfront_porch.typ +
  131. timings->hsync_len.typ + timings->hactive.typ),
  132. &regs->hw_lcdif_vdctrl2);
  133. writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
  134. LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
  135. (timings->vback_porch.typ + timings->vsync_len.typ),
  136. &regs->hw_lcdif_vdctrl3);
  137. writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
  138. &regs->hw_lcdif_vdctrl4);
  139. writel(fb_addr, &regs->hw_lcdif_cur_buf);
  140. writel(fb_addr, &regs->hw_lcdif_next_buf);
  141. /* Flush FIFO first */
  142. writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
  143. #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
  144. /* Sync signals ON */
  145. setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
  146. #endif
  147. /* FIFO cleared */
  148. writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
  149. /* RUN! */
  150. writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
  151. }
  152. static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
  153. int bpp, u32 fb)
  154. {
  155. /* Start framebuffer */
  156. mxs_lcd_init(dev, fb, timings, bpp);
  157. #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
  158. /*
  159. * If the LCD runs in system mode, the LCD refresh has to be triggered
  160. * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
  161. * having to set this bit manually after every single change in the
  162. * framebuffer memory, we set up specially crafted circular DMA, which
  163. * sets the RUN bit, then waits until it gets cleared and repeats this
  164. * infinitelly. This way, we get smooth continuous updates of the LCD.
  165. */
  166. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  167. memset(&desc, 0, sizeof(struct mxs_dma_desc));
  168. desc.address = (dma_addr_t)&desc;
  169. desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  170. MXS_DMA_DESC_WAIT4END |
  171. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  172. desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
  173. desc.cmd.next = (uint32_t)&desc.cmd;
  174. /* Execute the DMA chain. */
  175. mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
  176. #endif
  177. return 0;
  178. }
  179. static int mxs_remove_common(u32 fb)
  180. {
  181. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  182. int timeout = 1000000;
  183. if (!fb)
  184. return -EINVAL;
  185. writel(fb, &regs->hw_lcdif_cur_buf_reg);
  186. writel(fb, &regs->hw_lcdif_next_buf_reg);
  187. writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
  188. while (--timeout) {
  189. if (readl(&regs->hw_lcdif_ctrl1_reg) &
  190. LCDIF_CTRL1_VSYNC_EDGE_IRQ)
  191. break;
  192. udelay(1);
  193. }
  194. mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
  195. return 0;
  196. }
  197. #ifndef CONFIG_DM_VIDEO
  198. static GraphicDevice panel;
  199. void lcdif_power_down(void)
  200. {
  201. mxs_remove_common(panel.frameAdrs);
  202. }
  203. void *video_hw_init(void)
  204. {
  205. int bpp = -1;
  206. int ret = 0;
  207. char *penv;
  208. void *fb = NULL;
  209. struct ctfb_res_modes mode;
  210. struct display_timing timings;
  211. puts("Video: ");
  212. /* Suck display configuration from "videomode" variable */
  213. penv = env_get("videomode");
  214. if (!penv) {
  215. puts("MXSFB: 'videomode' variable not set!\n");
  216. return NULL;
  217. }
  218. bpp = video_get_params(&mode, penv);
  219. /* fill in Graphic device struct */
  220. sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
  221. panel.winSizeX = mode.xres;
  222. panel.winSizeY = mode.yres;
  223. panel.plnSizeX = mode.xres;
  224. panel.plnSizeY = mode.yres;
  225. switch (bpp) {
  226. case 24:
  227. case 18:
  228. panel.gdfBytesPP = 4;
  229. panel.gdfIndex = GDF_32BIT_X888RGB;
  230. break;
  231. case 16:
  232. panel.gdfBytesPP = 2;
  233. panel.gdfIndex = GDF_16BIT_565RGB;
  234. break;
  235. case 8:
  236. panel.gdfBytesPP = 1;
  237. panel.gdfIndex = GDF__8BIT_INDEX;
  238. break;
  239. default:
  240. printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
  241. return NULL;
  242. }
  243. panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
  244. /* Allocate framebuffer */
  245. fb = memalign(ARCH_DMA_MINALIGN,
  246. roundup(panel.memSize, ARCH_DMA_MINALIGN));
  247. if (!fb) {
  248. printf("MXSFB: Error allocating framebuffer!\n");
  249. return NULL;
  250. }
  251. /* Wipe framebuffer */
  252. memset(fb, 0, panel.memSize);
  253. panel.frameAdrs = (u32)fb;
  254. printf("%s\n", panel.modeIdent);
  255. video_ctfb_mode_to_display_timing(&mode, &timings);
  256. ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
  257. if (ret)
  258. goto dealloc_fb;
  259. return (void *)&panel;
  260. dealloc_fb:
  261. free(fb);
  262. return NULL;
  263. }
  264. #else /* ifndef CONFIG_DM_VIDEO */
  265. static int mxs_of_get_timings(struct udevice *dev,
  266. struct display_timing *timings,
  267. u32 *bpp)
  268. {
  269. int ret = 0;
  270. u32 display_phandle;
  271. ofnode display_node;
  272. ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
  273. if (ret) {
  274. dev_err(dev, "required display property isn't provided\n");
  275. return -EINVAL;
  276. }
  277. display_node = ofnode_get_by_phandle(display_phandle);
  278. if (!ofnode_valid(display_node)) {
  279. dev_err(dev, "failed to find display subnode\n");
  280. return -EINVAL;
  281. }
  282. ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
  283. if (ret) {
  284. dev_err(dev,
  285. "required bits-per-pixel property isn't provided\n");
  286. return -EINVAL;
  287. }
  288. ret = ofnode_decode_display_timing(display_node, 0, timings);
  289. if (ret) {
  290. dev_err(dev, "failed to get any display timings\n");
  291. return -EINVAL;
  292. }
  293. return ret;
  294. }
  295. static int mxs_video_probe(struct udevice *dev)
  296. {
  297. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  298. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  299. struct display_timing timings;
  300. u32 bpp = 0;
  301. u32 fb_start, fb_end;
  302. int ret;
  303. debug("%s() plat: base 0x%lx, size 0x%x\n",
  304. __func__, plat->base, plat->size);
  305. ret = mxs_of_get_timings(dev, &timings, &bpp);
  306. if (ret)
  307. return ret;
  308. ret = mxs_probe_common(dev, &timings, bpp, plat->base);
  309. if (ret)
  310. return ret;
  311. switch (bpp) {
  312. case 32:
  313. case 24:
  314. case 18:
  315. uc_priv->bpix = VIDEO_BPP32;
  316. break;
  317. case 16:
  318. uc_priv->bpix = VIDEO_BPP16;
  319. break;
  320. case 8:
  321. uc_priv->bpix = VIDEO_BPP8;
  322. break;
  323. default:
  324. dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
  325. return -EINVAL;
  326. }
  327. uc_priv->xsize = timings.hactive.typ;
  328. uc_priv->ysize = timings.vactive.typ;
  329. /* Enable dcache for the frame buffer */
  330. fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
  331. fb_end = plat->base + plat->size;
  332. fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
  333. mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
  334. DCACHE_WRITEBACK);
  335. video_set_flush_dcache(dev, true);
  336. gd->fb_base = plat->base;
  337. return ret;
  338. }
  339. static int mxs_video_bind(struct udevice *dev)
  340. {
  341. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  342. struct display_timing timings;
  343. u32 bpp = 0;
  344. u32 bytes_pp = 0;
  345. int ret;
  346. ret = mxs_of_get_timings(dev, &timings, &bpp);
  347. if (ret)
  348. return ret;
  349. switch (bpp) {
  350. case 32:
  351. case 24:
  352. case 18:
  353. bytes_pp = 4;
  354. break;
  355. case 16:
  356. bytes_pp = 2;
  357. break;
  358. case 8:
  359. bytes_pp = 1;
  360. break;
  361. default:
  362. dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
  363. return -EINVAL;
  364. }
  365. plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
  366. return 0;
  367. }
  368. static int mxs_video_remove(struct udevice *dev)
  369. {
  370. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  371. mxs_remove_common(plat->base);
  372. return 0;
  373. }
  374. static const struct udevice_id mxs_video_ids[] = {
  375. { .compatible = "fsl,imx23-lcdif" },
  376. { .compatible = "fsl,imx28-lcdif" },
  377. { .compatible = "fsl,imx7ulp-lcdif" },
  378. { .compatible = "fsl,imxrt-lcdif" },
  379. { /* sentinel */ }
  380. };
  381. U_BOOT_DRIVER(mxs_video) = {
  382. .name = "mxs_video",
  383. .id = UCLASS_VIDEO,
  384. .of_match = mxs_video_ids,
  385. .bind = mxs_video_bind,
  386. .probe = mxs_video_probe,
  387. .remove = mxs_video_remove,
  388. .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
  389. };
  390. #endif /* ifndef CONFIG_DM_VIDEO */