logicore_dp_tx.c 66 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * logicore_dp_tx.c
  4. *
  5. * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source)
  6. * based on Xilinx dp_v3_1 driver sources, updated to dp_v4_0
  7. *
  8. * (C) Copyright 2016
  9. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  10. */
  11. #include <common.h>
  12. #include <clk.h>
  13. #include <display.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <linux/delay.h>
  17. #include "axi.h"
  18. #include "logicore_dp_dpcd.h"
  19. #include "logicore_dp_tx.h"
  20. #include "logicore_dp_tx_regif.h"
  21. /* Default AXI clock frequency value */
  22. #define S_AXI_CLK_DEFAULT 100000000
  23. /* Default DP phy clock value */
  24. #define PHY_CLOCK_SELECT_DEFAULT PHY_CLOCK_SELECT_540GBPS
  25. /* The maximum voltage swing level is 3 */
  26. #define MAXIMUM_VS_LEVEL 3
  27. /* The maximum pre-emphasis level is 3 */
  28. #define MAXIMUM_PE_LEVEL 3
  29. /* Error out if an AUX request yields a defer reply more than 50 times */
  30. #define AUX_MAX_DEFER_COUNT 50
  31. /* Error out if an AUX request times out more than 50 times awaiting a reply */
  32. #define AUX_MAX_TIMEOUT_COUNT 50
  33. /* Error out if checking for a connected device times out more than 50 times */
  34. #define IS_CONNECTED_MAX_TIMEOUT_COUNT 50
  35. /**
  36. * enum link_training_states - States for link training state machine
  37. * @TS_CLOCK_RECOVERY: State for clock recovery
  38. * @TS_CHANNEL_EQUALIZATION: State for channel equalization
  39. * @TS_ADJUST_LINK_RATE: State where link rate is reduced in reaction to
  40. * failed link training
  41. * @TS_ADJUST_LANE_COUNT: State where lane count is reduced in reaction to
  42. * failed link training
  43. * @TS_FAILURE: State of link training failure
  44. * @TS_SUCCESS:: State for successfully completed link training
  45. */
  46. enum link_training_states {
  47. TS_CLOCK_RECOVERY,
  48. TS_CHANNEL_EQUALIZATION,
  49. TS_ADJUST_LINK_RATE,
  50. TS_ADJUST_LANE_COUNT,
  51. TS_FAILURE,
  52. TS_SUCCESS
  53. };
  54. /**
  55. * struct aux_transaction - Description of an AUX channel transaction
  56. * @cmd_code: Command code of the transaction
  57. * @num_bytes: The number of bytes in the transaction's payload data
  58. * @address: The DPCD address of the transaction
  59. * @data: Payload data of the AUX channel transaction
  60. */
  61. struct aux_transaction {
  62. u16 cmd_code;
  63. u8 num_bytes;
  64. u32 address;
  65. u8 *data;
  66. };
  67. /**
  68. * struct main_stream_attributes - Main stream attributes
  69. * @pixel_clock_hz: Pixel clock of the stream (in Hz)
  70. * @misc_0: Miscellaneous stream attributes 0 as specified
  71. * by the DisplayPort 1.2 specification
  72. * @misc_1: Miscellaneous stream attributes 1 as specified
  73. * by the DisplayPort 1.2 specification
  74. * @n_vid: N value for the video stream
  75. * @m_vid: M value used to recover the video clock from the
  76. * link clock
  77. * @user_pixel_width: Width of the user data input port
  78. * @data_per_lane: Used to translate the number of pixels per line
  79. * to the native internal 16-bit datapath
  80. * @avg_bytes_per_tu: Average number of bytes per transfer unit,
  81. * scaled up by a factor of 1000
  82. * @transfer_unit_size: Size of the transfer unit in the framing logic
  83. * In MST mode, this is also the number of time
  84. * slots that are alloted in the payload ID table
  85. * @init_wait: Number of initial wait cycles at the start of a
  86. * new line by the framing logic
  87. * @bits_per_color: Bits per color component
  88. * @component_format: The component format currently in use by the
  89. * video stream
  90. * @dynamic_range: The dynamic range currently in use by the video
  91. * stream
  92. * @y_cb_cr_colorimetry: The YCbCr colorimetry currently in use by the
  93. * video stream
  94. * @synchronous_clock_mode: Synchronous clock mode is currently in use by
  95. * the video stream
  96. * @override_user_pixel_width: If set to 1, the value stored for
  97. * user_pixel_width will be used as the pixel width
  98. * @h_start: Horizontal blank start (pixels)
  99. * @h_active: Horizontal active resolution (pixels)
  100. * @h_sync_width: Horizontal sync width (pixels)
  101. * @h_total: Horizontal total (pixels)
  102. * @h_sync_polarity: Horizontal sync polarity (0=neg|1=pos)
  103. * @v_start: Vertical blank start (in lines)
  104. * @v_active: Vertical active resolution (lines)
  105. * @v_sync_width: Vertical sync width (lines)
  106. * @v_total: Vertical total (lines)
  107. * @v_sync_polarity: Vertical sync polarity (0=neg|1=pos)
  108. *
  109. * All porch parameters have been removed, because our videodata is
  110. * hstart/vstart based, and there is no benefit in keeping the porches
  111. */
  112. struct main_stream_attributes {
  113. u32 pixel_clock_hz;
  114. u32 misc_0;
  115. u32 misc_1;
  116. u32 n_vid;
  117. //u32 m_vid;
  118. u32 user_pixel_width;
  119. u32 data_per_lane;
  120. u32 avg_bytes_per_tu;
  121. u32 transfer_unit_size;
  122. u32 init_wait;
  123. u32 bits_per_color;
  124. u8 component_format;
  125. u8 dynamic_range;
  126. u8 y_cb_cr_colorimetry;
  127. u8 synchronous_clock_mode;
  128. u8 override_user_pixel_width;
  129. u32 h_start;
  130. u16 h_active;
  131. u16 h_sync_width;
  132. u16 h_total;
  133. bool h_sync_polarity;
  134. u32 v_start;
  135. u16 v_active;
  136. u16 v_sync_width;
  137. u16 v_total;
  138. bool v_sync_polarity;
  139. };
  140. /**
  141. * struct link_config - Description of link configuration
  142. * @lane_count: Currently selected lane count for this link
  143. * @link_rate: Currently selected link rate for this link
  144. * @scrambler_en: Flag to determine whether the scrambler is
  145. * enabled for this link
  146. * @enhanced_framing_mode: Flag to determine whether enhanced framing
  147. * mode is active for this link
  148. * @max_lane_count: Maximum lane count for this link
  149. * @max_link_rate: Maximum link rate for this link
  150. * @support_enhanced_framing_mode: Flag to indicate whether the link supports
  151. * enhanced framing mode
  152. * @vs_level: Voltage swing for each lane
  153. * @pe_level: Pre-emphasis/cursor level for each lane
  154. */
  155. struct link_config {
  156. u8 lane_count;
  157. u8 link_rate;
  158. bool scrambler_en;
  159. bool enhanced_framing_mode;
  160. u8 max_lane_count;
  161. u8 max_link_rate;
  162. bool support_enhanced_framing_mode;
  163. u8 vs_level;
  164. u8 pe_level;
  165. };
  166. /**
  167. * struct dp_tx - Private data structure of LogiCore DP TX devices
  168. *
  169. * @base: Address of register base of device
  170. * @s_axi_clk: The AXI clock frequency in Hz
  171. * @train_adaptive: Use adaptive link trainig (i.e. successively reduce
  172. * link rate and/or lane count) for this device
  173. * @max_link_rate: Maximum link rate for this device
  174. * @max_lane_count: Maximum lane count for this device
  175. * @dpcd_rx_caps: RX device's status registers, see below
  176. * @lane_status_ajd_reqs: Lane status and adjustment requests information for
  177. * this device
  178. * @link_config: The link configuration for this device
  179. * @main_stream_attributes: MSA set for this device
  180. *
  181. * dpcd_rx_caps is a raw read of the RX device's status registers. The first 4
  182. * bytes correspond to the lane status associated with clock recovery, channel
  183. * equalization, symbol lock, and interlane alignment. The remaining 2 bytes
  184. * represent the pre-emphasis and voltage swing level adjustments requested by
  185. * the RX device.
  186. */
  187. struct dp_tx {
  188. u32 base;
  189. u32 s_axi_clk;
  190. bool train_adaptive;
  191. u8 max_link_rate;
  192. u8 max_lane_count;
  193. u8 dpcd_rx_caps[16];
  194. u8 lane_status_ajd_reqs[6];
  195. struct link_config link_config;
  196. struct main_stream_attributes main_stream_attributes;
  197. };
  198. /*
  199. * Internal API
  200. */
  201. /**
  202. * get_reg() - Read a register of a LogiCore DP TX device
  203. * @dev: The LogiCore DP TX device in question
  204. * @reg: The offset of the register to read
  205. *
  206. * Return: The read register value
  207. */
  208. static u32 get_reg(struct udevice *dev, u32 reg)
  209. {
  210. struct dp_tx *dp_tx = dev_get_priv(dev);
  211. u32 value = 0;
  212. int res;
  213. /* TODO(mario.six@gdsys.cc): error handling */
  214. res = axi_read(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);
  215. if (res < 0)
  216. printf("%s() failed; res = %d\n", __func__, res);
  217. return value;
  218. }
  219. /**
  220. * set_reg() - Write a register of a LogiCore DP TX device
  221. * @dev: The LogiCore DP TX device in question
  222. * @reg: The offset of the register to write
  223. * @value: The value to write to the register
  224. */
  225. static void set_reg(struct udevice *dev, u32 reg, u32 value)
  226. {
  227. struct dp_tx *dp_tx = dev_get_priv(dev);
  228. axi_write(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);
  229. }
  230. /**
  231. * is_connected() - Check if there is a connected RX device
  232. * @dev: The LogiCore DP TX device in question
  233. *
  234. * The Xilinx original calls msleep_interruptible at least once, ignoring
  235. * status.
  236. *
  237. * Return: true if a connected RX device was detected, false otherwise
  238. */
  239. static bool is_connected(struct udevice *dev)
  240. {
  241. u8 retries = 0;
  242. do {
  243. int status = get_reg(dev, REG_INTERRUPT_SIG_STATE) &
  244. INTERRUPT_SIG_STATE_HPD_STATE_MASK;
  245. if (status)
  246. return true;
  247. udelay(1000);
  248. } while (retries++ < IS_CONNECTED_MAX_TIMEOUT_COUNT);
  249. return false;
  250. }
  251. /**
  252. * wait_phy_ready() - Wait for the DisplayPort PHY to come out of reset
  253. * @dev: The LogiCore DP TX device in question
  254. * @mask: Bit mask specifying which bit in the status register should be waited
  255. * for
  256. *
  257. * Return: 0 if wait succeeded, -ve if error occurred
  258. */
  259. static int wait_phy_ready(struct udevice *dev, u32 mask)
  260. {
  261. u16 timeout = 20000;
  262. u32 phy_status;
  263. /* Wait until the PHY is ready. */
  264. do {
  265. phy_status = get_reg(dev, REG_PHY_STATUS) & mask;
  266. /* Protect against an infinite loop. */
  267. if (!timeout--)
  268. return -ETIMEDOUT;
  269. udelay(20);
  270. } while (phy_status != mask);
  271. return 0;
  272. }
  273. /* AUX channel access */
  274. /**
  275. * aux_wait_ready() - Wait until another request is no longer in progress
  276. * @dev: The LogiCore DP TX device in question
  277. *
  278. * Return: 0 if wait succeeded, -ve if error occurred
  279. */
  280. static int aux_wait_ready(struct udevice *dev)
  281. {
  282. int status;
  283. u32 timeout = 100;
  284. /* Wait until the DisplayPort TX core is ready. */
  285. do {
  286. status = get_reg(dev, REG_INTERRUPT_SIG_STATE);
  287. /* Protect against an infinite loop. */
  288. if (!timeout--)
  289. return -ETIMEDOUT;
  290. udelay(20);
  291. } while (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK);
  292. return 0;
  293. }
  294. /**
  295. * aux_wait_reply() - Wait for reply on AUX channel
  296. * @dev: The LogiCore DP TX device in question
  297. *
  298. * Wait for a reply indicating that the most recent AUX request
  299. * has been received by the RX device.
  300. *
  301. * Return: 0 if wait succeeded, -ve if error occurred
  302. */
  303. static int aux_wait_reply(struct udevice *dev)
  304. {
  305. u32 timeout = 100;
  306. while (timeout > 0) {
  307. int status = get_reg(dev, REG_REPLY_STATUS);
  308. /* Check for error. */
  309. if (status & REPLY_STATUS_REPLY_ERROR_MASK)
  310. return -ETIMEDOUT;
  311. /* Check for a reply. */
  312. if ((status & REPLY_STATUS_REPLY_RECEIVED_MASK) &&
  313. !(status &
  314. REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) &&
  315. !(status &
  316. REPLY_STATUS_REPLY_IN_PROGRESS_MASK)) {
  317. return 0;
  318. }
  319. timeout--;
  320. udelay(20);
  321. }
  322. return -ETIMEDOUT;
  323. }
  324. /**
  325. * aux_request_send() - Send request on the AUX channel
  326. * @dev: The LogiCore DP TX device in question
  327. * @request: The request to send
  328. *
  329. * Submit the supplied AUX request to the RX device over the AUX
  330. * channel by writing the command, the destination address, (the write buffer
  331. * for write commands), and the data size to the DisplayPort TX core.
  332. *
  333. * This is the lower-level sending routine, which is called by aux_request().
  334. *
  335. * Return: 0 if request was sent successfully, -ve on error
  336. */
  337. static int aux_request_send(struct udevice *dev,
  338. struct aux_transaction *request)
  339. {
  340. u32 timeout_count;
  341. int status;
  342. u8 index;
  343. /* Ensure that any pending AUX transactions have completed. */
  344. timeout_count = 0;
  345. do {
  346. status = get_reg(dev, REG_REPLY_STATUS);
  347. udelay(20);
  348. timeout_count++;
  349. if (timeout_count >= AUX_MAX_TIMEOUT_COUNT)
  350. return -ETIMEDOUT;
  351. } while ((status & REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) ||
  352. (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK));
  353. set_reg(dev, REG_AUX_ADDRESS, request->address);
  354. if (request->cmd_code == AUX_CMD_WRITE ||
  355. request->cmd_code == AUX_CMD_I2C_WRITE ||
  356. request->cmd_code == AUX_CMD_I2C_WRITE_MOT) {
  357. /* Feed write data into the DisplayPort TX core's write FIFO. */
  358. for (index = 0; index < request->num_bytes; index++) {
  359. set_reg(dev,
  360. REG_AUX_WRITE_FIFO, request->data[index]);
  361. }
  362. }
  363. /* Submit the command and the data size. */
  364. set_reg(dev, REG_AUX_CMD,
  365. ((request->cmd_code << AUX_CMD_SHIFT) |
  366. ((request->num_bytes - 1) &
  367. AUX_CMD_NBYTES_TRANSFER_MASK)));
  368. /* Check for a reply from the RX device to the submitted request. */
  369. status = aux_wait_reply(dev);
  370. if (status)
  371. /* Waiting for a reply timed out. */
  372. return -ETIMEDOUT;
  373. /* Analyze the reply. */
  374. status = get_reg(dev, REG_AUX_REPLY_CODE);
  375. if (status == AUX_REPLY_CODE_DEFER ||
  376. status == AUX_REPLY_CODE_I2C_DEFER) {
  377. /* The request was deferred. */
  378. return -EAGAIN;
  379. } else if ((status == AUX_REPLY_CODE_NACK) ||
  380. (status == AUX_REPLY_CODE_I2C_NACK)) {
  381. /* The request was not acknowledged. */
  382. return -EIO;
  383. }
  384. /* The request was acknowledged. */
  385. if (request->cmd_code == AUX_CMD_READ ||
  386. request->cmd_code == AUX_CMD_I2C_READ ||
  387. request->cmd_code == AUX_CMD_I2C_READ_MOT) {
  388. /* Wait until all data has been received. */
  389. timeout_count = 0;
  390. do {
  391. status = get_reg(dev, REG_REPLY_DATA_COUNT);
  392. udelay(100);
  393. timeout_count++;
  394. if (timeout_count >= AUX_MAX_TIMEOUT_COUNT)
  395. return -ETIMEDOUT;
  396. } while (status != request->num_bytes);
  397. /* Obtain the read data from the reply FIFO. */
  398. for (index = 0; index < request->num_bytes; index++)
  399. request->data[index] = get_reg(dev, REG_AUX_REPLY_DATA);
  400. }
  401. return 0;
  402. }
  403. /**
  404. * aux_request() - Submit request on the AUX channel
  405. * @dev: The LogiCore DP TX device in question
  406. * @request: The request to submit
  407. *
  408. * Submit the supplied AUX request to the RX device over the AUX
  409. * channel. If waiting for a reply times out, or if the DisplayPort TX core
  410. * indicates that the request was deferred, the request is sent again (up to a
  411. * maximum specified by AUX_MAX_DEFER_COUNT|AUX_MAX_TIMEOUT_COUNT).
  412. *
  413. * Return: 0 if request was submitted successfully, -ve on error
  414. */
  415. static int aux_request(struct udevice *dev, struct aux_transaction *request)
  416. {
  417. u32 defer_count = 0;
  418. u32 timeout_count = 0;
  419. while ((defer_count < AUX_MAX_DEFER_COUNT) &&
  420. (timeout_count < AUX_MAX_TIMEOUT_COUNT)) {
  421. int status = aux_wait_ready(dev);
  422. if (status) {
  423. /* The RX device isn't ready yet. */
  424. timeout_count++;
  425. continue;
  426. }
  427. status = aux_request_send(dev, request);
  428. if (status == -EAGAIN) {
  429. /* The request was deferred. */
  430. defer_count++;
  431. } else if (status == -ETIMEDOUT) {
  432. /* Waiting for a reply timed out. */
  433. timeout_count++;
  434. } else {
  435. /*
  436. * -EIO indicates that the request was NACK'ed,
  437. * 0 indicates that the request was ACK'ed.
  438. */
  439. return status;
  440. }
  441. udelay(100);
  442. }
  443. /* The request was not successfully received by the RX device. */
  444. return -ETIMEDOUT;
  445. }
  446. /**
  447. * aux_common() - Common (read/write) AUX communication transmission
  448. * @dev: The LogiCore DP TX device in question
  449. * @cmd_type: Command code of the transaction
  450. * @address: The DPCD address of the transaction
  451. * @num_bytes: Number of bytes in the payload data
  452. * @data: The payload data of the AUX command
  453. *
  454. * Common sequence of submitting an AUX command for AUX read, AUX write,
  455. * I2C-over-AUX read, and I2C-over-AUX write transactions. If required, the
  456. * reads and writes are split into multiple requests, each acting on a maximum
  457. * of 16 bytes.
  458. *
  459. * Return: 0 if OK, -ve on error
  460. */
  461. static int aux_common(struct udevice *dev, u32 cmd_type, u32 address,
  462. u32 num_bytes, u8 *data)
  463. {
  464. struct aux_transaction request;
  465. u32 bytes_left;
  466. /*
  467. * Set the start address for AUX transactions. For I2C transactions,
  468. * this is the address of the I2C bus.
  469. */
  470. request.address = address;
  471. bytes_left = num_bytes;
  472. while (bytes_left) {
  473. int status;
  474. request.cmd_code = cmd_type;
  475. if (cmd_type == AUX_CMD_READ ||
  476. cmd_type == AUX_CMD_WRITE) {
  477. /* Increment address for normal AUX transactions. */
  478. request.address = address + (num_bytes - bytes_left);
  479. }
  480. /* Increment the pointer to the supplied data buffer. */
  481. request.data = &data[num_bytes - bytes_left];
  482. request.num_bytes = (bytes_left > 16) ? 16 : bytes_left;
  483. bytes_left -= request.num_bytes;
  484. if (cmd_type == AUX_CMD_I2C_READ && bytes_left) {
  485. /*
  486. * Middle of a transaction I2C read request. Override
  487. * the command code that was set to cmd_type.
  488. */
  489. request.cmd_code = AUX_CMD_I2C_READ_MOT;
  490. } else if ((cmd_type == AUX_CMD_I2C_WRITE) && bytes_left) {
  491. /*
  492. * Middle of a transaction I2C write request. Override
  493. * the command code that was set to cmd_type.
  494. */
  495. request.cmd_code = AUX_CMD_I2C_WRITE_MOT;
  496. }
  497. status = aux_request(dev, &request);
  498. if (status)
  499. return status;
  500. }
  501. return 0;
  502. }
  503. /**
  504. * aux_read() - Issue AUX read request
  505. * @dev: The LogiCore DP TX device in question
  506. * @dpcd_address: The DPCD address to read from
  507. * @bytes_to_read: Number of bytes to read
  508. * @read_data: Buffer to receive the read data
  509. *
  510. * Issue a read request over the AUX channel that will read from the RX
  511. * device's DisplayPort Configuration data (DPCD) address space. The read
  512. * message will be divided into multiple transactions which read a maximum of
  513. * 16 bytes each.
  514. *
  515. * Return: 0 if read operation was successful, -ve on error
  516. */
  517. static int aux_read(struct udevice *dev, u32 dpcd_address, u32 bytes_to_read,
  518. void *read_data)
  519. {
  520. int status;
  521. if (!is_connected(dev))
  522. return -ENODEV;
  523. /* Send AUX read transaction. */
  524. status = aux_common(dev, AUX_CMD_READ, dpcd_address,
  525. bytes_to_read, (u8 *)read_data);
  526. return status;
  527. }
  528. /**
  529. * aux_write() - Issue AUX write request
  530. * @dev: The LogiCore DP TX device in question
  531. * @dpcd_address: The DPCD address to write to
  532. * @bytes_to_write: Number of bytes to write
  533. * @write_data: Buffer containig data to be written
  534. *
  535. * Issue a write request over the AUX channel that will write to
  536. * the RX device's DisplayPort Configuration data (DPCD) address space. The
  537. * write message will be divided into multiple transactions which write a
  538. * maximum of 16 bytes each.
  539. *
  540. * Return: 0 if write operation was successful, -ve on error
  541. */
  542. static int aux_write(struct udevice *dev, u32 dpcd_address, u32 bytes_to_write,
  543. void *write_data)
  544. {
  545. int status;
  546. if (!is_connected(dev))
  547. return -ENODEV;
  548. /* Send AUX write transaction. */
  549. status = aux_common(dev, AUX_CMD_WRITE, dpcd_address,
  550. bytes_to_write, (u8 *)write_data);
  551. return status;
  552. }
  553. /* Core initialization */
  554. /**
  555. * initialize() - Initialize a LogiCore DP TX device
  556. * @dev: The LogiCore DP TX device in question
  557. *
  558. * Return: Always 0
  559. */
  560. static int initialize(struct udevice *dev)
  561. {
  562. struct dp_tx *dp_tx = dev_get_priv(dev);
  563. u32 val;
  564. u32 phy_config;
  565. unsigned int k;
  566. /* place the PHY (and GTTXRESET) into reset. */
  567. phy_config = get_reg(dev, REG_PHY_CONFIG);
  568. set_reg(dev, REG_PHY_CONFIG, phy_config | PHY_CONFIG_GT_ALL_RESET_MASK);
  569. /* reset the video streams and AUX logic. */
  570. set_reg(dev, REG_SOFT_RESET,
  571. SOFT_RESET_VIDEO_STREAM_ALL_MASK |
  572. SOFT_RESET_AUX_MASK);
  573. /* disable the DisplayPort TX core. */
  574. set_reg(dev, REG_ENABLE, 0);
  575. /* set the clock divider. */
  576. val = get_reg(dev, REG_AUX_CLK_DIVIDER);
  577. val &= ~AUX_CLK_DIVIDER_VAL_MASK;
  578. val |= dp_tx->s_axi_clk / 1000000;
  579. set_reg(dev, REG_AUX_CLK_DIVIDER, val);
  580. /* set the DisplayPort TX core's clock speed. */
  581. set_reg(dev, REG_PHY_CLOCK_SELECT, PHY_CLOCK_SELECT_DEFAULT);
  582. /* bring the PHY (and GTTXRESET) out of reset. */
  583. set_reg(dev, REG_PHY_CONFIG,
  584. phy_config & ~PHY_CONFIG_GT_ALL_RESET_MASK);
  585. /* enable the DisplayPort TX core. */
  586. set_reg(dev, REG_ENABLE, 1);
  587. /* Unmask Hot-Plug-Detect (HPD) interrupts. */
  588. set_reg(dev, REG_INTERRUPT_MASK,
  589. ~INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK &
  590. ~INTERRUPT_MASK_HPD_EVENT_MASK &
  591. ~INTERRUPT_MASK_HPD_IRQ_MASK);
  592. for (k = 0; k < 4; k++) {
  593. /* Disable pre-cursor levels. */
  594. set_reg(dev, REG_PHY_PRECURSOR_LANE_0 + 4 * k, 0);
  595. /* Write default voltage swing levels to the TX registers. */
  596. set_reg(dev, REG_PHY_VOLTAGE_DIFF_LANE_0 + 4 * k, 0);
  597. /* Write default pre-emphasis levels to the TX registers. */
  598. set_reg(dev, REG_PHY_POSTCURSOR_LANE_0 + 4 * k, 0);
  599. }
  600. return 0;
  601. }
  602. /**
  603. * is_link_rate_valid() - Check if given link rate is valif for device
  604. * @dev: The LogiCore DP TX device in question
  605. * @link_rate: The link rate to be checked for validity
  606. *
  607. * Return: true if he supplied link rate is valid, false otherwise
  608. */
  609. static bool is_link_rate_valid(struct udevice *dev, u8 link_rate)
  610. {
  611. struct dp_tx *dp_tx = dev_get_priv(dev);
  612. bool valid = true;
  613. if (link_rate != LINK_BW_SET_162GBPS &&
  614. link_rate != LINK_BW_SET_270GBPS &&
  615. link_rate != LINK_BW_SET_540GBPS)
  616. valid = false;
  617. else if (link_rate > dp_tx->link_config.max_link_rate)
  618. valid = false;
  619. return valid;
  620. }
  621. /**
  622. * is_lane_count_valid() - Check if given lane count is valif for device
  623. * @dev: The LogiCore DP TX device in question
  624. * @lane_count: The lane count to be checked for validity
  625. *
  626. * Return: true if he supplied lane count is valid, false otherwise
  627. */
  628. static bool is_lane_count_valid(struct udevice *dev, u8 lane_count)
  629. {
  630. struct dp_tx *dp_tx = dev_get_priv(dev);
  631. bool valid = true;
  632. if (lane_count != LANE_COUNT_SET_1 &&
  633. lane_count != LANE_COUNT_SET_2 &&
  634. lane_count != LANE_COUNT_SET_4)
  635. valid = false;
  636. else if (lane_count > dp_tx->link_config.max_lane_count)
  637. valid = false;
  638. return valid;
  639. }
  640. /**
  641. * get_rx_capabilities() - Check if capabilities of RX device are valid for TX
  642. * device
  643. * @dev: The LogiCore DP TX device in question
  644. *
  645. * Return: 0 if the capabilities of the RX device are valid for the TX device,
  646. * -ve if not, of an error occurred during capability determination
  647. */
  648. static int get_rx_capabilities(struct udevice *dev)
  649. {
  650. struct dp_tx *dp_tx = dev_get_priv(dev);
  651. int status;
  652. u8 rx_max_link_rate;
  653. u8 rx_max_lane_count;
  654. if (!is_connected(dev))
  655. return -ENODEV;
  656. status = aux_read(dev, DPCD_RECEIVER_CAP_FIELD_START, 16,
  657. dp_tx->dpcd_rx_caps);
  658. if (status)
  659. return -EIO;
  660. rx_max_link_rate = dp_tx->dpcd_rx_caps[DPCD_MAX_LINK_RATE];
  661. rx_max_lane_count = dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] &
  662. DPCD_MAX_LANE_COUNT_MASK;
  663. dp_tx->link_config.max_link_rate =
  664. (rx_max_link_rate > dp_tx->max_link_rate) ?
  665. dp_tx->max_link_rate : rx_max_link_rate;
  666. if (!is_link_rate_valid(dev, rx_max_link_rate))
  667. return -EINVAL;
  668. dp_tx->link_config.max_lane_count =
  669. (rx_max_lane_count > dp_tx->max_lane_count) ?
  670. dp_tx->max_lane_count : rx_max_lane_count;
  671. if (!is_lane_count_valid(dev, rx_max_lane_count))
  672. return -EINVAL;
  673. dp_tx->link_config.support_enhanced_framing_mode =
  674. dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] &
  675. DPCD_ENHANCED_FRAME_SUPPORT_MASK;
  676. return 0;
  677. }
  678. /**
  679. * enable_main_link() - Switch on main link for a device
  680. * @dev: The LogiCore DP TX device in question
  681. */
  682. static void enable_main_link(struct udevice *dev)
  683. {
  684. /* reset the scrambler. */
  685. set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);
  686. /* enable the main stream. */
  687. set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x1);
  688. }
  689. /**
  690. * disable_main_link() - Switch off main link for a device
  691. * @dev: The LogiCore DP TX device in question
  692. */
  693. static void disable_main_link(struct udevice *dev)
  694. {
  695. /* reset the scrambler. */
  696. set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);
  697. /* Disable the main stream. */
  698. set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x0);
  699. }
  700. /**
  701. * reset_dp_phy() - Reset a device
  702. * @dev: The LogiCore DP TX device in question
  703. * @reset: Bit mask determining which bits in the device's config register
  704. * should be set for the reset
  705. */
  706. static void reset_dp_phy(struct udevice *dev, u32 reset)
  707. {
  708. struct dp_tx *dp_tx = dev_get_priv(dev);
  709. u32 val;
  710. set_reg(dev, REG_ENABLE, 0x0);
  711. val = get_reg(dev, REG_PHY_CONFIG);
  712. /* Apply reset. */
  713. set_reg(dev, REG_PHY_CONFIG, val | reset);
  714. /* Remove reset. */
  715. set_reg(dev, REG_PHY_CONFIG, val);
  716. /* Wait for the PHY to be ready. */
  717. wait_phy_ready(dev, phy_status_lanes_ready_mask(dp_tx->max_lane_count));
  718. set_reg(dev, REG_ENABLE, 0x1);
  719. }
  720. /**
  721. * set_enhanced_frame_mode() - Enable/Disable enhanced frame mode
  722. * @dev: The LogiCore DP TX device in question
  723. * @enable: Flag to determine whether to enable (1) or disable (0) the enhanced
  724. * frame mode
  725. *
  726. * Enable or disable the enhanced framing symbol sequence for
  727. * both the DisplayPort TX core and the RX device.
  728. *
  729. * Return: 0 if enabling/disabling the enhanced frame mode was successful, -ve
  730. * on error
  731. */
  732. static int set_enhanced_frame_mode(struct udevice *dev, u8 enable)
  733. {
  734. struct dp_tx *dp_tx = dev_get_priv(dev);
  735. int status;
  736. u8 val;
  737. if (!is_connected(dev))
  738. return -ENODEV;
  739. if (dp_tx->link_config.support_enhanced_framing_mode)
  740. dp_tx->link_config.enhanced_framing_mode = enable;
  741. else
  742. dp_tx->link_config.enhanced_framing_mode = false;
  743. /* Write enhanced frame mode enable to the DisplayPort TX core. */
  744. set_reg(dev, REG_ENHANCED_FRAME_EN,
  745. dp_tx->link_config.enhanced_framing_mode);
  746. /* Write enhanced frame mode enable to the RX device. */
  747. status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
  748. if (status)
  749. return -EIO;
  750. if (dp_tx->link_config.enhanced_framing_mode)
  751. val |= DPCD_ENHANCED_FRAME_EN_MASK;
  752. else
  753. val &= ~DPCD_ENHANCED_FRAME_EN_MASK;
  754. status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
  755. if (status)
  756. return -EIO;
  757. return 0;
  758. }
  759. /**
  760. * set_lane_count() - Set the lane count
  761. * @dev: The LogiCore DP TX device in question
  762. * @lane_count: Lane count to set
  763. *
  764. * Set the number of lanes to be used by the main link for both
  765. * the DisplayPort TX core and the RX device.
  766. *
  767. * Return: 0 if setting the lane count was successful, -ve on error
  768. */
  769. static int set_lane_count(struct udevice *dev, u8 lane_count)
  770. {
  771. struct dp_tx *dp_tx = dev_get_priv(dev);
  772. int status;
  773. u8 val;
  774. if (!is_connected(dev))
  775. return -ENODEV;
  776. printf(" set lane count to %u\n", lane_count);
  777. dp_tx->link_config.lane_count = lane_count;
  778. /* Write the new lane count to the DisplayPort TX core. */
  779. set_reg(dev, REG_LANE_COUNT_SET, dp_tx->link_config.lane_count);
  780. /* Write the new lane count to the RX device. */
  781. status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
  782. if (status)
  783. return -EIO;
  784. val &= ~DPCD_LANE_COUNT_SET_MASK;
  785. val |= dp_tx->link_config.lane_count;
  786. status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
  787. if (status)
  788. return -EIO;
  789. return 0;
  790. }
  791. /**
  792. * set_clk_speed() - Set DP phy clock speed
  793. * @dev: The LogiCore DP TX device in question
  794. * @speed: The clock frquency to set (one of PHY_CLOCK_SELECT_*)
  795. *
  796. * Set the clock frequency for the DisplayPort PHY corresponding to a desired
  797. * data rate.
  798. *
  799. * Return: 0 if setting the DP phy clock speed was successful, -ve on error
  800. */
  801. static int set_clk_speed(struct udevice *dev, u32 speed)
  802. {
  803. struct dp_tx *dp_tx = dev_get_priv(dev);
  804. int status;
  805. u32 val;
  806. u32 mask;
  807. /* Disable the DisplayPort TX core first. */
  808. val = get_reg(dev, REG_ENABLE);
  809. set_reg(dev, REG_ENABLE, 0x0);
  810. /* Change speed of the feedback clock. */
  811. set_reg(dev, REG_PHY_CLOCK_SELECT, speed);
  812. /* Re-enable the DisplayPort TX core if it was previously enabled. */
  813. if (val)
  814. set_reg(dev, REG_ENABLE, 0x1);
  815. /* Wait until the PHY is ready. */
  816. mask = phy_status_lanes_ready_mask(dp_tx->max_lane_count);
  817. status = wait_phy_ready(dev, mask);
  818. if (status)
  819. return -EIO;
  820. return 0;
  821. }
  822. /**
  823. * set_link_rate() - Set the link rate
  824. * @dev: The LogiCore DP TX device in question
  825. * @link_rate: The link rate to set (one of LINK_BW_SET_*)
  826. *
  827. * Set the data rate to be used by the main link for both the DisplayPort TX
  828. * core and the RX device.
  829. *
  830. * Return: 0 if setting the link rate was successful, -ve on error
  831. */
  832. static int set_link_rate(struct udevice *dev, u8 link_rate)
  833. {
  834. struct dp_tx *dp_tx = dev_get_priv(dev);
  835. int status;
  836. /* Write a corresponding clock frequency to the DisplayPort TX core. */
  837. switch (link_rate) {
  838. case LINK_BW_SET_162GBPS:
  839. printf(" set link rate to 1.62 Gb/s\n");
  840. status = set_clk_speed(dev, PHY_CLOCK_SELECT_162GBPS);
  841. break;
  842. case LINK_BW_SET_270GBPS:
  843. printf(" set link rate to 2.70 Gb/s\n");
  844. status = set_clk_speed(dev, PHY_CLOCK_SELECT_270GBPS);
  845. break;
  846. case LINK_BW_SET_540GBPS:
  847. printf(" set link rate to 5.40 Gb/s\n");
  848. status = set_clk_speed(dev, PHY_CLOCK_SELECT_540GBPS);
  849. break;
  850. default:
  851. return -EINVAL;
  852. }
  853. if (status)
  854. return -EIO;
  855. dp_tx->link_config.link_rate = link_rate;
  856. /* Write new link rate to the DisplayPort TX core. */
  857. set_reg(dev, REG_LINK_BW_SET, dp_tx->link_config.link_rate);
  858. /* Write new link rate to the RX device. */
  859. status = aux_write(dev, DPCD_LINK_BW_SET, 1,
  860. &dp_tx->link_config.link_rate);
  861. if (status)
  862. return -EIO;
  863. return 0;
  864. }
  865. /* Link training */
  866. /**
  867. * get_training_delay() - Get training delay
  868. * @dev: The LogiCore DP TX device in question
  869. * @training_state: The training state for which the required training delay
  870. * should be queried
  871. *
  872. * Determine what the RX device's required training delay is for
  873. * link training.
  874. *
  875. * Return: The training delay in us
  876. */
  877. static int get_training_delay(struct udevice *dev, int training_state)
  878. {
  879. struct dp_tx *dp_tx = dev_get_priv(dev);
  880. u16 delay;
  881. switch (dp_tx->dpcd_rx_caps[DPCD_TRAIN_AUX_RD_INTERVAL]) {
  882. case DPCD_TRAIN_AUX_RD_INT_100_400US:
  883. if (training_state == TS_CLOCK_RECOVERY)
  884. /* delay for the clock recovery phase. */
  885. delay = 100;
  886. else
  887. /* delay for the channel equalization phase. */
  888. delay = 400;
  889. break;
  890. case DPCD_TRAIN_AUX_RD_INT_4MS:
  891. delay = 4000;
  892. break;
  893. case DPCD_TRAIN_AUX_RD_INT_8MS:
  894. delay = 8000;
  895. break;
  896. case DPCD_TRAIN_AUX_RD_INT_12MS:
  897. delay = 12000;
  898. break;
  899. case DPCD_TRAIN_AUX_RD_INT_16MS:
  900. delay = 16000;
  901. break;
  902. default:
  903. /* Default to 20 ms. */
  904. delay = 20000;
  905. break;
  906. }
  907. return delay;
  908. }
  909. /**
  910. * set_vswing_preemp() - Build AUX data to set voltage swing and pre-emphasis
  911. * @dev: The LogiCore DP TX device in question
  912. * @aux_data: Buffer to receive the built AUX data
  913. *
  914. * Build AUX data to set current voltage swing and pre-emphasis level settings;
  915. * the necessary data is taken from the link_config structure.
  916. */
  917. static void set_vswing_preemp(struct udevice *dev, u8 *aux_data)
  918. {
  919. struct dp_tx *dp_tx = dev_get_priv(dev);
  920. u8 data;
  921. u8 vs_level_rx = dp_tx->link_config.vs_level;
  922. u8 pe_level_rx = dp_tx->link_config.pe_level;
  923. /* Set up the data buffer for writing to the RX device. */
  924. data = (pe_level_rx << DPCD_TRAINING_LANEX_SET_PE_SHIFT) | vs_level_rx;
  925. /* The maximum voltage swing has been reached. */
  926. if (vs_level_rx == MAXIMUM_VS_LEVEL)
  927. data |= DPCD_TRAINING_LANEX_SET_MAX_VS_MASK;
  928. /* The maximum pre-emphasis level has been reached. */
  929. if (pe_level_rx == MAXIMUM_PE_LEVEL)
  930. data |= DPCD_TRAINING_LANEX_SET_MAX_PE_MASK;
  931. memset(aux_data, data, 4);
  932. }
  933. /**
  934. * adj_vswing_preemp() - Adjust voltage swing and pre-emphasis
  935. * @dev: The LogiCore DP TX device in question
  936. *
  937. * Set new voltage swing and pre-emphasis levels using the
  938. * adjustment requests obtained from the RX device.
  939. *
  940. * Return: 0 if voltage swing and pre-emphasis could be adjusted successfully,
  941. * -ve on error
  942. */
  943. static int adj_vswing_preemp(struct udevice *dev)
  944. {
  945. struct dp_tx *dp_tx = dev_get_priv(dev);
  946. int status;
  947. u8 index;
  948. u8 vs_level_adj_req[4];
  949. u8 pe_level_adj_req[4];
  950. u8 aux_data[4];
  951. u8 *ajd_reqs = &dp_tx->lane_status_ajd_reqs[4];
  952. /*
  953. * Analyze the adjustment requests for changes in voltage swing and
  954. * pre-emphasis levels.
  955. */
  956. vs_level_adj_req[0] = ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
  957. vs_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
  958. DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
  959. vs_level_adj_req[2] = ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
  960. vs_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
  961. DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
  962. pe_level_adj_req[0] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
  963. DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
  964. pe_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
  965. DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
  966. pe_level_adj_req[2] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
  967. DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
  968. pe_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
  969. DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
  970. /*
  971. * Change the drive settings to match the adjustment requests. Use the
  972. * greatest level requested.
  973. */
  974. dp_tx->link_config.vs_level = 0;
  975. dp_tx->link_config.pe_level = 0;
  976. for (index = 0; index < dp_tx->link_config.lane_count; index++) {
  977. if (vs_level_adj_req[index] > dp_tx->link_config.vs_level)
  978. dp_tx->link_config.vs_level = vs_level_adj_req[index];
  979. if (pe_level_adj_req[index] > dp_tx->link_config.pe_level)
  980. dp_tx->link_config.pe_level = pe_level_adj_req[index];
  981. }
  982. /*
  983. * Verify that the voltage swing and pre-emphasis combination is
  984. * allowed. Some combinations will result in a differential peak-to-peak
  985. * voltage that is outside the permissible range. See the VESA
  986. * DisplayPort v1.2 Specification, section 3.1.5.2.
  987. * The valid combinations are:
  988. * PE=0 PE=1 PE=2 PE=3
  989. * VS=0 valid valid valid valid
  990. * VS=1 valid valid valid
  991. * VS=2 valid valid
  992. * VS=3 valid
  993. *
  994. * NOTE:
  995. * Xilinix dp_v3_1 driver seems to have an off by one error when
  996. * limiting pe_level which is fixed here.
  997. */
  998. if (dp_tx->link_config.pe_level > (3 - dp_tx->link_config.vs_level))
  999. dp_tx->link_config.pe_level = 3 - dp_tx->link_config.vs_level;
  1000. /*
  1001. * Make the adjustments to both the DisplayPort TX core and the RX
  1002. * device.
  1003. */
  1004. set_vswing_preemp(dev, aux_data);
  1005. /*
  1006. * Write the voltage swing and pre-emphasis levels for each lane to the
  1007. * RX device.
  1008. */
  1009. status = aux_write(dev, DPCD_TRAINING_LANE0_SET, 4, aux_data);
  1010. if (status)
  1011. return -EIO;
  1012. return 0;
  1013. }
  1014. /**
  1015. * get_lane_status_adj_reqs() - Read lane status and adjustment requests
  1016. * information from the device
  1017. * @dev: The LogiCore DP TX device in question
  1018. *
  1019. * Do a burst AUX read from the RX device over the AUX channel. The contents of
  1020. * the status registers will be stored for later use by check_clock_recovery,
  1021. * check_channel_equalization, and adj_vswing_preemp.
  1022. *
  1023. * Return: 0 if the status information were read successfully, -ve on error
  1024. */
  1025. static int get_lane_status_adj_reqs(struct udevice *dev)
  1026. {
  1027. struct dp_tx *dp_tx = dev_get_priv(dev);
  1028. int status;
  1029. /*
  1030. * Read and store 4 bytes of lane status and 2 bytes of adjustment
  1031. * requests.
  1032. */
  1033. status = aux_read(dev, DPCD_STATUS_LANE_0_1, 6,
  1034. dp_tx->lane_status_ajd_reqs);
  1035. if (status)
  1036. return -EIO;
  1037. return 0;
  1038. }
  1039. /**
  1040. * check_clock_recovery() - Check clock recovery success
  1041. * @dev: The LogiCore DP TX device in question
  1042. * @lane_count: The number of lanes for which to check clock recovery success
  1043. *
  1044. * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
  1045. * that the clock recovery sequence during link training was successful - the
  1046. * RX device's link clock and data recovery unit has realized and maintained
  1047. * the frequency lock for all lanes currently in use.
  1048. *
  1049. * Return: 0 if clock recovery was successful on all lanes in question, -ve if
  1050. * not
  1051. */
  1052. static int check_clock_recovery(struct udevice *dev, u8 lane_count)
  1053. {
  1054. struct dp_tx *dp_tx = dev_get_priv(dev);
  1055. u8 *lane_status = dp_tx->lane_status_ajd_reqs;
  1056. /* Check that all LANEx_CR_DONE bits are set. */
  1057. switch (lane_count) {
  1058. case LANE_COUNT_SET_4:
  1059. if (!(lane_status[1] & DPCD_STATUS_LANE_3_CR_DONE_MASK))
  1060. goto out_fail;
  1061. if (!(lane_status[1] & DPCD_STATUS_LANE_2_CR_DONE_MASK))
  1062. goto out_fail;
  1063. /* Drop through and check lane 1. */
  1064. case LANE_COUNT_SET_2:
  1065. if (!(lane_status[0] & DPCD_STATUS_LANE_1_CR_DONE_MASK))
  1066. goto out_fail;
  1067. /* Drop through and check lane 0. */
  1068. case LANE_COUNT_SET_1:
  1069. if (!(lane_status[0] & DPCD_STATUS_LANE_0_CR_DONE_MASK))
  1070. goto out_fail;
  1071. default:
  1072. /* All (lane_count) lanes have achieved clock recovery. */
  1073. break;
  1074. }
  1075. return 0;
  1076. out_fail:
  1077. return -EIO;
  1078. }
  1079. /**
  1080. * check_channel_equalization() - Check channel equalization success
  1081. * @dev: The LogiCore DP TX device in question
  1082. * @lane_count: The number of lanes for which to check channel equalization
  1083. * success
  1084. *
  1085. * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
  1086. * that the channel equalization sequence during link training was successful -
  1087. * the RX device has achieved channel equalization, symbol lock, and interlane
  1088. * alignment for all lanes currently in use.
  1089. *
  1090. * Return: 0 if channel equalization was successful on all lanes in question,
  1091. * -ve if not
  1092. */
  1093. static int check_channel_equalization(struct udevice *dev, u8 lane_count)
  1094. {
  1095. struct dp_tx *dp_tx = dev_get_priv(dev);
  1096. u8 *lane_status = dp_tx->lane_status_ajd_reqs;
  1097. /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */
  1098. switch (lane_count) {
  1099. case LANE_COUNT_SET_4:
  1100. if (!(lane_status[1] & DPCD_STATUS_LANE_3_CE_DONE_MASK))
  1101. goto out_fail;
  1102. if (!(lane_status[1] & DPCD_STATUS_LANE_2_CE_DONE_MASK))
  1103. goto out_fail;
  1104. /* Drop through and check lane 1. */
  1105. case LANE_COUNT_SET_2:
  1106. if (!(lane_status[0] & DPCD_STATUS_LANE_1_CE_DONE_MASK))
  1107. goto out_fail;
  1108. /* Drop through and check lane 0. */
  1109. case LANE_COUNT_SET_1:
  1110. if (!(lane_status[0] & DPCD_STATUS_LANE_0_CE_DONE_MASK))
  1111. goto out_fail;
  1112. default:
  1113. /* All (lane_count) lanes have achieved channel equalization. */
  1114. break;
  1115. }
  1116. /* Check that all LANEx_SYMBOL_LOCKED bits are set. */
  1117. switch (lane_count) {
  1118. case LANE_COUNT_SET_4:
  1119. if (!(lane_status[1] & DPCD_STATUS_LANE_3_SL_DONE_MASK))
  1120. goto out_fail;
  1121. if (!(lane_status[1] & DPCD_STATUS_LANE_2_SL_DONE_MASK))
  1122. goto out_fail;
  1123. /* Drop through and check lane 1. */
  1124. case LANE_COUNT_SET_2:
  1125. if (!(lane_status[0] & DPCD_STATUS_LANE_1_SL_DONE_MASK))
  1126. goto out_fail;
  1127. /* Drop through and check lane 0. */
  1128. case LANE_COUNT_SET_1:
  1129. if (!(lane_status[0] & DPCD_STATUS_LANE_0_SL_DONE_MASK))
  1130. goto out_fail;
  1131. default:
  1132. /* All (lane_count) lanes have achieved symbol lock. */
  1133. break;
  1134. }
  1135. /* Check that interlane alignment is done. */
  1136. if (!(lane_status[2] & DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK))
  1137. goto out_fail;
  1138. return 0;
  1139. out_fail:
  1140. return -EIO;
  1141. }
  1142. /**
  1143. * set_training_pattern() - Set training pattern for link training
  1144. * @dev: The LogiCore DP TX device in question
  1145. * @pattern: The training pattern to set
  1146. *
  1147. * Set the training pattern to be used during link training for both the
  1148. * DisplayPort TX core and the RX device.
  1149. *
  1150. * Return: 0 if the training pattern could be set successfully, -ve if not
  1151. */
  1152. static int set_training_pattern(struct udevice *dev, u32 pattern)
  1153. {
  1154. struct dp_tx *dp_tx = dev_get_priv(dev);
  1155. int status;
  1156. u8 aux_data[5];
  1157. /* Write to the DisplayPort TX core. */
  1158. set_reg(dev, REG_TRAINING_PATTERN_SET, pattern);
  1159. aux_data[0] = pattern;
  1160. /* Write scrambler disable to the DisplayPort TX core. */
  1161. switch (pattern) {
  1162. case TRAINING_PATTERN_SET_OFF:
  1163. set_reg(dev, REG_SCRAMBLING_DISABLE, 0);
  1164. dp_tx->link_config.scrambler_en = 1;
  1165. break;
  1166. case TRAINING_PATTERN_SET_TP1:
  1167. case TRAINING_PATTERN_SET_TP2:
  1168. case TRAINING_PATTERN_SET_TP3:
  1169. aux_data[0] |= DPCD_TP_SET_SCRAMB_DIS_MASK;
  1170. set_reg(dev, REG_SCRAMBLING_DISABLE, 1);
  1171. dp_tx->link_config.scrambler_en = 0;
  1172. break;
  1173. default:
  1174. break;
  1175. }
  1176. /*
  1177. * Make the adjustments to both the DisplayPort TX core and the RX
  1178. * device.
  1179. */
  1180. set_vswing_preemp(dev, &aux_data[1]);
  1181. /*
  1182. * Write the voltage swing and pre-emphasis levels for each lane to the
  1183. * RX device.
  1184. */
  1185. if (pattern == TRAINING_PATTERN_SET_OFF)
  1186. status = aux_write(dev, DPCD_TP_SET, 1, aux_data);
  1187. else
  1188. status = aux_write(dev, DPCD_TP_SET, 5, aux_data);
  1189. if (status)
  1190. return -EIO;
  1191. return 0;
  1192. }
  1193. /**
  1194. * training_state_clock_recovery() - Run clock recovery part of link training
  1195. * @dev: The LogiCore DP TX device in question
  1196. *
  1197. * Run the clock recovery sequence as part of link training. The
  1198. * sequence is as follows:
  1199. *
  1200. * 0) Start signaling at the minimum voltage swing, pre-emphasis, and
  1201. * post- cursor levels.
  1202. * 1) Transmit training pattern 1 over the main link with symbol
  1203. * scrambling disabled.
  1204. * 2) The clock recovery loop. If clock recovery is unsuccessful after
  1205. * MaxIterations loop iterations, return.
  1206. * 2a) Wait for at least the period of time specified in the RX device's
  1207. * DisplayPort Configuration data (DPCD) register,
  1208. * TRAINING_AUX_RD_INTERVAL.
  1209. * 2b) Check if all lanes have achieved clock recovery lock. If so,
  1210. * return.
  1211. * 2c) Check if the same voltage swing level has been used 5 consecutive
  1212. * times or if the maximum level has been reached. If so, return.
  1213. * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
  1214. * requested by the RX device.
  1215. * 2e) Loop back to 2a.
  1216. *
  1217. * For a more detailed description of the clock recovery sequence, see section
  1218. * 3.5.1.2.1 of the DisplayPort 1.2a specification document.
  1219. *
  1220. * Return: The next state machine state to advance to
  1221. */
  1222. static unsigned int training_state_clock_recovery(struct udevice *dev)
  1223. {
  1224. struct dp_tx *dp_tx = dev_get_priv(dev);
  1225. int status;
  1226. u32 delay_us;
  1227. u8 prev_vs_level = 0;
  1228. u8 same_vs_level_count = 0;
  1229. /*
  1230. * Obtain the required delay for clock recovery as specified by the
  1231. * RX device.
  1232. */
  1233. delay_us = get_training_delay(dev, TS_CLOCK_RECOVERY);
  1234. /* Start CRLock. */
  1235. /* Transmit training pattern 1. */
  1236. /* Disable the scrambler. */
  1237. /* Start from minimal voltage swing and pre-emphasis levels. */
  1238. dp_tx->link_config.vs_level = 0;
  1239. dp_tx->link_config.pe_level = 0;
  1240. status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP1);
  1241. if (status)
  1242. return TS_FAILURE;
  1243. while (1) {
  1244. /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
  1245. udelay(delay_us);
  1246. /* Get lane and adjustment requests. */
  1247. status = get_lane_status_adj_reqs(dev);
  1248. if (status)
  1249. return TS_FAILURE;
  1250. /*
  1251. * Check if all lanes have realized and maintained the frequency
  1252. * lock and get adjustment requests.
  1253. */
  1254. status = check_clock_recovery(dev,
  1255. dp_tx->link_config.lane_count);
  1256. if (!status)
  1257. return TS_CHANNEL_EQUALIZATION;
  1258. /*
  1259. * Check if the same voltage swing for each lane has been used 5
  1260. * consecutive times.
  1261. */
  1262. if (prev_vs_level == dp_tx->link_config.vs_level) {
  1263. same_vs_level_count++;
  1264. } else {
  1265. same_vs_level_count = 0;
  1266. prev_vs_level = dp_tx->link_config.vs_level;
  1267. }
  1268. if (same_vs_level_count >= 5)
  1269. break;
  1270. /* Only try maximum voltage swing once. */
  1271. if (dp_tx->link_config.vs_level == MAXIMUM_VS_LEVEL)
  1272. break;
  1273. /* Adjust the drive settings as requested by the RX device. */
  1274. status = adj_vswing_preemp(dev);
  1275. if (status)
  1276. /* The AUX write failed. */
  1277. return TS_FAILURE;
  1278. }
  1279. return TS_ADJUST_LINK_RATE;
  1280. }
  1281. /**
  1282. * training_state_channel_equalization() - Run channel equalization part of
  1283. * link training
  1284. * @dev: The LogiCore DP TX device in question
  1285. *
  1286. * Run the channel equalization sequence as part of link
  1287. * training. The sequence is as follows:
  1288. *
  1289. * 0) Start signaling with the same drive settings used at the end of the
  1290. * clock recovery sequence.
  1291. * 1) Transmit training pattern 2 (or 3) over the main link with symbol
  1292. * scrambling disabled.
  1293. * 2) The channel equalization loop. If channel equalization is
  1294. * unsuccessful after 5 loop iterations, return.
  1295. * 2a) Wait for at least the period of time specified in the RX device's
  1296. * DisplayPort Configuration data (DPCD) register,
  1297. * TRAINING_AUX_RD_INTERVAL.
  1298. * 2b) Check if all lanes have achieved channel equalization, symbol lock,
  1299. * and interlane alignment. If so, return.
  1300. * 2c) Check if the same voltage swing level has been used 5 consecutive
  1301. * times or if the maximum level has been reached. If so, return.
  1302. * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
  1303. * requested by the RX device.
  1304. * 2e) Loop back to 2a.
  1305. *
  1306. * For a more detailed description of the channel equalization sequence, see
  1307. * section 3.5.1.2.2 of the DisplayPort 1.2a specification document.
  1308. *
  1309. * Return: The next state machine state to advance to
  1310. */
  1311. static int training_state_channel_equalization(struct udevice *dev)
  1312. {
  1313. struct dp_tx *dp_tx = dev_get_priv(dev);
  1314. int status;
  1315. u32 delay_us;
  1316. u32 iteration_count = 0;
  1317. /*
  1318. * Obtain the required delay for channel equalization as specified by
  1319. * the RX device.
  1320. */
  1321. delay_us = get_training_delay(dev, TS_CHANNEL_EQUALIZATION);
  1322. /* Start channel equalization. */
  1323. /* Write the current drive settings. */
  1324. /* Transmit training pattern 2/3. */
  1325. if (dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & DPCD_TPS3_SUPPORT_MASK)
  1326. status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP3);
  1327. else
  1328. status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP2);
  1329. if (status)
  1330. return TS_FAILURE;
  1331. while (iteration_count < 5) {
  1332. /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
  1333. udelay(delay_us);
  1334. /* Get lane and adjustment requests. */
  1335. status = get_lane_status_adj_reqs(dev);
  1336. if (status)
  1337. /* The AUX read failed. */
  1338. return TS_FAILURE;
  1339. /* Check that all lanes still have their clocks locked. */
  1340. status = check_clock_recovery(dev,
  1341. dp_tx->link_config.lane_count);
  1342. if (status)
  1343. break;
  1344. /*
  1345. * Check if all lanes have accomplished channel equalization,
  1346. * symbol lock, and interlane alignment.
  1347. */
  1348. status =
  1349. check_channel_equalization(dev,
  1350. dp_tx->link_config.lane_count);
  1351. if (!status)
  1352. return TS_SUCCESS;
  1353. /* Adjust the drive settings as requested by the RX device. */
  1354. status = adj_vswing_preemp(dev);
  1355. if (status)
  1356. /* The AUX write failed. */
  1357. return TS_FAILURE;
  1358. iteration_count++;
  1359. }
  1360. /*
  1361. * Tried 5 times with no success. Try a reduced bitrate first, then
  1362. * reduce the number of lanes.
  1363. */
  1364. return TS_ADJUST_LINK_RATE;
  1365. }
  1366. /**
  1367. * training_state_adjust_link_rate() - Downshift data rate and/or lane count
  1368. * @dev: The LogiCore DP TX device in question
  1369. *
  1370. * This function is reached if either the clock recovery or the channel
  1371. * equalization process failed during training. As a result, the data rate will
  1372. * be downshifted, and training will be re-attempted (starting with clock
  1373. * recovery) at the reduced data rate. If the data rate is already at 1.62
  1374. * Gbps, a downshift in lane count will be attempted.
  1375. *
  1376. * Return: The next state machine state to advance to
  1377. */
  1378. static int training_state_adjust_link_rate(struct udevice *dev)
  1379. {
  1380. struct dp_tx *dp_tx = dev_get_priv(dev);
  1381. int status;
  1382. switch (dp_tx->link_config.link_rate) {
  1383. case LINK_BW_SET_540GBPS:
  1384. status = set_link_rate(dev, LINK_BW_SET_270GBPS);
  1385. if (status) {
  1386. status = TS_FAILURE;
  1387. break;
  1388. }
  1389. status = TS_CLOCK_RECOVERY;
  1390. break;
  1391. case LINK_BW_SET_270GBPS:
  1392. status = set_link_rate(dev, LINK_BW_SET_162GBPS);
  1393. if (status) {
  1394. status = TS_FAILURE;
  1395. break;
  1396. }
  1397. status = TS_CLOCK_RECOVERY;
  1398. break;
  1399. default:
  1400. /*
  1401. * Already at the lowest link rate. Try reducing the lane
  1402. * count next.
  1403. */
  1404. status = TS_ADJUST_LANE_COUNT;
  1405. break;
  1406. }
  1407. return status;
  1408. }
  1409. /**
  1410. * trainig_state_adjust_lane_count - Downshift lane count
  1411. * @dev: The LogiCore DP TX device in question
  1412. *
  1413. * This function is reached if either the clock recovery or the channel
  1414. * equalization process failed during training, and a minimal data rate of 1.62
  1415. * Gbps was being used. As a result, the number of lanes in use will be
  1416. * reduced, and training will be re-attempted (starting with clock recovery) at
  1417. * this lower lane count.
  1418. *
  1419. * Return: The next state machine state to advance to
  1420. */
  1421. static int trainig_state_adjust_lane_count(struct udevice *dev)
  1422. {
  1423. struct dp_tx *dp_tx = dev_get_priv(dev);
  1424. int status;
  1425. switch (dp_tx->link_config.lane_count) {
  1426. case LANE_COUNT_SET_4:
  1427. status = set_lane_count(dev, LANE_COUNT_SET_2);
  1428. if (status) {
  1429. status = TS_FAILURE;
  1430. break;
  1431. }
  1432. status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
  1433. if (status) {
  1434. status = TS_FAILURE;
  1435. break;
  1436. }
  1437. status = TS_CLOCK_RECOVERY;
  1438. break;
  1439. case LANE_COUNT_SET_2:
  1440. status = set_lane_count(dev, LANE_COUNT_SET_1);
  1441. if (status) {
  1442. status = TS_FAILURE;
  1443. break;
  1444. }
  1445. status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
  1446. if (status) {
  1447. status = TS_FAILURE;
  1448. break;
  1449. }
  1450. status = TS_CLOCK_RECOVERY;
  1451. break;
  1452. default:
  1453. /*
  1454. * Already at the lowest lane count. Training has failed at the
  1455. * lowest lane count and link rate.
  1456. */
  1457. status = TS_FAILURE;
  1458. break;
  1459. }
  1460. return status;
  1461. }
  1462. /**
  1463. * check_link_status() - Check status of link
  1464. * @dev: The LogiCore DP TX device in question
  1465. * @lane_count: The lane count to use for the check
  1466. *
  1467. * Check if the receiver's DisplayPort Configuration data (DPCD) indicates the
  1468. * receiver has achieved and maintained clock recovery, channel equalization,
  1469. * symbol lock, and interlane alignment for all lanes currently in use.
  1470. *
  1471. * Return: 0 if the link status is OK, -ve if a error occurred during checking
  1472. */
  1473. static int check_link_status(struct udevice *dev, u8 lane_count)
  1474. {
  1475. u8 retry_count = 0;
  1476. if (!is_connected(dev))
  1477. return -ENODEV;
  1478. /* Retrieve AUX info. */
  1479. do {
  1480. int status;
  1481. /* Get lane and adjustment requests. */
  1482. status = get_lane_status_adj_reqs(dev);
  1483. if (status)
  1484. return -EIO;
  1485. /* Check if the link needs training. */
  1486. if ((check_clock_recovery(dev, lane_count) == 0) &&
  1487. (check_channel_equalization(dev, lane_count) == 0))
  1488. return 0;
  1489. retry_count++;
  1490. } while (retry_count < 5); /* Retry up to 5 times. */
  1491. return -EIO;
  1492. }
  1493. /**
  1494. * run_training() - Run link training
  1495. * @dev: The LogiCore DP TX device in question
  1496. *
  1497. * Run the link training process. It is implemented as a state machine, with
  1498. * each state returning the next state. First, the clock recovery sequence will
  1499. * be run; if successful, the channel equalization sequence will run. If either
  1500. * the clock recovery or channel equalization sequence failed, the link rate or
  1501. * the number of lanes used will be reduced and training will be re-attempted.
  1502. * If training fails at the minimal data rate, 1.62 Gbps with a single lane,
  1503. * training will no longer re-attempt and fail.
  1504. *
  1505. * ### Here be dragons ###
  1506. * There are undocumented timeout constraints in the link training process. In
  1507. * DP v1.2a spec, Chapter 3.5.1.2.2 a 10ms limit for the complete training
  1508. * process is mentioned. Which individual timeouts are derived and implemented
  1509. * by sink manufacturers is unknown. So each step should be as short as
  1510. * possible and link training should start as soon as possible after HPD.
  1511. *
  1512. * Return: 0 if the training sequence ran successfully, -ve if a error occurred
  1513. * or the training failed
  1514. */
  1515. static int run_training(struct udevice *dev)
  1516. {
  1517. struct dp_tx *dp_tx = dev_get_priv(dev);
  1518. int status;
  1519. int training_state = TS_CLOCK_RECOVERY;
  1520. while (1) {
  1521. switch (training_state) {
  1522. case TS_CLOCK_RECOVERY:
  1523. training_state =
  1524. training_state_clock_recovery(dev);
  1525. break;
  1526. case TS_CHANNEL_EQUALIZATION:
  1527. training_state =
  1528. training_state_channel_equalization(dev);
  1529. break;
  1530. case TS_ADJUST_LINK_RATE:
  1531. training_state =
  1532. training_state_adjust_link_rate(dev);
  1533. break;
  1534. case TS_ADJUST_LANE_COUNT:
  1535. training_state =
  1536. trainig_state_adjust_lane_count(dev);
  1537. break;
  1538. default:
  1539. break;
  1540. }
  1541. if (training_state == TS_SUCCESS)
  1542. break;
  1543. else if (training_state == TS_FAILURE)
  1544. return -EIO;
  1545. if (training_state == TS_ADJUST_LINK_RATE ||
  1546. training_state == TS_ADJUST_LANE_COUNT) {
  1547. if (!dp_tx->train_adaptive)
  1548. return -EIO;
  1549. status = set_training_pattern(dev,
  1550. TRAINING_PATTERN_SET_OFF);
  1551. if (status)
  1552. return -EIO;
  1553. }
  1554. }
  1555. /* Final status check. */
  1556. status = check_link_status(dev, dp_tx->link_config.lane_count);
  1557. if (status)
  1558. return -EIO;
  1559. return 0;
  1560. }
  1561. /* Link policy maker */
  1562. /**
  1563. * cfg_main_link_max() - Determine best common capabilities
  1564. * @dev: The LogiCore DP TX device in question
  1565. *
  1566. * Determine the common capabilities between the DisplayPort TX core and the RX
  1567. * device.
  1568. *
  1569. * Return: 0 if the determination succeeded, -ve on error
  1570. */
  1571. static int cfg_main_link_max(struct udevice *dev)
  1572. {
  1573. struct dp_tx *dp_tx = dev_get_priv(dev);
  1574. int status;
  1575. if (!is_connected(dev))
  1576. return -ENODEV;
  1577. /*
  1578. * Configure the main link to the maximum common link rate between the
  1579. * DisplayPort TX core and the RX device.
  1580. */
  1581. status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
  1582. if (status)
  1583. return status;
  1584. /*
  1585. * Configure the main link to the maximum common lane count between the
  1586. * DisplayPort TX core and the RX device.
  1587. */
  1588. status = set_lane_count(dev, dp_tx->link_config.max_lane_count);
  1589. if (status)
  1590. return status;
  1591. return 0;
  1592. }
  1593. /**
  1594. * establish_link() - Establish a link
  1595. * @dev: The LogiCore DP TX device in question
  1596. *
  1597. * Check if the link needs training and run the training sequence if training
  1598. * is required.
  1599. *
  1600. * Return: 0 if the link was established successfully, -ve on error
  1601. */
  1602. static int establish_link(struct udevice *dev)
  1603. {
  1604. struct dp_tx *dp_tx = dev_get_priv(dev);
  1605. int status;
  1606. int status2;
  1607. u32 mask;
  1608. reset_dp_phy(dev, PHY_CONFIG_PHY_RESET_MASK);
  1609. /* Disable main link during training. */
  1610. disable_main_link(dev);
  1611. /* Wait for the PHY to be ready. */
  1612. mask = phy_status_lanes_ready_mask(dp_tx->max_lane_count);
  1613. status = wait_phy_ready(dev, mask);
  1614. if (status)
  1615. return -EIO;
  1616. /* Train main link. */
  1617. status = run_training(dev);
  1618. /* Turn off the training pattern and enable scrambler. */
  1619. status2 = set_training_pattern(dev, TRAINING_PATTERN_SET_OFF);
  1620. if (status || status2)
  1621. return -EIO;
  1622. return 0;
  1623. }
  1624. /*
  1625. * Stream policy maker
  1626. */
  1627. /**
  1628. * cfg_msa_recalculate() - Calculate MSA parameters
  1629. * @dev: The LogiCore DP TX device in question
  1630. *
  1631. * Calculate the following Main Stream Attributes (MSA):
  1632. * - Transfer unit size
  1633. * - User pixel width
  1634. * - Horizontal total clock
  1635. * - Vertical total clock
  1636. * - misc_0
  1637. * - misc_1
  1638. * - Data per lane
  1639. * - Average number of bytes per transfer unit
  1640. * - Number of initial wait cycles
  1641. *
  1642. * These values are derived from:
  1643. * - Bits per color
  1644. * - Horizontal resolution
  1645. * - Vertical resolution
  1646. * - Horizontal blank start
  1647. * - Vertical blank start
  1648. * - Pixel clock (in KHz)
  1649. * - Horizontal sync polarity
  1650. * - Vertical sync polarity
  1651. * - Horizontal sync pulse width
  1652. * - Vertical sync pulse width
  1653. */
  1654. static void cfg_msa_recalculate(struct udevice *dev)
  1655. {
  1656. struct dp_tx *dp_tx = dev_get_priv(dev);
  1657. u32 video_bw;
  1658. u32 link_bw;
  1659. u32 words_per_line;
  1660. u8 bits_per_pixel;
  1661. struct main_stream_attributes *msa_config;
  1662. struct link_config *link_config;
  1663. msa_config = &dp_tx->main_stream_attributes;
  1664. link_config = &dp_tx->link_config;
  1665. /*
  1666. * Set the user pixel width to handle clocks that exceed the
  1667. * capabilities of the DisplayPort TX core.
  1668. */
  1669. if (msa_config->override_user_pixel_width == 0) {
  1670. if (msa_config->pixel_clock_hz > 300000000 &&
  1671. link_config->lane_count == LANE_COUNT_SET_4) {
  1672. msa_config->user_pixel_width = 4;
  1673. } /*
  1674. * Xilinx driver used 75 MHz as a limit here, 150 MHZ should
  1675. * be more sane
  1676. */
  1677. else if ((msa_config->pixel_clock_hz > 150000000) &&
  1678. (link_config->lane_count != LANE_COUNT_SET_1)) {
  1679. msa_config->user_pixel_width = 2;
  1680. } else {
  1681. msa_config->user_pixel_width = 1;
  1682. }
  1683. }
  1684. /* Compute the rest of the MSA values. */
  1685. msa_config->n_vid = 27 * 1000 * link_config->link_rate;
  1686. /* Miscellaneous attributes. */
  1687. if (msa_config->bits_per_color == 6)
  1688. msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_6BPC;
  1689. else if (msa_config->bits_per_color == 8)
  1690. msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_8BPC;
  1691. else if (msa_config->bits_per_color == 10)
  1692. msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_10BPC;
  1693. else if (msa_config->bits_per_color == 12)
  1694. msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_12BPC;
  1695. else if (msa_config->bits_per_color == 16)
  1696. msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_16BPC;
  1697. msa_config->misc_0 = (msa_config->misc_0 <<
  1698. MAIN_STREAMX_MISC0_BDC_SHIFT) |
  1699. (msa_config->y_cb_cr_colorimetry <<
  1700. MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
  1701. (msa_config->dynamic_range <<
  1702. MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
  1703. (msa_config->component_format <<
  1704. MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
  1705. (msa_config->synchronous_clock_mode);
  1706. msa_config->misc_1 = 0;
  1707. /*
  1708. * Determine the number of bits per pixel for the specified color
  1709. * component format.
  1710. */
  1711. if (msa_config->component_format ==
  1712. MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422)
  1713. /* YCbCr422 color component format. */
  1714. bits_per_pixel = msa_config->bits_per_color * 2;
  1715. else
  1716. /* RGB or YCbCr 4:4:4 color component format. */
  1717. bits_per_pixel = msa_config->bits_per_color * 3;
  1718. /* Calculate the data per lane. */
  1719. words_per_line = (msa_config->h_active * bits_per_pixel);
  1720. if (words_per_line % 16)
  1721. words_per_line += 16;
  1722. words_per_line /= 16;
  1723. msa_config->data_per_lane = words_per_line - link_config->lane_count;
  1724. if (words_per_line % link_config->lane_count)
  1725. msa_config->data_per_lane += (words_per_line %
  1726. link_config->lane_count);
  1727. /*
  1728. * Allocate a fixed size for single-stream transport (SST)
  1729. * operation.
  1730. */
  1731. msa_config->transfer_unit_size = 64;
  1732. /*
  1733. * Calculate the average number of bytes per transfer unit.
  1734. * Note: Both the integer and the fractional part is stored in
  1735. * avg_bytes_per_tu.
  1736. */
  1737. video_bw = ((msa_config->pixel_clock_hz / 1000) * bits_per_pixel) / 8;
  1738. link_bw = (link_config->lane_count * link_config->link_rate * 27);
  1739. msa_config->avg_bytes_per_tu = (video_bw *
  1740. msa_config->transfer_unit_size) /
  1741. link_bw;
  1742. /*
  1743. * The number of initial wait cycles at the start of a new line
  1744. * by the framing logic. This allows enough data to be buffered
  1745. * in the input FIFO before video is sent.
  1746. */
  1747. if ((msa_config->avg_bytes_per_tu / 1000) <= 4)
  1748. msa_config->init_wait = 64;
  1749. else
  1750. msa_config->init_wait = msa_config->transfer_unit_size -
  1751. (msa_config->avg_bytes_per_tu / 1000);
  1752. }
  1753. /**
  1754. * set_line_reset() - Enable/Disable end-of-line-reset
  1755. * @dev: The LogiCore DP TX device in question
  1756. *
  1757. * Disable/enable the end-of-line-reset to the internal video pipe in case of
  1758. * reduced blanking as required.
  1759. */
  1760. static void set_line_reset(struct udevice *dev)
  1761. {
  1762. struct dp_tx *dp_tx = dev_get_priv(dev);
  1763. u32 reg_val;
  1764. u16 h_blank;
  1765. u16 h_reduced_blank;
  1766. struct main_stream_attributes *msa_config =
  1767. &dp_tx->main_stream_attributes;
  1768. h_blank = msa_config->h_total - msa_config->h_active;
  1769. /* Reduced blanking starts at ceil(0.2 * HTotal). */
  1770. h_reduced_blank = 2 * msa_config->h_total;
  1771. if (h_reduced_blank % 10)
  1772. h_reduced_blank += 10;
  1773. h_reduced_blank /= 10;
  1774. /* CVT spec. states h_blank is either 80 or 160 for reduced blanking. */
  1775. reg_val = get_reg(dev, REG_LINE_RESET_DISABLE);
  1776. if (h_blank < h_reduced_blank &&
  1777. (h_blank == 80 || h_blank == 160)) {
  1778. reg_val |= LINE_RESET_DISABLE_MASK;
  1779. } else {
  1780. reg_val &= ~LINE_RESET_DISABLE_MASK;
  1781. }
  1782. set_reg(dev, REG_LINE_RESET_DISABLE, reg_val);
  1783. }
  1784. /**
  1785. * clear_msa_values() - Clear MSA values
  1786. * @dev: The LogiCore DP TX device in question
  1787. *
  1788. * Clear the main stream attributes registers of the DisplayPort TX core.
  1789. */
  1790. static void clear_msa_values(struct udevice *dev)
  1791. {
  1792. set_reg(dev, REG_MAIN_STREAM_HTOTAL, 0);
  1793. set_reg(dev, REG_MAIN_STREAM_VTOTAL, 0);
  1794. set_reg(dev, REG_MAIN_STREAM_POLARITY, 0);
  1795. set_reg(dev, REG_MAIN_STREAM_HSWIDTH, 0);
  1796. set_reg(dev, REG_MAIN_STREAM_VSWIDTH, 0);
  1797. set_reg(dev, REG_MAIN_STREAM_HRES, 0);
  1798. set_reg(dev, REG_MAIN_STREAM_VRES, 0);
  1799. set_reg(dev, REG_MAIN_STREAM_HSTART, 0);
  1800. set_reg(dev, REG_MAIN_STREAM_VSTART, 0);
  1801. set_reg(dev, REG_MAIN_STREAM_MISC0, 0);
  1802. set_reg(dev, REG_MAIN_STREAM_MISC1, 0);
  1803. set_reg(dev, REG_USER_PIXEL_WIDTH, 0);
  1804. set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, 0);
  1805. set_reg(dev, REG_M_VID, 0);
  1806. set_reg(dev, REG_N_VID, 0);
  1807. set_reg(dev, REG_STREAM1, 0);
  1808. set_reg(dev, REG_TU_SIZE, 0);
  1809. set_reg(dev, REG_MIN_BYTES_PER_TU, 0);
  1810. set_reg(dev, REG_FRAC_BYTES_PER_TU, 0);
  1811. set_reg(dev, REG_INIT_WAIT, 0);
  1812. }
  1813. /**
  1814. * set_msa_values() - Set MSA values
  1815. * @dev: The LogiCore DP TX device in question
  1816. *
  1817. * Set the main stream attributes registers of the DisplayPort TX
  1818. * core with the values specified in the main stream attributes configuration
  1819. * structure.
  1820. */
  1821. static void set_msa_values(struct udevice *dev)
  1822. {
  1823. struct dp_tx *dp_tx = dev_get_priv(dev);
  1824. struct main_stream_attributes *msa_config =
  1825. &dp_tx->main_stream_attributes;
  1826. printf(" set MSA %u x %u\n", msa_config->h_active,
  1827. msa_config->v_active);
  1828. set_reg(dev, REG_MAIN_STREAM_HTOTAL, msa_config->h_total);
  1829. set_reg(dev, REG_MAIN_STREAM_VTOTAL, msa_config->v_total);
  1830. set_reg(dev, REG_MAIN_STREAM_POLARITY,
  1831. msa_config->h_sync_polarity |
  1832. (msa_config->v_sync_polarity <<
  1833. MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
  1834. set_reg(dev, REG_MAIN_STREAM_HSWIDTH, msa_config->h_sync_width);
  1835. set_reg(dev, REG_MAIN_STREAM_VSWIDTH, msa_config->v_sync_width);
  1836. set_reg(dev, REG_MAIN_STREAM_HRES, msa_config->h_active);
  1837. set_reg(dev, REG_MAIN_STREAM_VRES, msa_config->v_active);
  1838. set_reg(dev, REG_MAIN_STREAM_HSTART, msa_config->h_start);
  1839. set_reg(dev, REG_MAIN_STREAM_VSTART, msa_config->v_start);
  1840. set_reg(dev, REG_MAIN_STREAM_MISC0, msa_config->misc_0);
  1841. set_reg(dev, REG_MAIN_STREAM_MISC1, msa_config->misc_1);
  1842. set_reg(dev, REG_USER_PIXEL_WIDTH, msa_config->user_pixel_width);
  1843. set_reg(dev, REG_M_VID, msa_config->pixel_clock_hz / 1000);
  1844. set_reg(dev, REG_N_VID, msa_config->n_vid);
  1845. set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, msa_config->data_per_lane);
  1846. set_line_reset(dev);
  1847. set_reg(dev, REG_TU_SIZE, msa_config->transfer_unit_size);
  1848. set_reg(dev, REG_MIN_BYTES_PER_TU, msa_config->avg_bytes_per_tu / 1000);
  1849. set_reg(dev, REG_FRAC_BYTES_PER_TU,
  1850. (msa_config->avg_bytes_per_tu % 1000) * 1024 / 1000);
  1851. set_reg(dev, REG_INIT_WAIT, msa_config->init_wait);
  1852. }
  1853. /*
  1854. * external API
  1855. */
  1856. /**
  1857. * logicore_dp_tx_set_msa() - Set given MSA values on device
  1858. * @dev: The LogiCore DP TX device in question
  1859. * @msa: The MSA values to set for the device
  1860. */
  1861. static void logicore_dp_tx_set_msa(struct udevice *dev,
  1862. struct logicore_dp_tx_msa *msa)
  1863. {
  1864. struct dp_tx *dp_tx = dev_get_priv(dev);
  1865. memset(&dp_tx->main_stream_attributes, 0,
  1866. sizeof(struct main_stream_attributes));
  1867. dp_tx->main_stream_attributes.pixel_clock_hz = msa->pixel_clock_hz;
  1868. dp_tx->main_stream_attributes.bits_per_color = msa->bits_per_color;
  1869. dp_tx->main_stream_attributes.h_active = msa->h_active;
  1870. dp_tx->main_stream_attributes.h_start = msa->h_start;
  1871. dp_tx->main_stream_attributes.h_sync_polarity = msa->h_sync_polarity;
  1872. dp_tx->main_stream_attributes.h_sync_width = msa->h_sync_width;
  1873. dp_tx->main_stream_attributes.h_total = msa->h_total;
  1874. dp_tx->main_stream_attributes.v_active = msa->v_active;
  1875. dp_tx->main_stream_attributes.v_start = msa->v_start;
  1876. dp_tx->main_stream_attributes.v_sync_polarity = msa->v_sync_polarity;
  1877. dp_tx->main_stream_attributes.v_sync_width = msa->v_sync_width;
  1878. dp_tx->main_stream_attributes.v_total = msa->v_total;
  1879. dp_tx->main_stream_attributes.override_user_pixel_width =
  1880. msa->override_user_pixel_width;
  1881. dp_tx->main_stream_attributes.user_pixel_width = msa->user_pixel_width;
  1882. dp_tx->main_stream_attributes.synchronous_clock_mode = 0;
  1883. }
  1884. /**
  1885. * logicore_dp_tx_video_enable() - Enable video output
  1886. * @dev: The LogiCore DP TX device in question
  1887. * @msa: The MSA values to set for the device
  1888. *
  1889. * Return: 0 if the video was enabled successfully, -ve on error
  1890. */
  1891. static int logicore_dp_tx_video_enable(struct udevice *dev,
  1892. struct logicore_dp_tx_msa *msa)
  1893. {
  1894. struct dp_tx *dp_tx = dev_get_priv(dev);
  1895. int res;
  1896. u8 power = 0x01;
  1897. if (!is_connected(dev)) {
  1898. printf(" no DP sink connected\n");
  1899. return -EIO;
  1900. }
  1901. initialize(dev);
  1902. disable_main_link(dev);
  1903. logicore_dp_tx_set_msa(dev, msa);
  1904. get_rx_capabilities(dev);
  1905. printf(" DP sink connected\n");
  1906. aux_write(dev, DPCD_SET_POWER_DP_PWR_VOLTAGE, 1, &power);
  1907. set_enhanced_frame_mode(dev, true);
  1908. cfg_main_link_max(dev);
  1909. res = establish_link(dev);
  1910. printf(" establish_link: %s, vs: %d, pe: %d\n",
  1911. res ? "failed" : "ok", dp_tx->link_config.vs_level,
  1912. dp_tx->link_config.pe_level);
  1913. cfg_msa_recalculate(dev);
  1914. clear_msa_values(dev);
  1915. set_msa_values(dev);
  1916. enable_main_link(dev);
  1917. return 0;
  1918. }
  1919. /*
  1920. * Driver functions
  1921. */
  1922. static int logicore_dp_tx_enable(struct udevice *dev, int panel_bpp,
  1923. const struct display_timing *timing)
  1924. {
  1925. struct clk pixclock;
  1926. struct logicore_dp_tx_msa *msa;
  1927. struct logicore_dp_tx_msa mode_640_480_60 = {
  1928. .pixel_clock_hz = 25175000,
  1929. .bits_per_color = 8,
  1930. .h_active = 640,
  1931. .h_start = 144,
  1932. .h_sync_polarity = false,
  1933. .h_sync_width = 96,
  1934. .h_total = 800,
  1935. .v_active = 480,
  1936. .v_start = 35,
  1937. .v_sync_polarity = false,
  1938. .v_sync_width = 2,
  1939. .v_total = 525,
  1940. .override_user_pixel_width = false,
  1941. .user_pixel_width = 0,
  1942. };
  1943. struct logicore_dp_tx_msa mode_720_400_70 = {
  1944. .pixel_clock_hz = 28300000,
  1945. .bits_per_color = 8,
  1946. .h_active = 720,
  1947. .h_start = 162,
  1948. .h_sync_polarity = false,
  1949. .h_sync_width = 108,
  1950. .h_total = 900,
  1951. .v_active = 400,
  1952. .v_start = 37,
  1953. .v_sync_polarity = true,
  1954. .v_sync_width = 2,
  1955. .v_total = 449,
  1956. .override_user_pixel_width = false,
  1957. .user_pixel_width = 0,
  1958. };
  1959. struct logicore_dp_tx_msa mode_1024_768_60 = {
  1960. .pixel_clock_hz = 65000000,
  1961. .bits_per_color = 8,
  1962. .h_active = 1024,
  1963. .h_start = 296,
  1964. .h_sync_polarity = false,
  1965. .h_sync_width = 136,
  1966. .h_total = 1344,
  1967. .v_active = 768,
  1968. .v_start = 35,
  1969. .v_sync_polarity = false,
  1970. .v_sync_width = 2,
  1971. .v_total = 806,
  1972. .override_user_pixel_width = false,
  1973. .user_pixel_width = 0,
  1974. };
  1975. if (timing->hactive.typ == 1024 && timing->vactive.typ == 768)
  1976. msa = &mode_1024_768_60;
  1977. else if (timing->hactive.typ == 720 && timing->vactive.typ == 400)
  1978. msa = &mode_720_400_70;
  1979. else
  1980. msa = &mode_640_480_60;
  1981. if (clk_get_by_index(dev, 0, &pixclock)) {
  1982. printf("%s: Could not get pixelclock\n", dev->name);
  1983. return -1;
  1984. }
  1985. clk_set_rate(&pixclock, msa->pixel_clock_hz);
  1986. return logicore_dp_tx_video_enable(dev, msa);
  1987. }
  1988. static int logicore_dp_tx_probe(struct udevice *dev)
  1989. {
  1990. struct dp_tx *dp_tx = dev_get_priv(dev);
  1991. dp_tx->s_axi_clk = S_AXI_CLK_DEFAULT;
  1992. dp_tx->train_adaptive = false;
  1993. dp_tx->max_link_rate = DPCD_MAX_LINK_RATE_540GBPS;
  1994. dp_tx->max_lane_count = DPCD_MAX_LANE_COUNT_4;
  1995. dp_tx->base = dev_read_u32_default(dev, "reg", -1);
  1996. return 0;
  1997. }
  1998. static const struct dm_display_ops logicore_dp_tx_ops = {
  1999. .enable = logicore_dp_tx_enable,
  2000. };
  2001. static const struct udevice_id logicore_dp_tx_ids[] = {
  2002. { .compatible = "gdsys,logicore_dp_tx" },
  2003. { /* sentinel */ }
  2004. };
  2005. U_BOOT_DRIVER(logicore_dp_tx) = {
  2006. .name = "logicore_dp_tx",
  2007. .id = UCLASS_DISPLAY,
  2008. .of_match = logicore_dp_tx_ids,
  2009. .probe = logicore_dp_tx_probe,
  2010. .priv_auto_alloc_size = sizeof(struct dp_tx),
  2011. .ops = &logicore_dp_tx_ops,
  2012. };