logicore_dp_dpcd.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * logicore_dp_dpcd.h
  4. *
  5. * DPCD interface definition for XILINX LogiCore DisplayPort v6.1
  6. * based on Xilinx dp_v3_1 driver sources
  7. *
  8. * (C) Copyright 2016
  9. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  10. */
  11. #ifndef __GDSYS_LOGICORE_DP_DPCD_H__
  12. #define __GDSYS_LOGICORE_DP_DPCD_H__
  13. /* receiver capability field */
  14. #define DPCD_REV 0x00000
  15. #define DPCD_MAX_LINK_RATE 0x00001
  16. #define DPCD_MAX_LANE_COUNT 0x00002
  17. #define DPCD_MAX_DOWNSPREAD 0x00003
  18. #define DPCD_NORP_PWR_V_CAP 0x00004
  19. #define DPCD_DOWNSP_PRESENT 0x00005
  20. #define DPCD_ML_CH_CODING_CAP 0x00006
  21. #define DPCD_DOWNSP_COUNT_MSA_OUI 0x00007
  22. #define DPCD_RX_PORT0_CAP_0 0x00008
  23. #define DPCD_RX_PORT0_CAP_1 0x00009
  24. #define DPCD_RX_PORT1_CAP_0 0x0000A
  25. #define DPCD_RX_PORT1_CAP_1 0x0000B
  26. #define DPCD_I2C_SPEED_CTL_CAP 0x0000C
  27. #define DPCD_EDP_CFG_CAP 0x0000D
  28. #define DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E
  29. #define DPCD_ADAPTER_CAP 0x0000F
  30. #define DPCD_FAUX_CAP 0x00020
  31. #define DPCD_MSTM_CAP 0x00021
  32. #define DPCD_NUM_AUDIO_EPS 0x00022
  33. #define DPCD_AV_GRANULARITY 0x00023
  34. #define DPCD_AUD_DEC_LAT_7_0 0x00024
  35. #define DPCD_AUD_DEC_LAT_15_8 0x00025
  36. #define DPCD_AUD_PP_LAT_7_0 0x00026
  37. #define DPCD_AUD_PP_LAT_15_8 0x00027
  38. #define DPCD_VID_INTER_LAT 0x00028
  39. #define DPCD_VID_PROG_LAT 0x00029
  40. #define DPCD_REP_LAT 0x0002A
  41. #define DPCD_AUD_DEL_INS_7_0 0x0002B
  42. #define DPCD_AUD_DEL_INS_15_8 0x0002C
  43. #define DPCD_AUD_DEL_INS_23_16 0x0002D
  44. #define DPCD_GUID 0x00030
  45. #define DPCD_RX_GTC_VALUE_7_0 0x00054
  46. #define DPCD_RX_GTC_VALUE_15_8 0x00055
  47. #define DPCD_RX_GTC_VALUE_23_16 0x00056
  48. #define DPCD_RX_GTC_VALUE_31_24 0x00057
  49. #define DPCD_RX_GTC_MSTR_REQ 0x00058
  50. #define DPCD_RX_GTC_FREQ_LOCK_DONE 0x00059
  51. #define DPCD_DOWNSP_0_CAP 0x00080
  52. #define DPCD_DOWNSP_1_CAP 0x00081
  53. #define DPCD_DOWNSP_2_CAP 0x00082
  54. #define DPCD_DOWNSP_3_CAP 0x00083
  55. #define DPCD_DOWNSP_0_DET_CAP 0x00080
  56. #define DPCD_DOWNSP_1_DET_CAP 0x00084
  57. #define DPCD_DOWNSP_2_DET_CAP 0x00088
  58. #define DPCD_DOWNSP_3_DET_CAP 0x0008C
  59. /* link configuration field */
  60. #define DPCD_LINK_BW_SET 0x00100
  61. #define DPCD_LANE_COUNT_SET 0x00101
  62. #define DPCD_TP_SET 0x00102
  63. #define DPCD_TRAINING_LANE0_SET 0x00103
  64. #define DPCD_TRAINING_LANE1_SET 0x00104
  65. #define DPCD_TRAINING_LANE2_SET 0x00105
  66. #define DPCD_TRAINING_LANE3_SET 0x00106
  67. #define DPCD_DOWNSPREAD_CTRL 0x00107
  68. #define DPCD_ML_CH_CODING_SET 0x00108
  69. #define DPCD_I2C_SPEED_CTL_SET 0x00109
  70. #define DPCD_EDP_CFG_SET 0x0010A
  71. #define DPCD_LINK_QUAL_LANE0_SET 0x0010B
  72. #define DPCD_LINK_QUAL_LANE1_SET 0x0010C
  73. #define DPCD_LINK_QUAL_LANE2_SET 0x0010D
  74. #define DPCD_LINK_QUAL_LANE3_SET 0x0010E
  75. #define DPCD_TRAINING_LANE0_1_SET2 0x0010F
  76. #define DPCD_TRAINING_LANE2_3_SET2 0x00110
  77. #define DPCD_MSTM_CTRL 0x00111
  78. #define DPCD_AUDIO_DELAY_7_0 0x00112
  79. #define DPCD_AUDIO_DELAY_15_8 0x00113
  80. #define DPCD_AUDIO_DELAY_23_6 0x00114
  81. #define DPCD_UPSTREAM_DEVICE_DP_PWR_NEED 0x00118
  82. #define DPCD_FAUX_MODE_CTRL 0x00120
  83. #define DPCD_FAUX_FORWARD_CH_DRIVE_SET 0x00121
  84. #define DPCD_BACK_CH_STATUS 0x00122
  85. #define DPCD_FAUX_BACK_CH_SYMBOL_ERROR_COUNT 0x00123
  86. #define DPCD_FAUX_BACK_CH_TRAINING_PATTERN_TIME 0x00125
  87. #define DPCD_TX_GTC_VALUE_7_0 0x00154
  88. #define DPCD_TX_GTC_VALUE_15_8 0x00155
  89. #define DPCD_TX_GTC_VALUE_23_16 0x00156
  90. #define DPCD_TX_GTC_VALUE_31_24 0x00157
  91. #define DPCD_RX_GTC_VALUE_PHASE_SKEW_EN 0x00158
  92. #define DPCD_TX_GTC_FREQ_LOCK_DONE 0x00159
  93. #define DPCD_ADAPTER_CTRL 0x001A0
  94. #define DPCD_BRANCH_DEVICE_CTRL 0x001A1
  95. #define DPCD_PAYLOAD_ALLOCATE_SET 0x001C0
  96. #define DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1
  97. #define DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2
  98. /* link/sink status field */
  99. #define DPCD_SINK_COUNT 0x00200
  100. #define DPCD_DEVICE_SERVICE_IRQ 0x00201
  101. #define DPCD_STATUS_LANE_0_1 0x00202
  102. #define DPCD_STATUS_LANE_2_3 0x00203
  103. #define DPCD_LANE_ALIGN_STATUS_UPDATED 0x00204
  104. #define DPCD_SINK_STATUS 0x00205
  105. #define DPCD_ADJ_REQ_LANE_0_1 0x00206
  106. #define DPCD_ADJ_REQ_LANE_2_3 0x00207
  107. #define DPCD_TRAINING_SCORE_LANE_0 0x00208
  108. #define DPCD_TRAINING_SCORE_LANE_1 0x00209
  109. #define DPCD_TRAINING_SCORE_LANE_2 0x0020A
  110. #define DPCD_TRAINING_SCORE_LANE_3 0x0020B
  111. #define DPCD_ADJ_REQ_PC2 0x0020C
  112. #define DPCD_FAUX_FORWARD_CH_SYMBOL_ERROR_COUNT 0x0020D
  113. #define DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x00210
  114. #define DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x00212
  115. #define DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x00214
  116. #define DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216
  117. /* automated testing sub-field */
  118. #define DPCD_FAUX_FORWARD_CH_STATUS 0x00280
  119. #define DPCD_FAUX_BACK_CH_DRIVE_SET 0x00281
  120. #define DPCD_FAUX_BACK_CH_SYM_ERR_COUNT_CTRL 0x00282
  121. #define DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x002C0
  122. #define DPCD_VC_PAYLOAD_ID_SLOT(slotnum) \
  123. (DPCD_PAYLOAD_TABLE_UPDATE_STATUS + slotnum)
  124. /* sink control field */
  125. #define DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600
  126. /* sideband message buffers */
  127. #define DPCD_DOWN_REQ 0x01000
  128. #define DPCD_UP_REP 0x01200
  129. #define DPCD_DOWN_REP 0x01400
  130. #define DPCD_UP_REQ 0x01600
  131. /* event status indicator field */
  132. #define DPCD_SINK_COUNT_ESI 0x02002
  133. #define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003
  134. #define DPCD_SINK_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004
  135. #define DPCD_SINK_LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005
  136. #define DPCD_SINK_LANE0_1_STATUS 0x0200C
  137. #define DPCD_SINK_LANE2_3_STATUS 0x0200D
  138. #define DPCD_SINK_ALIGN_STATUS_UPDATED_ESI 0x0200E
  139. #define DPCD_SINK_STATUS_ESI 0x0200F
  140. /*
  141. * field addresses and sizes.
  142. */
  143. #define DPCD_RECEIVER_CAP_FIELD_START DPCD_REV
  144. #define DPCD_RECEIVER_CAP_FIELD_SIZE 0x100
  145. #define DPCD_LINK_CFG_FIELD_START DPCD_LINK_BW_SET
  146. #define DPCD_LINK_CFG_FIELD_SIZE 0x100
  147. #define DPCD_LINK_SINK_STATUS_FIELD_START DPCD_SINK_COUNT
  148. #define DPCD_LINK_SINK_STATUS_FIELD_SIZE 0x17
  149. /* 0x00000: DPCD_REV */
  150. #define DPCD_REV_MNR_MASK 0x0F
  151. #define DPCD_REV_MJR_MASK 0xF0
  152. #define DPCD_REV_MJR_SHIFT 4
  153. /* 0x00001: MAX_LINK_RATE */
  154. #define DPCD_MAX_LINK_RATE_162GBPS 0x06
  155. #define DPCD_MAX_LINK_RATE_270GBPS 0x0A
  156. #define DPCD_MAX_LINK_RATE_540GBPS 0x14
  157. /* 0x00002: MAX_LANE_COUNT */
  158. #define DPCD_MAX_LANE_COUNT_MASK 0x1F
  159. #define DPCD_MAX_LANE_COUNT_1 0x01
  160. #define DPCD_MAX_LANE_COUNT_2 0x02
  161. #define DPCD_MAX_LANE_COUNT_4 0x04
  162. #define DPCD_TPS3_SUPPORT_MASK 0x40
  163. #define DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80
  164. /* 0x00003: MAX_DOWNSPREAD */
  165. #define DPCD_MAX_DOWNSPREAD_MASK 0x01
  166. #define DPCD_NO_AUX_HANDSHAKE_LINK_TRAIN_MASK 0x40
  167. /* 0x00005: DOWNSP_PRESENT */
  168. #define DPCD_DOWNSP_PRESENT_MASK 0x01
  169. #define DPCD_DOWNSP_TYPE_MASK 0x06
  170. #define DPCD_DOWNSP_TYPE_SHIFT 1
  171. #define DPCD_DOWNSP_TYPE_DP 0x0
  172. #define DPCD_DOWNSP_TYPE_AVGA_ADVII 0x1
  173. #define DPCD_DOWNSP_TYPE_DVI_HDMI_DPPP 0x2
  174. #define DPCD_DOWNSP_TYPE_OTHERS 0x3
  175. #define DPCD_DOWNSP_FORMAT_CONV_MASK 0x08
  176. #define DPCD_DOWNSP_DCAP_INFO_AVAIL_MASK 0x10
  177. /* 0x00006, 0x00108: ML_CH_CODING_SUPPORT, ML_CH_CODING_SET */
  178. #define DPCD_ML_CH_CODING_MASK 0x01
  179. /* 0x00007: DOWNSP_COUNT_MSA_OUI */
  180. #define DPCD_DOWNSP_COUNT_MASK 0x0F
  181. #define DPCD_MSA_TIMING_PAR_IGNORED_MASK 0x40
  182. #define DPCD_OUI_SUPPORT_MASK 0x80
  183. /* 0x00008, 0x0000A: RX_PORT[0-1]_CAP_0 */
  184. #define DPCD_RX_PORTX_CAP_0_LOCAL_EDID_PRESENT_MASK 0x02
  185. #define DPCD_RX_PORTX_CAP_0_ASSOC_TO_PRECEDING_PORT_MASK 0x04
  186. /* 0x0000C, 0x00109: I2C_SPEED_CTL_CAP, I2C_SPEED_CTL_SET */
  187. #define DPCD_I2C_SPEED_CTL_NONE 0x00
  188. #define DPCD_I2C_SPEED_CTL_1KBIPS 0x01
  189. #define DPCD_I2C_SPEED_CTL_5KBIPS 0x02
  190. #define DPCD_I2C_SPEED_CTL_10KBIPS 0x04
  191. #define DPCD_I2C_SPEED_CTL_100KBIPS 0x08
  192. #define DPCD_I2C_SPEED_CTL_400KBIPS 0x10
  193. #define DPCD_I2C_SPEED_CTL_1MBIPS 0x20
  194. /* 0x0000E: TRAIN_AUX_RD_INTERVAL */
  195. #define DPCD_TRAIN_AUX_RD_INT_100_400US 0x00
  196. #define DPCD_TRAIN_AUX_RD_INT_4MS 0x01
  197. #define DPCD_TRAIN_AUX_RD_INT_8MS 0x02
  198. #define DPCD_TRAIN_AUX_RD_INT_12MS 0x03
  199. #define DPCD_TRAIN_AUX_RD_INT_16MS 0x04
  200. /* 0x00020: DPCD_FAUX_CAP */
  201. #define DPCD_FAUX_CAP_MASK 0x01
  202. /* 0x00021: MSTM_CAP */
  203. #define DPCD_MST_CAP_MASK 0x01
  204. /* 0x00080, 0x00081|4, 0x00082|8, 0x00083|C: DOWNSP_X_(DET_)CAP */
  205. #define DPCD_DOWNSP_X_CAP_TYPE_MASK 0x07
  206. #define DPCD_DOWNSP_X_CAP_TYPE_DP 0x0
  207. #define DPCD_DOWNSP_X_CAP_TYPE_AVGA 0x1
  208. #define DPCD_DOWNSP_X_CAP_TYPE_DVI 0x2
  209. #define DPCD_DOWNSP_X_CAP_TYPE_HDMI 0x3
  210. #define DPCD_DOWNSP_X_CAP_TYPE_OTHERS 0x4
  211. #define DPCD_DOWNSP_X_CAP_TYPE_DPPP 0x5
  212. #define DPCD_DOWNSP_X_CAP_HPD_MASK 0x80
  213. #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_MASK 0xF0
  214. #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_SHIFT 4
  215. #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_60 0x1
  216. #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_720_480_I_50 0x2
  217. #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_60 0x3
  218. #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1920_1080_I_50 0x4
  219. #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_60 0x5
  220. #define DPCD_DOWNSP_X_CAP_NON_EDID_ATTR_1280_720_P_50 0x7
  221. /* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */
  222. #define DPCD_DOWNSP_X_DCAP_MAX_BPC_MASK 0x03
  223. #define DPCD_DOWNSP_X_DCAP_MAX_BPC_8 0x0
  224. #define DPCD_DOWNSP_X_DCAP_MAX_BPC_10 0x1
  225. #define DPCD_DOWNSP_X_DCAP_MAX_BPC_12 0x2
  226. #define DPCD_DOWNSP_X_DCAP_MAX_BPC_16 0x3
  227. /* 0x00082, 0x00086, 0x0008A, 0x0008E: DOWNSP_X_(DET_)CAP2 */
  228. #define DPCD_DOWNSP_X_DCAP_HDMI_DPPP_FS2FP_MASK 0x01
  229. #define DPCD_DOWNSP_X_DCAP_DVI_DL_MASK 0x02
  230. #define DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04
  231. /* link configuration field masks, shifts, and register values */
  232. /* 0x00100: DPCD_LINK_BW_SET */
  233. #define DPCD_LINK_BW_SET_162GBPS 0x06
  234. #define DPCD_LINK_BW_SET_270GBPS 0x0A
  235. #define DPCD_LINK_BW_SET_540GBPS 0x14
  236. /* 0x00101: LANE_COUNT_SET */
  237. #define DPCD_LANE_COUNT_SET_MASK 0x1F
  238. #define DPCD_LANE_COUNT_SET_1 0x01
  239. #define DPCD_LANE_COUNT_SET_2 0x02
  240. #define DPCD_LANE_COUNT_SET_4 0x04
  241. #define DPCD_ENHANCED_FRAME_EN_MASK 0x80
  242. /* 0x00102: TP_SET */
  243. #define DPCD_TP_SEL_MASK 0x03
  244. #define DPCD_TP_SEL_OFF 0x0
  245. #define DPCD_TP_SEL_TP1 0x1
  246. #define DPCD_TP_SEL_TP2 0x2
  247. #define DPCD_TP_SEL_TP3 0x3
  248. #define DPCD_TP_SET_LQP_MASK 0x06
  249. #define DPCD_TP_SET_LQP_SHIFT 2
  250. #define DPCD_TP_SET_LQP_OFF 0x0
  251. #define DPCD_TP_SET_LQP_D102_TEST 0x1
  252. #define DPCD_TP_SET_LQP_SER_MES 0x2
  253. #define DPCD_TP_SET_LQP_PRBS7 0x3
  254. #define DPCD_TP_SET_REC_CLK_OUT_EN_MASK 0x10
  255. #define DPCD_TP_SET_SCRAMB_DIS_MASK 0x20
  256. #define DPCD_TP_SET_SE_COUNT_SEL_MASK 0xC0
  257. #define DPCD_TP_SET_SE_COUNT_SEL_SHIFT 6
  258. #define DPCD_TP_SET_SE_COUNT_SEL_DE_ISE 0x0
  259. #define DPCD_TP_SET_SE_COUNT_SEL_DE 0x1
  260. #define DPCD_TP_SET_SE_COUNT_SEL_ISE 0x2
  261. /* 0x00103-0x00106: TRAINING_LANE[0-3]_SET */
  262. #define DPCD_TRAINING_LANEX_SET_VS_MASK 0x03
  263. #define DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04
  264. #define DPCD_TRAINING_LANEX_SET_PE_MASK 0x18
  265. #define DPCD_TRAINING_LANEX_SET_PE_SHIFT 3
  266. #define DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20
  267. /* 0x00107: DOWNSPREAD_CTRL */
  268. #define DPCD_SPREAD_AMP_MASK 0x10
  269. #define DPCD_MSA_TIMING_PAR_IGNORED_EN_MASK 0x80
  270. /* 0x00108: ML_CH_CODING_SET - Same as 0x00006: ML_CH_CODING_SUPPORT */
  271. /* 0x00109: I2C_SPEED_CTL_SET - Same as 0x0000C: I2C_SPEED_CTL_CAP */
  272. /* 0x0010F-0x00110: TRAINING_LANE[0_1-2_3]_SET2 */
  273. #define DPCD_TRAINING_LANE_0_2_SET_PC2_MASK 0x03
  274. #define DPCD_TRAINING_LANE_0_2_SET_MAX_PC2_MASK 0x04
  275. #define DPCD_TRAINING_LANE_1_3_SET_PC2_MASK 0x30
  276. #define DPCD_TRAINING_LANE_1_3_SET_PC2_SHIFT 4
  277. #define DPCD_TRAINING_LANE_1_3_SET_MAX_PC2_MASK 0x40
  278. /* 0x00111: MSTM_CTRL */
  279. #define DPCD_MST_EN_MASK 0x01
  280. #define DPCD_UP_REQ_EN_MASK 0x02
  281. #define DPCD_UP_IS_SRC_MASK 0x03
  282. /* link/sink status field masks, shifts, and register values */
  283. /* 0x00200: SINK_COUNT */
  284. #define DPCD_SINK_COUNT_LOW_MASK 0x3F
  285. #define DPCD_SINK_CP_READY_MASK 0x40
  286. #define DPCD_SINK_COUNT_HIGH_MASK 0x80
  287. #define DPCD_SINK_COUNT_HIGH_LOW_SHIFT 1
  288. /* 0x00202: STATUS_LANE_0_1 */
  289. #define DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01
  290. #define DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02
  291. #define DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04
  292. #define DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10
  293. #define DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20
  294. #define DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40
  295. /* 0x00202: STATUS_LANE_2_3 */
  296. #define DPCD_STATUS_LANE_2_CR_DONE_MASK 0x01
  297. #define DPCD_STATUS_LANE_2_CE_DONE_MASK 0x02
  298. #define DPCD_STATUS_LANE_2_SL_DONE_MASK 0x04
  299. #define DPCD_STATUS_LANE_3_CR_DONE_MASK 0x10
  300. #define DPCD_STATUS_LANE_3_CE_DONE_MASK 0x20
  301. #define DPCD_STATUS_LANE_3_SL_DONE_MASK 0x40
  302. /* 0x00204: LANE_ALIGN_STATUS_UPDATED */
  303. #define DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK \
  304. 0x01
  305. #define DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSP_STATUS_CHANGED_MASK \
  306. 0x40
  307. #define DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED_MASK \
  308. 0x80
  309. /* 0x00205: SINK_STATUS */
  310. #define DPCD_SINK_STATUS_RX_PORT0_SYNC_STATUS_MASK 0x01
  311. #define DPCD_SINK_STATUS_RX_PORT1_SYNC_STATUS_MASK 0x02
  312. /* 0x00206, 0x00207: ADJ_REQ_LANE_[0,2]_[1,3] */
  313. #define DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03
  314. #define DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C
  315. #define DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2
  316. #define DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30
  317. #define DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4
  318. #define DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0
  319. #define DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6
  320. /* 0x0020C: ADJ_REQ_PC2 */
  321. #define DPCD_ADJ_REQ_PC2_LANE_0_MASK 0x03
  322. #define DPCD_ADJ_REQ_PC2_LANE_1_MASK 0x0C
  323. #define DPCD_ADJ_REQ_PC2_LANE_1_SHIFT 2
  324. #define DPCD_ADJ_REQ_PC2_LANE_2_MASK 0x30
  325. #define DPCD_ADJ_REQ_PC2_LANE_2_SHIFT 4
  326. #define DPCD_ADJ_REQ_PC2_LANE_3_MASK 0xC0
  327. #define DPCD_ADJ_REQ_PC2_LANE_3_SHIFT 6
  328. #endif /* __GDSYS_LOGICORE_DP_DPCD_H__ */