ivybridge_igd.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <bios_emul.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <fdtdec.h>
  10. #include <log.h>
  11. #include <pci_rom.h>
  12. #include <vbe.h>
  13. #include <video.h>
  14. #include <asm/intel_regs.h>
  15. #include <asm/io.h>
  16. #include <asm/mtrr.h>
  17. #include <asm/pci.h>
  18. #include <asm/arch/pch.h>
  19. #include <asm/arch/sandybridge.h>
  20. #include <linux/delay.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. struct gt_powermeter {
  23. u16 reg;
  24. u32 value;
  25. };
  26. /* These are magic values - unfortunately the meaning is unknown */
  27. static const struct gt_powermeter snb_pm_gt1[] = {
  28. { 0xa200, 0xcc000000 },
  29. { 0xa204, 0x07000040 },
  30. { 0xa208, 0x0000fe00 },
  31. { 0xa20c, 0x00000000 },
  32. { 0xa210, 0x17000000 },
  33. { 0xa214, 0x00000021 },
  34. { 0xa218, 0x0817fe19 },
  35. { 0xa21c, 0x00000000 },
  36. { 0xa220, 0x00000000 },
  37. { 0xa224, 0xcc000000 },
  38. { 0xa228, 0x07000040 },
  39. { 0xa22c, 0x0000fe00 },
  40. { 0xa230, 0x00000000 },
  41. { 0xa234, 0x17000000 },
  42. { 0xa238, 0x00000021 },
  43. { 0xa23c, 0x0817fe19 },
  44. { 0xa240, 0x00000000 },
  45. { 0xa244, 0x00000000 },
  46. { 0xa248, 0x8000421e },
  47. { 0 }
  48. };
  49. static const struct gt_powermeter snb_pm_gt2[] = {
  50. { 0xa200, 0x330000a6 },
  51. { 0xa204, 0x402d0031 },
  52. { 0xa208, 0x00165f83 },
  53. { 0xa20c, 0xf1000000 },
  54. { 0xa210, 0x00000000 },
  55. { 0xa214, 0x00160016 },
  56. { 0xa218, 0x002a002b },
  57. { 0xa21c, 0x00000000 },
  58. { 0xa220, 0x00000000 },
  59. { 0xa224, 0x330000a6 },
  60. { 0xa228, 0x402d0031 },
  61. { 0xa22c, 0x00165f83 },
  62. { 0xa230, 0xf1000000 },
  63. { 0xa234, 0x00000000 },
  64. { 0xa238, 0x00160016 },
  65. { 0xa23c, 0x002a002b },
  66. { 0xa240, 0x00000000 },
  67. { 0xa244, 0x00000000 },
  68. { 0xa248, 0x8000421e },
  69. { 0 }
  70. };
  71. static const struct gt_powermeter ivb_pm_gt1[] = {
  72. { 0xa800, 0x00000000 },
  73. { 0xa804, 0x00021c00 },
  74. { 0xa808, 0x00000403 },
  75. { 0xa80c, 0x02001700 },
  76. { 0xa810, 0x05000200 },
  77. { 0xa814, 0x00000000 },
  78. { 0xa818, 0x00690500 },
  79. { 0xa81c, 0x0000007f },
  80. { 0xa820, 0x01002501 },
  81. { 0xa824, 0x00000300 },
  82. { 0xa828, 0x01000331 },
  83. { 0xa82c, 0x0000000c },
  84. { 0xa830, 0x00010016 },
  85. { 0xa834, 0x01100101 },
  86. { 0xa838, 0x00010103 },
  87. { 0xa83c, 0x00041300 },
  88. { 0xa840, 0x00000b30 },
  89. { 0xa844, 0x00000000 },
  90. { 0xa848, 0x7f000000 },
  91. { 0xa84c, 0x05000008 },
  92. { 0xa850, 0x00000001 },
  93. { 0xa854, 0x00000004 },
  94. { 0xa858, 0x00000007 },
  95. { 0xa85c, 0x00000000 },
  96. { 0xa860, 0x00010000 },
  97. { 0xa248, 0x0000221e },
  98. { 0xa900, 0x00000000 },
  99. { 0xa904, 0x00001c00 },
  100. { 0xa908, 0x00000000 },
  101. { 0xa90c, 0x06000000 },
  102. { 0xa910, 0x09000200 },
  103. { 0xa914, 0x00000000 },
  104. { 0xa918, 0x00590000 },
  105. { 0xa91c, 0x00000000 },
  106. { 0xa920, 0x04002501 },
  107. { 0xa924, 0x00000100 },
  108. { 0xa928, 0x03000410 },
  109. { 0xa92c, 0x00000000 },
  110. { 0xa930, 0x00020000 },
  111. { 0xa934, 0x02070106 },
  112. { 0xa938, 0x00010100 },
  113. { 0xa93c, 0x00401c00 },
  114. { 0xa940, 0x00000000 },
  115. { 0xa944, 0x00000000 },
  116. { 0xa948, 0x10000e00 },
  117. { 0xa94c, 0x02000004 },
  118. { 0xa950, 0x00000001 },
  119. { 0xa954, 0x00000004 },
  120. { 0xa960, 0x00060000 },
  121. { 0xaa3c, 0x00001c00 },
  122. { 0xaa54, 0x00000004 },
  123. { 0xaa60, 0x00060000 },
  124. { 0 }
  125. };
  126. static const struct gt_powermeter ivb_pm_gt2_17w[] = {
  127. { 0xa800, 0x20000000 },
  128. { 0xa804, 0x000e3800 },
  129. { 0xa808, 0x00000806 },
  130. { 0xa80c, 0x0c002f00 },
  131. { 0xa810, 0x0c000800 },
  132. { 0xa814, 0x00000000 },
  133. { 0xa818, 0x00d20d00 },
  134. { 0xa81c, 0x000000ff },
  135. { 0xa820, 0x03004b02 },
  136. { 0xa824, 0x00000600 },
  137. { 0xa828, 0x07000773 },
  138. { 0xa82c, 0x00000000 },
  139. { 0xa830, 0x00020032 },
  140. { 0xa834, 0x1520040d },
  141. { 0xa838, 0x00020105 },
  142. { 0xa83c, 0x00083700 },
  143. { 0xa840, 0x000016ff },
  144. { 0xa844, 0x00000000 },
  145. { 0xa848, 0xff000000 },
  146. { 0xa84c, 0x0a000010 },
  147. { 0xa850, 0x00000002 },
  148. { 0xa854, 0x00000008 },
  149. { 0xa858, 0x0000000f },
  150. { 0xa85c, 0x00000000 },
  151. { 0xa860, 0x00020000 },
  152. { 0xa248, 0x0000221e },
  153. { 0xa900, 0x00000000 },
  154. { 0xa904, 0x00003800 },
  155. { 0xa908, 0x00000000 },
  156. { 0xa90c, 0x0c000000 },
  157. { 0xa910, 0x12000800 },
  158. { 0xa914, 0x00000000 },
  159. { 0xa918, 0x00b20000 },
  160. { 0xa91c, 0x00000000 },
  161. { 0xa920, 0x08004b02 },
  162. { 0xa924, 0x00000300 },
  163. { 0xa928, 0x01000820 },
  164. { 0xa92c, 0x00000000 },
  165. { 0xa930, 0x00030000 },
  166. { 0xa934, 0x15150406 },
  167. { 0xa938, 0x00020300 },
  168. { 0xa93c, 0x00903900 },
  169. { 0xa940, 0x00000000 },
  170. { 0xa944, 0x00000000 },
  171. { 0xa948, 0x20001b00 },
  172. { 0xa94c, 0x0a000010 },
  173. { 0xa950, 0x00000000 },
  174. { 0xa954, 0x00000008 },
  175. { 0xa960, 0x00110000 },
  176. { 0xaa3c, 0x00003900 },
  177. { 0xaa54, 0x00000008 },
  178. { 0xaa60, 0x00110000 },
  179. { 0 }
  180. };
  181. static const struct gt_powermeter ivb_pm_gt2_35w[] = {
  182. { 0xa800, 0x00000000 },
  183. { 0xa804, 0x00030400 },
  184. { 0xa808, 0x00000806 },
  185. { 0xa80c, 0x0c002f00 },
  186. { 0xa810, 0x0c000300 },
  187. { 0xa814, 0x00000000 },
  188. { 0xa818, 0x00d20d00 },
  189. { 0xa81c, 0x000000ff },
  190. { 0xa820, 0x03004b02 },
  191. { 0xa824, 0x00000600 },
  192. { 0xa828, 0x07000773 },
  193. { 0xa82c, 0x00000000 },
  194. { 0xa830, 0x00020032 },
  195. { 0xa834, 0x1520040d },
  196. { 0xa838, 0x00020105 },
  197. { 0xa83c, 0x00083700 },
  198. { 0xa840, 0x000016ff },
  199. { 0xa844, 0x00000000 },
  200. { 0xa848, 0xff000000 },
  201. { 0xa84c, 0x0a000010 },
  202. { 0xa850, 0x00000001 },
  203. { 0xa854, 0x00000008 },
  204. { 0xa858, 0x00000008 },
  205. { 0xa85c, 0x00000000 },
  206. { 0xa860, 0x00020000 },
  207. { 0xa248, 0x0000221e },
  208. { 0xa900, 0x00000000 },
  209. { 0xa904, 0x00003800 },
  210. { 0xa908, 0x00000000 },
  211. { 0xa90c, 0x0c000000 },
  212. { 0xa910, 0x12000800 },
  213. { 0xa914, 0x00000000 },
  214. { 0xa918, 0x00b20000 },
  215. { 0xa91c, 0x00000000 },
  216. { 0xa920, 0x08004b02 },
  217. { 0xa924, 0x00000300 },
  218. { 0xa928, 0x01000820 },
  219. { 0xa92c, 0x00000000 },
  220. { 0xa930, 0x00030000 },
  221. { 0xa934, 0x15150406 },
  222. { 0xa938, 0x00020300 },
  223. { 0xa93c, 0x00903900 },
  224. { 0xa940, 0x00000000 },
  225. { 0xa944, 0x00000000 },
  226. { 0xa948, 0x20001b00 },
  227. { 0xa94c, 0x0a000010 },
  228. { 0xa950, 0x00000000 },
  229. { 0xa954, 0x00000008 },
  230. { 0xa960, 0x00110000 },
  231. { 0xaa3c, 0x00003900 },
  232. { 0xaa54, 0x00000008 },
  233. { 0xaa60, 0x00110000 },
  234. { 0 }
  235. };
  236. static inline u32 gtt_read(void *bar, u32 reg)
  237. {
  238. return readl(bar + reg);
  239. }
  240. static inline void gtt_write(void *bar, u32 reg, u32 data)
  241. {
  242. writel(data, bar + reg);
  243. }
  244. static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
  245. {
  246. for (; pm && pm->reg; pm++)
  247. gtt_write(bar, pm->reg, pm->value);
  248. }
  249. #define GTT_RETRY 1000
  250. static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
  251. {
  252. unsigned try = GTT_RETRY;
  253. u32 data;
  254. while (try--) {
  255. data = gtt_read(bar, reg);
  256. if ((data & mask) == value)
  257. return 1;
  258. udelay(10);
  259. }
  260. printf("GT init timeout\n");
  261. return 0;
  262. }
  263. static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
  264. {
  265. u32 reg32;
  266. debug("GT Power Management Init, silicon = %#x\n", rev);
  267. if (rev < IVB_STEP_C0) {
  268. /* 1: Enable force wake */
  269. gtt_write(gtt_bar, 0xa18c, 0x00000001);
  270. gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
  271. } else {
  272. gtt_write(gtt_bar, 0xa180, 1 << 5);
  273. gtt_write(gtt_bar, 0xa188, 0xffff0001);
  274. gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
  275. }
  276. if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
  277. /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
  278. reg32 = gtt_read(gtt_bar, 0x42004);
  279. reg32 |= (1 << 14) | (1 << 15);
  280. gtt_write(gtt_bar, 0x42004, reg32);
  281. }
  282. if (rev >= IVB_STEP_A0) {
  283. /* Display Reset Acknowledge Settings */
  284. reg32 = gtt_read(gtt_bar, 0x45010);
  285. reg32 |= (1 << 1) | (1 << 0);
  286. gtt_write(gtt_bar, 0x45010, reg32);
  287. }
  288. /* 2: Get GT SKU from GTT+0x911c[13] */
  289. reg32 = gtt_read(gtt_bar, 0x911c);
  290. if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
  291. if (reg32 & (1 << 13)) {
  292. debug("SNB GT1 Power Meter Weights\n");
  293. gtt_write_powermeter(gtt_bar, snb_pm_gt1);
  294. } else {
  295. debug("SNB GT2 Power Meter Weights\n");
  296. gtt_write_powermeter(gtt_bar, snb_pm_gt2);
  297. }
  298. } else {
  299. u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
  300. if (reg32 & (1 << 13)) {
  301. /* GT1 SKU */
  302. debug("IVB GT1 Power Meter Weights\n");
  303. gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
  304. } else {
  305. /* GT2 SKU */
  306. u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
  307. tdp /= (1 << unit);
  308. if (tdp <= 17) {
  309. /* <=17W ULV */
  310. debug("IVB GT2 17W Power Meter Weights\n");
  311. gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
  312. } else if ((tdp >= 25) && (tdp <= 35)) {
  313. /* 25W-35W */
  314. debug("IVB GT2 25W-35W Power Meter Weights\n");
  315. gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
  316. } else {
  317. /* All others */
  318. debug("IVB GT2 35W Power Meter Weights\n");
  319. gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
  320. }
  321. }
  322. }
  323. /* 3: Gear ratio map */
  324. gtt_write(gtt_bar, 0xa004, 0x00000010);
  325. /* 4: GFXPAUSE */
  326. gtt_write(gtt_bar, 0xa000, 0x00070020);
  327. /* 5: Dynamic EU trip control */
  328. gtt_write(gtt_bar, 0xa080, 0x00000004);
  329. /* 6: ECO bits */
  330. reg32 = gtt_read(gtt_bar, 0xa180);
  331. reg32 |= (1 << 26) | (1 << 31);
  332. /* (bit 20=1 for SNB step D1+ / IVB A0+) */
  333. if (rev >= SNB_STEP_D1)
  334. reg32 |= (1 << 20);
  335. gtt_write(gtt_bar, 0xa180, reg32);
  336. /* 6a: for SnB step D2+ only */
  337. if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
  338. (rev >= SNB_STEP_D2)) {
  339. reg32 = gtt_read(gtt_bar, 0x9400);
  340. reg32 |= (1 << 7);
  341. gtt_write(gtt_bar, 0x9400, reg32);
  342. reg32 = gtt_read(gtt_bar, 0x941c);
  343. reg32 &= 0xf;
  344. reg32 |= (1 << 1);
  345. gtt_write(gtt_bar, 0x941c, reg32);
  346. gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
  347. }
  348. if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
  349. reg32 = gtt_read(gtt_bar, 0x907c);
  350. reg32 |= (1 << 16);
  351. gtt_write(gtt_bar, 0x907c, reg32);
  352. /* 6b: Clocking reset controls */
  353. gtt_write(gtt_bar, 0x9424, 0x00000001);
  354. } else {
  355. /* 6b: Clocking reset controls */
  356. gtt_write(gtt_bar, 0x9424, 0x00000000);
  357. }
  358. /* 7 */
  359. if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
  360. gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
  361. /* Mailbox Cmd for RC6 VID */
  362. gtt_write(gtt_bar, 0x138124, 0x80000004);
  363. if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
  364. gtt_write(gtt_bar, 0x138124, 0x8000000a);
  365. gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
  366. }
  367. /* 8 */
  368. gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
  369. gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
  370. gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
  371. gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
  372. gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
  373. gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
  374. /* 9 */
  375. gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
  376. gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
  377. gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
  378. /* 10 */
  379. gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
  380. gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
  381. gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
  382. gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
  383. gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
  384. /* 11 */
  385. gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
  386. gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
  387. gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
  388. gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
  389. gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
  390. gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
  391. gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
  392. /* 11a: Enable Render Standby (RC6) */
  393. if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
  394. /*
  395. * IvyBridge should also support DeepRenderStandby.
  396. *
  397. * Unfortunately it does not work reliably on all SKUs so
  398. * disable it here and it can be enabled by the kernel.
  399. */
  400. gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
  401. } else {
  402. gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
  403. }
  404. /* 12: Normal Frequency Request */
  405. /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
  406. reg32 = readl(MCHBAR_REG(0x5998));
  407. reg32 >>= 16;
  408. reg32 &= 0xef;
  409. reg32 <<= 25;
  410. gtt_write(gtt_bar, 0xa008, reg32);
  411. /* 13: RP Control */
  412. gtt_write(gtt_bar, 0xa024, 0x00000592);
  413. /* 14: Enable PM Interrupts */
  414. gtt_write(gtt_bar, 0x4402c, 0x03000076);
  415. /* Clear 0x6c024 [8:6] */
  416. reg32 = gtt_read(gtt_bar, 0x6c024);
  417. reg32 &= ~0x000001c0;
  418. gtt_write(gtt_bar, 0x6c024, reg32);
  419. return 0;
  420. }
  421. static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
  422. {
  423. const void *blob = gd->fdt_blob;
  424. int node = dev_of_offset(dev);
  425. u32 reg32, cycle_delay;
  426. debug("GT Power Management Init (post VBIOS)\n");
  427. /* 15: Deassert Force Wake */
  428. if (rev < IVB_STEP_C0) {
  429. gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
  430. gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
  431. } else {
  432. gtt_write(gtt_bar, 0xa188, 0x1fffe);
  433. if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
  434. gtt_write(gtt_bar, 0xa188,
  435. gtt_read(gtt_bar, 0xa188) | 1);
  436. }
  437. }
  438. /* 16: SW RC Control */
  439. gtt_write(gtt_bar, 0xa094, 0x00060000);
  440. /* Setup Digital Port Hotplug */
  441. reg32 = gtt_read(gtt_bar, 0xc4030);
  442. if (!reg32) {
  443. u32 dp_hotplug[3];
  444. if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
  445. dp_hotplug, ARRAY_SIZE(dp_hotplug)))
  446. return -EINVAL;
  447. reg32 = (dp_hotplug[0] & 0x7) << 2;
  448. reg32 |= (dp_hotplug[0] & 0x7) << 10;
  449. reg32 |= (dp_hotplug[0] & 0x7) << 18;
  450. gtt_write(gtt_bar, 0xc4030, reg32);
  451. }
  452. /* Setup Panel Power On Delays */
  453. reg32 = gtt_read(gtt_bar, 0xc7208);
  454. if (!reg32) {
  455. reg32 = (unsigned)fdtdec_get_int(blob, node,
  456. "panel-port-select", 0) << 30;
  457. reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
  458. << 16;
  459. reg32 |= fdtdec_get_int(blob, node,
  460. "panel-power-backlight-on-delay", 0);
  461. gtt_write(gtt_bar, 0xc7208, reg32);
  462. }
  463. /* Setup Panel Power Off Delays */
  464. reg32 = gtt_read(gtt_bar, 0xc720c);
  465. if (!reg32) {
  466. reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
  467. << 16;
  468. reg32 |= fdtdec_get_int(blob, node,
  469. "panel-power-backlight-off-delay", 0);
  470. gtt_write(gtt_bar, 0xc720c, reg32);
  471. }
  472. /* Setup Panel Power Cycle Delay */
  473. cycle_delay = fdtdec_get_int(blob, node,
  474. "intel,panel-power-cycle-delay", 0);
  475. if (cycle_delay) {
  476. reg32 = gtt_read(gtt_bar, 0xc7210);
  477. reg32 &= ~0xff;
  478. reg32 |= cycle_delay;
  479. gtt_write(gtt_bar, 0xc7210, reg32);
  480. }
  481. /* Enable Backlight if needed */
  482. reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
  483. if (reg32) {
  484. gtt_write(gtt_bar, 0x48250, (1 << 31));
  485. gtt_write(gtt_bar, 0x48254, reg32);
  486. }
  487. reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
  488. if (reg32) {
  489. gtt_write(gtt_bar, 0xc8250, (1 << 31));
  490. gtt_write(gtt_bar, 0xc8254, reg32);
  491. }
  492. return 0;
  493. }
  494. /*
  495. * Some vga option roms are used for several chipsets but they only have one
  496. * PCI ID in their header. If we encounter such an option rom, we need to do
  497. * the mapping ourselves.
  498. */
  499. uint32_t board_map_oprom_vendev(uint32_t vendev)
  500. {
  501. switch (vendev) {
  502. case 0x80860102: /* GT1 Desktop */
  503. case 0x8086010a: /* GT1 Server */
  504. case 0x80860112: /* GT2 Desktop */
  505. case 0x80860116: /* GT2 Mobile */
  506. case 0x80860122: /* GT2 Desktop >=1.3GHz */
  507. case 0x80860126: /* GT2 Mobile >=1.3GHz */
  508. case 0x80860156: /* IVB */
  509. case 0x80860166: /* IVB */
  510. return 0x80860106; /* GT1 Mobile */
  511. }
  512. return vendev;
  513. }
  514. static int int15_handler(void)
  515. {
  516. int res = 0;
  517. debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
  518. switch (M.x86.R_AX) {
  519. case 0x5f34:
  520. /*
  521. * Set Panel Fitting Hook:
  522. * bit 2 = Graphics Stretching
  523. * bit 1 = Text Stretching
  524. * bit 0 = Centering (do not set with bit1 or bit2)
  525. * 0 = video bios default
  526. */
  527. M.x86.R_AX = 0x005f;
  528. M.x86.R_CL = 0x00; /* Use video bios default */
  529. res = 1;
  530. break;
  531. case 0x5f35:
  532. /*
  533. * Boot Display Device Hook:
  534. * bit 0 = CRT
  535. * bit 1 = TV (eDP)
  536. * bit 2 = EFP
  537. * bit 3 = LFP
  538. * bit 4 = CRT2
  539. * bit 5 = TV2 (eDP)
  540. * bit 6 = EFP2
  541. * bit 7 = LFP2
  542. */
  543. M.x86.R_AX = 0x005f;
  544. M.x86.R_CX = 0x0000; /* Use video bios default */
  545. res = 1;
  546. break;
  547. case 0x5f51:
  548. /*
  549. * Hook to select active LFP configuration:
  550. * 00h = No LVDS, VBIOS does not enable LVDS
  551. * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
  552. * 02h = SVDO-LVDS, LFP driven by SVDO decoder
  553. * 03h = eDP, LFP Driven by Int-DisplayPort encoder
  554. */
  555. M.x86.R_AX = 0x005f;
  556. M.x86.R_CX = 0x0003; /* eDP */
  557. res = 1;
  558. break;
  559. case 0x5f70:
  560. switch (M.x86.R_CH) {
  561. case 0:
  562. /* Get Mux */
  563. M.x86.R_AX = 0x005f;
  564. M.x86.R_CX = 0x0000;
  565. res = 1;
  566. break;
  567. case 1:
  568. /* Set Mux */
  569. M.x86.R_AX = 0x005f;
  570. M.x86.R_CX = 0x0000;
  571. res = 1;
  572. break;
  573. case 2:
  574. /* Get SG/Non-SG mode */
  575. M.x86.R_AX = 0x005f;
  576. M.x86.R_CX = 0x0000;
  577. res = 1;
  578. break;
  579. default:
  580. /* Interrupt was not handled */
  581. debug("Unknown INT15 5f70 function: 0x%02x\n",
  582. M.x86.R_CH);
  583. break;
  584. }
  585. break;
  586. case 0x5fac:
  587. res = 1;
  588. break;
  589. default:
  590. debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
  591. break;
  592. }
  593. return res;
  594. }
  595. static void sandybridge_setup_graphics(struct udevice *dev,
  596. struct udevice *video_dev)
  597. {
  598. u32 reg32;
  599. u16 reg16;
  600. u8 reg8;
  601. dm_pci_read_config16(video_dev, PCI_DEVICE_ID, &reg16);
  602. switch (reg16) {
  603. case 0x0102: /* GT1 Desktop */
  604. case 0x0106: /* GT1 Mobile */
  605. case 0x010a: /* GT1 Server */
  606. case 0x0112: /* GT2 Desktop */
  607. case 0x0116: /* GT2 Mobile */
  608. case 0x0122: /* GT2 Desktop >=1.3GHz */
  609. case 0x0126: /* GT2 Mobile >=1.3GHz */
  610. case 0x0156: /* IvyBridge */
  611. case 0x0166: /* IvyBridge */
  612. break;
  613. default:
  614. debug("Graphics not supported by this CPU/chipset\n");
  615. return;
  616. }
  617. debug("Initialising Graphics\n");
  618. /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
  619. dm_pci_read_config16(dev, GGC, &reg16);
  620. reg16 &= ~0x00f8;
  621. reg16 |= 1 << 3;
  622. /* Program GTT memory by setting GGC[9:8] = 2MB */
  623. reg16 &= ~0x0300;
  624. reg16 |= 2 << 8;
  625. /* Enable VGA decode */
  626. reg16 &= ~0x0002;
  627. dm_pci_write_config16(dev, GGC, reg16);
  628. /* Enable 256MB aperture */
  629. dm_pci_read_config8(video_dev, MSAC, &reg8);
  630. reg8 &= ~0x06;
  631. reg8 |= 0x02;
  632. dm_pci_write_config8(video_dev, MSAC, reg8);
  633. /* Erratum workarounds */
  634. reg32 = readl(MCHBAR_REG(0x5f00));
  635. reg32 |= (1 << 9) | (1 << 10);
  636. writel(reg32, MCHBAR_REG(0x5f00));
  637. /* Enable SA Clock Gating */
  638. reg32 = readl(MCHBAR_REG(0x5f00));
  639. writel(reg32 | 1, MCHBAR_REG(0x5f00));
  640. /* GPU RC6 workaround for sighting 366252 */
  641. reg32 = readl(MCHBAR_REG(0x5d14));
  642. reg32 |= (1 << 31);
  643. writel(reg32, MCHBAR_REG(0x5d14));
  644. /* VLW */
  645. reg32 = readl(MCHBAR_REG(0x6120));
  646. reg32 &= ~(1 << 0);
  647. writel(reg32, MCHBAR_REG(0x6120));
  648. reg32 = readl(MCHBAR_REG(0x5418));
  649. reg32 |= (1 << 4) | (1 << 5);
  650. writel(reg32, MCHBAR_REG(0x5418));
  651. }
  652. static int gma_func0_init(struct udevice *dev)
  653. {
  654. struct udevice *nbridge;
  655. void *gtt_bar;
  656. u32 reg32;
  657. int ret;
  658. int rev;
  659. /* Enable PCH Display Port */
  660. writew(0x0010, RCB_REG(DISPBDF));
  661. setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
  662. ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
  663. if (ret)
  664. return ret;
  665. rev = bridge_silicon_revision(nbridge);
  666. sandybridge_setup_graphics(nbridge, dev);
  667. /* IGD needs to be Bus Master */
  668. dm_pci_read_config32(dev, PCI_COMMAND, &reg32);
  669. reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
  670. dm_pci_write_config32(dev, PCI_COMMAND, reg32);
  671. gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
  672. debug("GT bar %p\n", gtt_bar);
  673. ret = gma_pm_init_pre_vbios(gtt_bar, rev);
  674. if (ret)
  675. return ret;
  676. return rev;
  677. }
  678. static int bd82x6x_video_probe(struct udevice *dev)
  679. {
  680. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  681. ulong fbbase;
  682. void *gtt_bar;
  683. int ret, rev;
  684. rev = gma_func0_init(dev);
  685. if (rev < 0)
  686. return rev;
  687. ret = vbe_setup_video(dev, int15_handler);
  688. if (ret)
  689. return ret;
  690. /* Post VBIOS init */
  691. gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
  692. ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
  693. if (ret)
  694. return ret;
  695. /* Use write-combining for the graphics memory, 256MB */
  696. fbbase = IS_ENABLED(CONFIG_VIDEO_COPY) ? plat->copy_base : plat->base;
  697. mtrr_add_request(MTRR_TYPE_WRCOMB, fbbase, 256 << 20);
  698. mtrr_commit(true);
  699. return 0;
  700. }
  701. static int bd82x6x_video_bind(struct udevice *dev)
  702. {
  703. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  704. /* Set the maximum supported resolution */
  705. uc_plat->size = 2560 * 1600 * 4;
  706. log_debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  707. return 0;
  708. }
  709. static const struct udevice_id bd82x6x_video_ids[] = {
  710. { .compatible = "intel,gma" },
  711. { }
  712. };
  713. U_BOOT_DRIVER(bd82x6x_video) = {
  714. .name = "bd82x6x_video",
  715. .id = UCLASS_VIDEO,
  716. .of_match = bd82x6x_video_ids,
  717. .bind = bd82x6x_video_bind,
  718. .probe = bd82x6x_video_probe,
  719. };