ipu_regs.h 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Porting to u-boot:
  4. *
  5. * (C) Copyright 2010
  6. * Stefano Babic, DENX Software Engineering, sbabic@denx.de
  7. *
  8. * Linux IPU driver for MX51:
  9. *
  10. * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
  11. */
  12. #ifndef __IPU_REGS_INCLUDED__
  13. #define __IPU_REGS_INCLUDED__
  14. #define IPU_DISP0_BASE 0x00000000
  15. #define IPU_MCU_T_DEFAULT 8
  16. #define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)
  17. #define IPU_CM_REG_BASE 0x00000000
  18. #define IPU_STAT_REG_BASE 0x00000200
  19. #define IPU_IDMAC_REG_BASE 0x00008000
  20. #define IPU_ISP_REG_BASE 0x00010000
  21. #define IPU_DP_REG_BASE 0x00018000
  22. #define IPU_IC_REG_BASE 0x00020000
  23. #define IPU_IRT_REG_BASE 0x00028000
  24. #define IPU_CSI0_REG_BASE 0x00030000
  25. #define IPU_CSI1_REG_BASE 0x00038000
  26. #define IPU_DI0_REG_BASE 0x00040000
  27. #define IPU_DI1_REG_BASE 0x00048000
  28. #define IPU_SMFC_REG_BASE 0x00050000
  29. #define IPU_DC_REG_BASE 0x00058000
  30. #define IPU_DMFC_REG_BASE 0x00060000
  31. #define IPU_VDI_REG_BASE 0x00680000
  32. #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
  33. #define IPU_CPMEM_REG_BASE 0x01000000
  34. #define IPU_LUT_REG_BASE 0x01020000
  35. #define IPU_SRM_REG_BASE 0x01040000
  36. #define IPU_TPM_REG_BASE 0x01060000
  37. #define IPU_DC_TMPL_REG_BASE 0x01080000
  38. #define IPU_ISP_TBPR_REG_BASE 0x010C0000
  39. #elif defined(CONFIG_MX6)
  40. #define IPU_CPMEM_REG_BASE 0x00100000
  41. #define IPU_LUT_REG_BASE 0x00120000
  42. #define IPU_SRM_REG_BASE 0x00140000
  43. #define IPU_TPM_REG_BASE 0x00160000
  44. #define IPU_DC_TMPL_REG_BASE 0x00180000
  45. #define IPU_ISP_TBPR_REG_BASE 0x001C0000
  46. #endif
  47. #define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
  48. extern u32 *ipu_dc_tmpl_reg;
  49. #define DC_EVT_NF 0
  50. #define DC_EVT_NL 1
  51. #define DC_EVT_EOF 2
  52. #define DC_EVT_NFIELD 3
  53. #define DC_EVT_EOL 4
  54. #define DC_EVT_EOFIELD 5
  55. #define DC_EVT_NEW_ADDR 6
  56. #define DC_EVT_NEW_CHAN 7
  57. #define DC_EVT_NEW_DATA 8
  58. #define DC_EVT_NEW_ADDR_W_0 0
  59. #define DC_EVT_NEW_ADDR_W_1 1
  60. #define DC_EVT_NEW_CHAN_W_0 2
  61. #define DC_EVT_NEW_CHAN_W_1 3
  62. #define DC_EVT_NEW_DATA_W_0 4
  63. #define DC_EVT_NEW_DATA_W_1 5
  64. #define DC_EVT_NEW_ADDR_R_0 6
  65. #define DC_EVT_NEW_ADDR_R_1 7
  66. #define DC_EVT_NEW_CHAN_R_0 8
  67. #define DC_EVT_NEW_CHAN_R_1 9
  68. #define DC_EVT_NEW_DATA_R_0 10
  69. #define DC_EVT_NEW_DATA_R_1 11
  70. /* Software reset for ipu */
  71. #define SW_IPU_RST 8
  72. enum {
  73. IPU_CONF_DP_EN = 0x00000020,
  74. IPU_CONF_DI0_EN = 0x00000040,
  75. IPU_CONF_DI1_EN = 0x00000080,
  76. IPU_CONF_DMFC_EN = 0x00000400,
  77. IPU_CONF_DC_EN = 0x00000200,
  78. DI0_COUNTER_RELEASE = 0x01000000,
  79. DI1_COUNTER_RELEASE = 0x02000000,
  80. DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
  81. DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
  82. DI_GEN_DI_CLK_EXT = 0x100000,
  83. DI_GEN_POLARITY_1 = 0x00000001,
  84. DI_GEN_POLARITY_2 = 0x00000002,
  85. DI_GEN_POLARITY_3 = 0x00000004,
  86. DI_GEN_POLARITY_4 = 0x00000008,
  87. DI_GEN_POLARITY_5 = 0x00000010,
  88. DI_GEN_POLARITY_6 = 0x00000020,
  89. DI_GEN_POLARITY_7 = 0x00000040,
  90. DI_GEN_POLARITY_8 = 0x00000080,
  91. DI_GEN_POL_CLK = 0x20000,
  92. DI_POL_DRDY_DATA_POLARITY = 0x00000080,
  93. DI_POL_DRDY_POLARITY_15 = 0x00000010,
  94. DI_VSYNC_SEL_OFFSET = 13,
  95. DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
  96. DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
  97. DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
  98. DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
  99. DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
  100. DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
  101. DP_COM_CONF_FG_EN = 0x00000001,
  102. DP_COM_CONF_GWSEL = 0x00000002,
  103. DP_COM_CONF_GWAM = 0x00000004,
  104. DP_COM_CONF_GWCKE = 0x00000008,
  105. DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
  106. DP_COM_CONF_CSC_DEF_OFFSET = 8,
  107. DP_COM_CONF_CSC_DEF_FG = 0x00000300,
  108. DP_COM_CONF_CSC_DEF_BG = 0x00000200,
  109. DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
  110. DP_COM_CONF_GAMMA_EN = 0x00001000,
  111. DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
  112. };
  113. enum di_pins {
  114. DI_PIN11 = 0,
  115. DI_PIN12 = 1,
  116. DI_PIN13 = 2,
  117. DI_PIN14 = 3,
  118. DI_PIN15 = 4,
  119. DI_PIN16 = 5,
  120. DI_PIN17 = 6,
  121. DI_PIN_CS = 7,
  122. DI_PIN_SER_CLK = 0,
  123. DI_PIN_SER_RS = 1,
  124. };
  125. enum di_sync_wave {
  126. DI_SYNC_NONE = -1,
  127. DI_SYNC_CLK = 0,
  128. DI_SYNC_INT_HSYNC = 1,
  129. DI_SYNC_HSYNC = 2,
  130. DI_SYNC_VSYNC = 3,
  131. DI_SYNC_DE = 5,
  132. };
  133. struct ipu_cm {
  134. u32 conf;
  135. u32 sisg_ctrl0;
  136. u32 sisg_ctrl1;
  137. u32 sisg_set[6];
  138. u32 sisg_clear[6];
  139. u32 int_ctrl[15];
  140. u32 sdma_event[10];
  141. u32 srm_pri1;
  142. u32 srm_pri2;
  143. u32 fs_proc_flow[3];
  144. u32 fs_disp_flow[2];
  145. u32 skip;
  146. u32 disp_alt_conf;
  147. u32 disp_gen;
  148. u32 disp_alt[4];
  149. u32 snoop;
  150. u32 mem_rst;
  151. u32 pm;
  152. u32 gpr;
  153. u32 reserved0[26];
  154. u32 ch_db_mode_sel[2];
  155. u32 reserved1[4];
  156. u32 alt_ch_db_mode_sel[2];
  157. u32 reserved2[2];
  158. u32 ch_trb_mode_sel[2];
  159. };
  160. struct ipu_idmac {
  161. u32 conf;
  162. u32 ch_en[2];
  163. u32 sep_alpha;
  164. u32 alt_sep_alpha;
  165. u32 ch_pri[2];
  166. u32 wm_en[2];
  167. u32 lock_en[2];
  168. u32 sub_addr[5];
  169. u32 bndm_en[2];
  170. u32 sc_cord[2];
  171. u32 reserved[44];
  172. u32 ch_busy[2];
  173. };
  174. struct ipu_com_async {
  175. u32 com_conf_async;
  176. u32 graph_wind_ctrl_async;
  177. u32 fg_pos_async;
  178. u32 cur_pos_async;
  179. u32 cur_map_async;
  180. u32 gamma_c_async[8];
  181. u32 gamma_s_async[4];
  182. u32 dp_csca_async[4];
  183. u32 dp_csc_async[2];
  184. };
  185. struct ipu_dp {
  186. u32 com_conf_sync;
  187. u32 graph_wind_ctrl_sync;
  188. u32 fg_pos_sync;
  189. u32 cur_pos_sync;
  190. u32 cur_map_sync;
  191. u32 gamma_c_sync[8];
  192. u32 gamma_s_sync[4];
  193. u32 csca_sync[4];
  194. u32 csc_sync[2];
  195. u32 cur_pos_alt;
  196. struct ipu_com_async async[2];
  197. };
  198. struct ipu_di {
  199. u32 general;
  200. u32 bs_clkgen0;
  201. u32 bs_clkgen1;
  202. u32 sw_gen0[9];
  203. u32 sw_gen1[9];
  204. u32 sync_as;
  205. u32 dw_gen[12];
  206. u32 dw_set[48];
  207. u32 stp_rep[4];
  208. u32 stp_rep9;
  209. u32 ser_conf;
  210. u32 ssc;
  211. u32 pol;
  212. u32 aw0;
  213. u32 aw1;
  214. u32 scr_conf;
  215. u32 stat;
  216. };
  217. struct ipu_stat {
  218. u32 int_stat[15];
  219. u32 cur_buf[2];
  220. u32 alt_cur_buf_0;
  221. u32 alt_cur_buf_1;
  222. u32 srm_stat;
  223. u32 proc_task_stat;
  224. u32 disp_task_stat;
  225. u32 triple_cur_buf[4];
  226. u32 ch_buf0_rdy[2];
  227. u32 ch_buf1_rdy[2];
  228. u32 alt_ch_buf0_rdy[2];
  229. u32 alt_ch_buf1_rdy[2];
  230. u32 ch_buf2_rdy[2];
  231. };
  232. struct ipu_dc_ch {
  233. u32 wr_ch_conf;
  234. u32 wr_ch_addr;
  235. u32 rl[5];
  236. };
  237. struct ipu_dc {
  238. struct ipu_dc_ch dc_ch0_1_2[3];
  239. u32 cmd_ch_conf_3;
  240. u32 cmd_ch_conf_4;
  241. struct ipu_dc_ch dc_ch5_6[2];
  242. struct ipu_dc_ch dc_ch8;
  243. u32 rl6_ch_8;
  244. struct ipu_dc_ch dc_ch9;
  245. u32 rl6_ch_9;
  246. u32 gen;
  247. u32 disp_conf1[4];
  248. u32 disp_conf2[4];
  249. u32 di0_conf[2];
  250. u32 di1_conf[2];
  251. u32 dc_map_ptr[15];
  252. u32 dc_map_val[12];
  253. u32 udge[16];
  254. u32 lla[2];
  255. u32 r_lla[2];
  256. u32 wr_ch_addr_5_alt;
  257. u32 stat;
  258. };
  259. struct ipu_dmfc {
  260. u32 rd_chan;
  261. u32 wr_chan;
  262. u32 wr_chan_def;
  263. u32 dp_chan;
  264. u32 dp_chan_def;
  265. u32 general[2];
  266. u32 ic_ctrl;
  267. u32 wr_chan_alt;
  268. u32 wr_chan_def_alt;
  269. u32 general1_alt;
  270. u32 stat;
  271. };
  272. #define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \
  273. IPU_CM_REG_BASE))
  274. #define IPU_CONF (&IPU_CM_REG->conf)
  275. #define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1)
  276. #define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2)
  277. #define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0])
  278. #define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1])
  279. #define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2])
  280. #define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])
  281. #define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)
  282. #define IPU_MEM_RST (&IPU_CM_REG->mem_rst)
  283. #define IPU_GPR (&IPU_CM_REG->gpr)
  284. #define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])
  285. #define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
  286. IPU_STAT_REG_BASE))
  287. #define IPU_INT_STAT(n) (&IPU_STAT->int_stat[(n) - 1])
  288. #define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32])
  289. #define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])
  290. #define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32])
  291. #define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32))
  292. #define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F))
  293. #define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])
  294. #define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \
  295. IPU_IDMAC_REG_BASE))
  296. #define IDMAC_CONF (&IDMAC_REG->conf)
  297. #define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32])
  298. #define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32])
  299. #define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
  300. ((di == 1) ? IPU_DI1_REG_BASE : \
  301. IPU_DI0_REG_BASE)))
  302. #define DI_GENERAL(di) (&DI_REG(di)->general)
  303. #define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0)
  304. #define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1)
  305. #define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])
  306. #define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])
  307. #define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])
  308. #define DI_STP_REP9(di) (&DI_REG(di)->stp_rep9)
  309. #define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
  310. #define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
  311. #define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
  312. #define DI_POL(di) (&DI_REG(di)->pol)
  313. #define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf)
  314. #define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \
  315. IPU_DMFC_REG_BASE))
  316. #define DMFC_WR_CHAN (&DMFC_REG->wr_chan)
  317. #define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def)
  318. #define DMFC_DP_CHAN (&DMFC_REG->dp_chan)
  319. #define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def)
  320. #define DMFC_GENERAL1 (&DMFC_REG->general[0])
  321. #define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl)
  322. #define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \
  323. IPU_DC_REG_BASE))
  324. #define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2])
  325. #define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2])
  326. static inline struct ipu_dc_ch *dc_ch_offset(int ch)
  327. {
  328. switch (ch) {
  329. case 0:
  330. case 1:
  331. case 2:
  332. return &DC_REG->dc_ch0_1_2[ch];
  333. case 5:
  334. case 6:
  335. return &DC_REG->dc_ch5_6[ch - 5];
  336. case 8:
  337. return &DC_REG->dc_ch8;
  338. case 9:
  339. return &DC_REG->dc_ch9;
  340. default:
  341. printf("%s: invalid channel %d\n", __func__, ch);
  342. return NULL;
  343. }
  344. }
  345. #define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2])
  346. #define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf)
  347. #define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr)
  348. #define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1)
  349. #define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5)
  350. #define DC_GEN (&DC_REG->gen)
  351. #define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp])
  352. #define DC_STAT (&DC_REG->stat)
  353. #define DP_SYNC 0
  354. #define DP_ASYNC0 0x60
  355. #define DP_ASYNC1 0xBC
  356. #define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
  357. IPU_DP_REG_BASE))
  358. #define DP_COM_CONF() (&DP_REG->com_conf_sync)
  359. #define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync)
  360. #define DP_CSC_A_0() (&DP_REG->csca_sync[0])
  361. #define DP_CSC_A_1() (&DP_REG->csca_sync[1])
  362. #define DP_CSC_A_2() (&DP_REG->csca_sync[2])
  363. #define DP_CSC_A_3() (&DP_REG->csca_sync[3])
  364. #define DP_CSC_0() (&DP_REG->csc_sync[0])
  365. #define DP_CSC_1() (&DP_REG->csc_sync[1])
  366. /* DC template opcodes */
  367. #define WROD(lf) (0x18 | (lf << 1))
  368. #endif