ipu.h 7.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Porting to u-boot:
  4. *
  5. * (C) Copyright 2010
  6. * Stefano Babic, DENX Software Engineering, sbabic@denx.de
  7. *
  8. * Linux IPU driver for MX51:
  9. *
  10. * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
  11. */
  12. #ifndef __ASM_ARCH_IPU_H__
  13. #define __ASM_ARCH_IPU_H__
  14. #include <linux/types.h>
  15. #include <ipu_pixfmt.h>
  16. #define IDMA_CHAN_INVALID 0xFF
  17. #define HIGH_RESOLUTION_WIDTH 1024
  18. struct clk {
  19. const char *name;
  20. int id;
  21. /* Source clock this clk depends on */
  22. struct clk *parent;
  23. /* Secondary clock to enable/disable with this clock */
  24. struct clk *secondary;
  25. /* Current clock rate */
  26. unsigned long rate;
  27. /* Reference count of clock enable/disable */
  28. __s8 usecount;
  29. /* Register bit position for clock's enable/disable control. */
  30. u8 enable_shift;
  31. /* Register address for clock's enable/disable control. */
  32. void *enable_reg;
  33. u32 flags;
  34. /*
  35. * Function ptr to recalculate the clock's rate based on parent
  36. * clock's rate
  37. */
  38. void (*recalc) (struct clk *);
  39. /*
  40. * Function ptr to set the clock to a new rate. The rate must match a
  41. * supported rate returned from round_rate. Leave blank if clock is not
  42. * programmable
  43. */
  44. int (*set_rate) (struct clk *, unsigned long);
  45. /*
  46. * Function ptr to round the requested clock rate to the nearest
  47. * supported rate that is less than or equal to the requested rate.
  48. */
  49. unsigned long (*round_rate) (struct clk *, unsigned long);
  50. /*
  51. * Function ptr to enable the clock. Leave blank if clock can not
  52. * be gated.
  53. */
  54. int (*enable) (struct clk *);
  55. /*
  56. * Function ptr to disable the clock. Leave blank if clock can not
  57. * be gated.
  58. */
  59. void (*disable) (struct clk *);
  60. /* Function ptr to set the parent clock of the clock. */
  61. int (*set_parent) (struct clk *, struct clk *);
  62. };
  63. /*
  64. * Enumeration of Synchronous (Memory-less) panel types
  65. */
  66. typedef enum {
  67. IPU_PANEL_SHARP_TFT,
  68. IPU_PANEL_TFT,
  69. } ipu_panel_t;
  70. /*
  71. * IPU Driver channels definitions.
  72. * Note these are different from IDMA channels
  73. */
  74. #define IPU_MAX_CH 32
  75. #define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
  76. ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
  77. #define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
  78. #define IPU_CHAN_ID(ch) (ch >> 24)
  79. #define IPU_CHAN_ALT(ch) (ch & 0x02000000)
  80. #define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
  81. #define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
  82. #define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
  83. #define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
  84. #define NO_DMA 0x3F
  85. #define ALT 1
  86. /*
  87. * Enumeration of IPU logical channels. An IPU logical channel is defined as a
  88. * combination of an input (memory to IPU), output (IPU to memory), and/or
  89. * secondary input IDMA channels and in some cases an Image Converter task.
  90. * Some channels consist of only an input or output.
  91. */
  92. typedef enum {
  93. CHAN_NONE = -1,
  94. MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
  95. MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
  96. MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
  97. MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
  98. MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
  99. MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
  100. MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
  101. MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
  102. DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
  103. DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
  104. } ipu_channel_t;
  105. /*
  106. * Enumeration of types of buffers for a logical channel.
  107. */
  108. typedef enum {
  109. IPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */
  110. IPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */
  111. IPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */
  112. IPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */
  113. IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
  114. IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
  115. } ipu_buffer_t;
  116. #define IPU_PANEL_SERIAL 1
  117. #define IPU_PANEL_PARALLEL 2
  118. struct ipu_channel {
  119. u8 video_in_dma;
  120. u8 alpha_in_dma;
  121. u8 graph_in_dma;
  122. u8 out_dma;
  123. };
  124. enum ipu_dmfc_type {
  125. DMFC_NORMAL = 0,
  126. DMFC_HIGH_RESOLUTION_DC,
  127. DMFC_HIGH_RESOLUTION_DP,
  128. DMFC_HIGH_RESOLUTION_ONLY_DP,
  129. };
  130. /*
  131. * Union of initialization parameters for a logical channel.
  132. */
  133. typedef union {
  134. struct {
  135. uint32_t di;
  136. unsigned char interlaced;
  137. } mem_dc_sync;
  138. struct {
  139. uint32_t temp;
  140. } mem_sdc_fg;
  141. struct {
  142. uint32_t di;
  143. unsigned char interlaced;
  144. uint32_t in_pixel_fmt;
  145. uint32_t out_pixel_fmt;
  146. unsigned char alpha_chan_en;
  147. } mem_dp_bg_sync;
  148. struct {
  149. uint32_t temp;
  150. } mem_sdc_bg;
  151. struct {
  152. uint32_t di;
  153. unsigned char interlaced;
  154. uint32_t in_pixel_fmt;
  155. uint32_t out_pixel_fmt;
  156. unsigned char alpha_chan_en;
  157. } mem_dp_fg_sync;
  158. } ipu_channel_params_t;
  159. /*
  160. * Enumeration of IPU interrupts.
  161. */
  162. enum ipu_irq_line {
  163. IPU_IRQ_DP_SF_END = 448 + 3,
  164. IPU_IRQ_DC_FC_1 = 448 + 9,
  165. };
  166. /*
  167. * Bitfield of Display Interface signal polarities.
  168. */
  169. typedef struct {
  170. unsigned datamask_en:1;
  171. unsigned ext_clk:1;
  172. unsigned interlaced:1;
  173. unsigned odd_field_first:1;
  174. unsigned clksel_en:1;
  175. unsigned clkidle_en:1;
  176. unsigned data_pol:1; /* true = inverted */
  177. unsigned clk_pol:1; /* true = rising edge */
  178. unsigned enable_pol:1;
  179. unsigned Hsync_pol:1; /* true = active high */
  180. unsigned Vsync_pol:1;
  181. } ipu_di_signal_cfg_t;
  182. typedef enum {
  183. RGB,
  184. YCbCr,
  185. YUV
  186. } ipu_color_space_t;
  187. /* Common IPU API */
  188. int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
  189. void ipu_uninit_channel(ipu_channel_t channel);
  190. int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
  191. uint32_t pixel_fmt,
  192. uint16_t width, uint16_t height,
  193. uint32_t stride,
  194. dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
  195. uint32_t u_offset, uint32_t v_offset);
  196. int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
  197. uint32_t bufNum, dma_addr_t phyaddr);
  198. int32_t ipu_is_channel_busy(ipu_channel_t channel);
  199. void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
  200. uint32_t bufNum);
  201. int32_t ipu_enable_channel(ipu_channel_t channel);
  202. int32_t ipu_disable_channel(ipu_channel_t channel);
  203. int32_t ipu_init_sync_panel(int disp,
  204. uint32_t pixel_clk,
  205. uint16_t width, uint16_t height,
  206. uint32_t pixel_fmt,
  207. uint16_t h_start_width, uint16_t h_sync_width,
  208. uint16_t h_end_width, uint16_t v_start_width,
  209. uint16_t v_sync_width, uint16_t v_end_width,
  210. uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
  211. int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
  212. uint8_t alpha);
  213. int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
  214. uint32_t colorKey);
  215. uint32_t bytes_per_pixel(uint32_t fmt);
  216. void clk_enable(struct clk *clk);
  217. void clk_disable(struct clk *clk);
  218. u32 clk_get_rate(struct clk *clk);
  219. int clk_set_rate(struct clk *clk, unsigned long rate);
  220. long clk_round_rate(struct clk *clk, unsigned long rate);
  221. int clk_set_parent(struct clk *clk, struct clk *parent);
  222. int clk_get_usecount(struct clk *clk);
  223. struct clk *clk_get_parent(struct clk *clk);
  224. void ipu_dump_registers(void);
  225. int ipu_probe(void);
  226. bool ipu_clk_enabled(void);
  227. void ipu_dmfc_init(int dmfc_type, int first);
  228. void ipu_init_dc_mappings(void);
  229. void ipu_dmfc_set_wait4eot(int dma_chan, int width);
  230. void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
  231. void ipu_dc_uninit(int dc_chan);
  232. void ipu_dp_dc_enable(ipu_channel_t channel);
  233. int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
  234. uint32_t out_pixel_fmt);
  235. void ipu_dp_uninit(ipu_channel_t channel);
  236. void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
  237. ipu_color_space_t format_to_colorspace(uint32_t fmt);
  238. #endif