fsl_dcu_fb.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2019 Toradex AG
  5. *
  6. * FSL DCU Framebuffer driver
  7. */
  8. #include <init.h>
  9. #include <asm/cache.h>
  10. #include <asm/io.h>
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <fdt_support.h>
  14. #include <fsl_dcu_fb.h>
  15. #include <linux/fb.h>
  16. #include <malloc.h>
  17. #include <video.h>
  18. #include <video_fb.h>
  19. #include "videomodes.h"
  20. /* Convert the X,Y resolution pair into a single number */
  21. #define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
  22. #ifdef CONFIG_SYS_FSL_DCU_LE
  23. #define dcu_read32 in_le32
  24. #define dcu_write32 out_le32
  25. #elif defined(CONFIG_SYS_FSL_DCU_BE)
  26. #define dcu_read32 in_be32
  27. #define dcu_write32 out_be32
  28. #endif
  29. #define DCU_MODE_BLEND_ITER(x) ((x) << 20)
  30. #define DCU_MODE_RASTER_EN (1 << 14)
  31. #define DCU_MODE_NORMAL 1
  32. #define DCU_MODE_COLORBAR 3
  33. #define DCU_BGND_R(x) ((x) << 16)
  34. #define DCU_BGND_G(x) ((x) << 8)
  35. #define DCU_BGND_B(x) (x)
  36. #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16)
  37. #define DCU_DISP_SIZE_DELTA_X(x) (x)
  38. #define DCU_HSYN_PARA_BP(x) ((x) << 22)
  39. #define DCU_HSYN_PARA_PW(x) ((x) << 11)
  40. #define DCU_HSYN_PARA_FP(x) (x)
  41. #define DCU_VSYN_PARA_BP(x) ((x) << 22)
  42. #define DCU_VSYN_PARA_PW(x) ((x) << 11)
  43. #define DCU_VSYN_PARA_FP(x) (x)
  44. #define DCU_SYN_POL_INV_PXCK_FALL (1 << 6)
  45. #define DCU_SYN_POL_NEG_REMAIN (0 << 5)
  46. #define DCU_SYN_POL_INV_VS_LOW (1 << 1)
  47. #define DCU_SYN_POL_INV_HS_LOW (1)
  48. #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16)
  49. #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8)
  50. #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x)
  51. #define DCU_UPDATE_MODE_MODE (1 << 31)
  52. #define DCU_UPDATE_MODE_READREG (1 << 30)
  53. #define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16)
  54. #define DCU_CTRLDESCLN_1_WIDTH(x) (x)
  55. #define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16)
  56. #define DCU_CTRLDESCLN_2_POSX(x) (x)
  57. #define DCU_CTRLDESCLN_4_EN (1 << 31)
  58. #define DCU_CTRLDESCLN_4_TILE_EN (1 << 30)
  59. #define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29)
  60. #define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28)
  61. #define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20)
  62. #define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16)
  63. #define DCU_CTRLDESCLN_4_RLE_EN (1 << 15)
  64. #define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4)
  65. #define DCU_CTRLDESCLN_4_BB_ON (1 << 2)
  66. #define DCU_CTRLDESCLN_4_AB(x) (x)
  67. #define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16)
  68. #define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8)
  69. #define DCU_CTRLDESCLN_5_CKMAX_B(x) (x)
  70. #define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16)
  71. #define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8)
  72. #define DCU_CTRLDESCLN_6_CKMIN_B(x) (x)
  73. #define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16)
  74. #define DCU_CTRLDESCLN_7_TILE_HOR(x) (x)
  75. #define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x)
  76. #define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x)
  77. #define BPP_16_RGB565 4
  78. #define BPP_24_RGB888 5
  79. #define BPP_32_ARGB8888 6
  80. DECLARE_GLOBAL_DATA_PTR;
  81. /*
  82. * This setting is used for the TWR_LCD_RGB card
  83. */
  84. static struct fb_videomode fsl_dcu_mode_480_272 = {
  85. .name = "480x272-60",
  86. .refresh = 60,
  87. .xres = 480,
  88. .yres = 272,
  89. .pixclock = 91996,
  90. .left_margin = 2,
  91. .right_margin = 2,
  92. .upper_margin = 1,
  93. .lower_margin = 1,
  94. .hsync_len = 41,
  95. .vsync_len = 2,
  96. .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  97. .vmode = FB_VMODE_NONINTERLACED
  98. };
  99. /*
  100. * This setting is used for Siliconimage SiI9022A HDMI
  101. */
  102. static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
  103. .name = "640x480-60",
  104. .refresh = 60,
  105. .xres = 640,
  106. .yres = 480,
  107. .pixclock = 39722,
  108. .left_margin = 48,
  109. .right_margin = 16,
  110. .upper_margin = 33,
  111. .lower_margin = 10,
  112. .hsync_len = 96,
  113. .vsync_len = 2,
  114. .sync = 0,
  115. .vmode = FB_VMODE_NONINTERLACED,
  116. };
  117. static struct fb_videomode fsl_dcu_mode_640_480 = {
  118. .name = "640x480-60",
  119. .refresh = 60,
  120. .xres = 640,
  121. .yres = 480,
  122. .pixclock = 25175,
  123. .left_margin = 40,
  124. .right_margin = 24,
  125. .upper_margin = 32,
  126. .lower_margin = 11,
  127. .hsync_len = 96,
  128. .vsync_len = 2,
  129. .sync = 0,
  130. .vmode = FB_VMODE_NONINTERLACED,
  131. };
  132. static struct fb_videomode fsl_dcu_mode_800_480 = {
  133. .name = "800x480-60",
  134. .refresh = 60,
  135. .xres = 800,
  136. .yres = 480,
  137. .pixclock = 33260,
  138. .left_margin = 216,
  139. .right_margin = 40,
  140. .upper_margin = 35,
  141. .lower_margin = 10,
  142. .hsync_len = 128,
  143. .vsync_len = 2,
  144. .sync = 0,
  145. .vmode = FB_VMODE_NONINTERLACED,
  146. };
  147. static struct fb_videomode fsl_dcu_mode_1024_600 = {
  148. .name = "1024x600-60",
  149. .refresh = 60,
  150. .xres = 1024,
  151. .yres = 600,
  152. .pixclock = 48000,
  153. .left_margin = 104,
  154. .right_margin = 43,
  155. .upper_margin = 24,
  156. .lower_margin = 20,
  157. .hsync_len = 5,
  158. .vsync_len = 5,
  159. .sync = 0,
  160. .vmode = FB_VMODE_NONINTERLACED,
  161. };
  162. /*
  163. * DCU register map
  164. */
  165. struct dcu_reg {
  166. u32 desc_cursor[4];
  167. u32 mode;
  168. u32 bgnd;
  169. u32 disp_size;
  170. u32 hsyn_para;
  171. u32 vsyn_para;
  172. u32 synpol;
  173. u32 threshold;
  174. u32 int_status;
  175. u32 int_mask;
  176. u32 colbar[8];
  177. u32 div_ratio;
  178. u32 sign_calc[2];
  179. u32 crc_val;
  180. u8 res_064[0x6c-0x64];
  181. u32 parr_err_status1;
  182. u8 res_070[0x7c-0x70];
  183. u32 parr_err_status3;
  184. u32 mparr_err_status1;
  185. u8 res_084[0x90-0x84];
  186. u32 mparr_err_status3;
  187. u32 threshold_inp_buf[2];
  188. u8 res_09c[0xa0-0x9c];
  189. u32 luma_comp;
  190. u32 chroma_red;
  191. u32 chroma_green;
  192. u32 chroma_blue;
  193. u32 crc_pos;
  194. u32 lyr_intpol_en;
  195. u32 lyr_luma_comp;
  196. u32 lyr_chrm_red;
  197. u32 lyr_chrm_grn;
  198. u32 lyr_chrm_blue;
  199. u8 res_0c4[0xcc-0xc8];
  200. u32 update_mode;
  201. u32 underrun;
  202. u8 res_0d4[0x100-0xd4];
  203. u32 gpr;
  204. u32 slr_l[2];
  205. u32 slr_disp_size;
  206. u32 slr_hvsync_para;
  207. u32 slr_pol;
  208. u32 slr_l_transp[2];
  209. u8 res_120[0x200-0x120];
  210. u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
  211. };
  212. static void reset_total_layers(void)
  213. {
  214. struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
  215. int i;
  216. for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
  217. dcu_write32(&regs->ctrldescl[i][0], 0);
  218. dcu_write32(&regs->ctrldescl[i][1], 0);
  219. dcu_write32(&regs->ctrldescl[i][2], 0);
  220. dcu_write32(&regs->ctrldescl[i][3], 0);
  221. dcu_write32(&regs->ctrldescl[i][4], 0);
  222. dcu_write32(&regs->ctrldescl[i][5], 0);
  223. dcu_write32(&regs->ctrldescl[i][6], 0);
  224. dcu_write32(&regs->ctrldescl[i][7], 0);
  225. dcu_write32(&regs->ctrldescl[i][8], 0);
  226. dcu_write32(&regs->ctrldescl[i][9], 0);
  227. dcu_write32(&regs->ctrldescl[i][10], 0);
  228. }
  229. }
  230. static int layer_ctrldesc_init(struct fb_info fbinfo,
  231. int index, u32 pixel_format)
  232. {
  233. struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
  234. unsigned int bpp = BPP_24_RGB888;
  235. dcu_write32(&regs->ctrldescl[index][0],
  236. DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) |
  237. DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres));
  238. dcu_write32(&regs->ctrldescl[index][1],
  239. DCU_CTRLDESCLN_2_POSY(0) |
  240. DCU_CTRLDESCLN_2_POSX(0));
  241. dcu_write32(&regs->ctrldescl[index][2],
  242. (unsigned int)fbinfo.screen_base);
  243. switch (pixel_format) {
  244. case 16:
  245. bpp = BPP_16_RGB565;
  246. break;
  247. case 24:
  248. bpp = BPP_24_RGB888;
  249. break;
  250. case 32:
  251. bpp = BPP_32_ARGB8888;
  252. break;
  253. default:
  254. printf("unsupported color depth: %u\n", pixel_format);
  255. }
  256. dcu_write32(&regs->ctrldescl[index][3],
  257. DCU_CTRLDESCLN_4_EN |
  258. DCU_CTRLDESCLN_4_TRANS(0xff) |
  259. DCU_CTRLDESCLN_4_BPP(bpp) |
  260. DCU_CTRLDESCLN_4_AB(0));
  261. dcu_write32(&regs->ctrldescl[index][4],
  262. DCU_CTRLDESCLN_5_CKMAX_R(0xff) |
  263. DCU_CTRLDESCLN_5_CKMAX_G(0xff) |
  264. DCU_CTRLDESCLN_5_CKMAX_B(0xff));
  265. dcu_write32(&regs->ctrldescl[index][5],
  266. DCU_CTRLDESCLN_6_CKMIN_R(0) |
  267. DCU_CTRLDESCLN_6_CKMIN_G(0) |
  268. DCU_CTRLDESCLN_6_CKMIN_B(0));
  269. dcu_write32(&regs->ctrldescl[index][6],
  270. DCU_CTRLDESCLN_7_TILE_VER(0) |
  271. DCU_CTRLDESCLN_7_TILE_HOR(0));
  272. dcu_write32(&regs->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
  273. dcu_write32(&regs->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
  274. return 0;
  275. }
  276. int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres,
  277. unsigned int yres, unsigned int pixel_format)
  278. {
  279. struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
  280. unsigned int div, mode;
  281. /*
  282. * When DM_VIDEO is enabled reservation of framebuffer is done
  283. * in advance during bind() call.
  284. */
  285. #if !CONFIG_IS_ENABLED(DM_VIDEO)
  286. fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres *
  287. (fbinfo->var.bits_per_pixel / 8);
  288. if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
  289. fbinfo->screen_size = 0;
  290. return -ENOMEM;
  291. }
  292. /* Reserve framebuffer at the end of memory */
  293. gd->fb_base = gd->bd->bi_dram[0].start +
  294. gd->bd->bi_dram[0].size - fbinfo->screen_size;
  295. fbinfo->screen_base = (char *)gd->fb_base;
  296. memset(fbinfo->screen_base, 0, fbinfo->screen_size);
  297. #endif
  298. reset_total_layers();
  299. dcu_write32(&regs->disp_size,
  300. DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) |
  301. DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16));
  302. dcu_write32(&regs->hsyn_para,
  303. DCU_HSYN_PARA_BP(fbinfo->var.left_margin) |
  304. DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) |
  305. DCU_HSYN_PARA_FP(fbinfo->var.right_margin));
  306. dcu_write32(&regs->vsyn_para,
  307. DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) |
  308. DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) |
  309. DCU_VSYN_PARA_FP(fbinfo->var.lower_margin));
  310. dcu_write32(&regs->synpol,
  311. DCU_SYN_POL_INV_PXCK_FALL |
  312. DCU_SYN_POL_NEG_REMAIN |
  313. DCU_SYN_POL_INV_VS_LOW |
  314. DCU_SYN_POL_INV_HS_LOW);
  315. dcu_write32(&regs->bgnd,
  316. DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
  317. dcu_write32(&regs->mode,
  318. DCU_MODE_BLEND_ITER(2) |
  319. DCU_MODE_RASTER_EN);
  320. dcu_write32(&regs->threshold,
  321. DCU_THRESHOLD_LS_BF_VS(0x3) |
  322. DCU_THRESHOLD_OUT_BUF_HIGH(0x78) |
  323. DCU_THRESHOLD_OUT_BUF_LOW(0));
  324. mode = dcu_read32(&regs->mode);
  325. dcu_write32(&regs->mode, mode | DCU_MODE_NORMAL);
  326. layer_ctrldesc_init(*fbinfo, 0, pixel_format);
  327. div = dcu_set_pixel_clock(fbinfo->var.pixclock);
  328. dcu_write32(&regs->div_ratio, (div - 1));
  329. dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
  330. return 0;
  331. }
  332. ulong board_get_usable_ram_top(ulong total_size)
  333. {
  334. return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
  335. }
  336. int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x,
  337. unsigned int *win_y)
  338. {
  339. const char *options;
  340. unsigned int depth = 0, freq = 0;
  341. struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
  342. if (!video_get_video_mode(win_x, win_y, &depth, &freq,
  343. &options))
  344. return -EINVAL;
  345. /* Find the monitor port, which is a required option */
  346. if (!options)
  347. return -EINVAL;
  348. if (strncmp(options, "monitor=", 8) != 0)
  349. return -EINVAL;
  350. switch (RESOLUTION(*win_x, *win_y)) {
  351. case RESOLUTION(480, 272):
  352. fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
  353. break;
  354. case RESOLUTION(640, 480):
  355. if (!strncmp(options, "monitor=hdmi", 12))
  356. fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
  357. else
  358. fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
  359. break;
  360. case RESOLUTION(800, 480):
  361. fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
  362. break;
  363. case RESOLUTION(1024, 600):
  364. fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
  365. break;
  366. default:
  367. printf("unsupported resolution %ux%u\n",
  368. *win_x, *win_y);
  369. }
  370. fbinfo->var.xres = fsl_dcu_mode_db->xres;
  371. fbinfo->var.yres = fsl_dcu_mode_db->yres;
  372. fbinfo->var.bits_per_pixel = 32;
  373. fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock;
  374. fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin;
  375. fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin;
  376. fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin;
  377. fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin;
  378. fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len;
  379. fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len;
  380. fbinfo->var.sync = fsl_dcu_mode_db->sync;
  381. fbinfo->var.vmode = fsl_dcu_mode_db->vmode;
  382. fbinfo->fix.line_length = fbinfo->var.xres *
  383. fbinfo->var.bits_per_pixel / 8;
  384. return platform_dcu_init(fbinfo, *win_x, *win_y,
  385. options + 8, fsl_dcu_mode_db);
  386. }
  387. #ifndef CONFIG_DM_VIDEO
  388. static struct fb_info info;
  389. #if defined(CONFIG_OF_BOARD_SETUP)
  390. int fsl_dcu_fixedfb_setup(void *blob)
  391. {
  392. u64 start, size;
  393. int ret;
  394. start = gd->bd->bi_dram[0].start;
  395. size = gd->bd->bi_dram[0].size - info.screen_size;
  396. /*
  397. * Align size on section size (1 MiB).
  398. */
  399. size &= 0xfff00000;
  400. ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
  401. if (ret) {
  402. eprintf("Cannot setup fb: Error reserving memory\n");
  403. return ret;
  404. }
  405. return 0;
  406. }
  407. #endif
  408. void *video_hw_init(void)
  409. {
  410. static GraphicDevice ctfb;
  411. if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0)
  412. return NULL;
  413. ctfb.frameAdrs = (unsigned int)info.screen_base;
  414. ctfb.plnSizeX = ctfb.winSizeX;
  415. ctfb.plnSizeY = ctfb.winSizeY;
  416. ctfb.gdfBytesPP = 4;
  417. ctfb.gdfIndex = GDF_32BIT_X888RGB;
  418. ctfb.memSize = info.screen_size;
  419. return &ctfb;
  420. }
  421. #else /* ifndef CONFIG_DM_VIDEO */
  422. static int fsl_dcu_video_probe(struct udevice *dev)
  423. {
  424. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  425. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  426. struct fb_info fbinfo = { 0 };
  427. unsigned int win_x;
  428. unsigned int win_y;
  429. u32 fb_start, fb_end;
  430. int ret = 0;
  431. fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
  432. fb_end = plat->base + plat->size;
  433. fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
  434. fbinfo.screen_base = (char *)fb_start;
  435. fbinfo.screen_size = plat->size;
  436. ret = fsl_probe_common(&fbinfo, &win_x, &win_y);
  437. if (ret < 0)
  438. return ret;
  439. uc_priv->bpix = VIDEO_BPP32;
  440. uc_priv->xsize = win_x;
  441. uc_priv->ysize = win_y;
  442. /* Enable dcache for the frame buffer */
  443. mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
  444. DCACHE_WRITEBACK);
  445. video_set_flush_dcache(dev, true);
  446. return ret;
  447. }
  448. static int fsl_dcu_video_bind(struct udevice *dev)
  449. {
  450. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  451. unsigned int win_x;
  452. unsigned int win_y;
  453. unsigned int depth = 0, freq = 0;
  454. const char *options;
  455. int ret = 0;
  456. ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options);
  457. if (ret < 0)
  458. return ret;
  459. plat->size = win_x * win_y * 32;
  460. return 0;
  461. }
  462. static const struct udevice_id fsl_dcu_video_ids[] = {
  463. { .compatible = "fsl,vf610-dcu" },
  464. { /* sentinel */ }
  465. };
  466. U_BOOT_DRIVER(fsl_dcu_video) = {
  467. .name = "fsl_dcu_video",
  468. .id = UCLASS_VIDEO,
  469. .of_match = fsl_dcu_video_ids,
  470. .bind = fsl_dcu_video_bind,
  471. .probe = fsl_dcu_video_probe,
  472. .flags = DM_FLAG_PRE_RELOC,
  473. };
  474. #endif /* ifndef CONFIG_DM_VIDEO */