exynos_mipi_dsi_lowlevel.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. *
  5. * Author: InKi Dae <inki.dae@samsung.com>
  6. * Author: Donghwa Lee <dh09.lee@samsung.com>
  7. */
  8. #include <common.h>
  9. #include <asm/arch/dsim.h>
  10. #include <asm/arch/mipi_dsim.h>
  11. #include <asm/arch/power.h>
  12. #include <asm/arch/cpu.h>
  13. #include <linux/delay.h>
  14. #include "exynos_mipi_dsi_lowlevel.h"
  15. #include "exynos_mipi_dsi_common.h"
  16. void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim)
  17. {
  18. unsigned int reg;
  19. struct exynos_mipi_dsim *mipi_dsim =
  20. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  21. reg = readl(&mipi_dsim->swrst);
  22. reg |= DSIM_FUNCRST;
  23. writel(reg, &mipi_dsim->swrst);
  24. }
  25. void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim)
  26. {
  27. unsigned int reg = 0;
  28. struct exynos_mipi_dsim *mipi_dsim =
  29. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  30. reg = readl(&mipi_dsim->swrst);
  31. reg |= DSIM_SWRST;
  32. reg |= DSIM_FUNCRST;
  33. writel(reg, &mipi_dsim->swrst);
  34. }
  35. void exynos_mipi_dsi_sw_release(struct mipi_dsim_device *dsim)
  36. {
  37. struct exynos_mipi_dsim *mipi_dsim =
  38. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  39. unsigned int reg = readl(&mipi_dsim->intsrc);
  40. reg |= INTSRC_SWRST_RELEASE;
  41. writel(reg, &mipi_dsim->intsrc);
  42. }
  43. void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
  44. unsigned int mode, unsigned int mask)
  45. {
  46. struct exynos_mipi_dsim *mipi_dsim =
  47. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  48. unsigned int reg = readl(&mipi_dsim->intmsk);
  49. if (mask)
  50. reg |= mode;
  51. else
  52. reg &= ~mode;
  53. writel(reg, &mipi_dsim->intmsk);
  54. }
  55. void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
  56. unsigned int cfg)
  57. {
  58. unsigned int reg;
  59. struct exynos_mipi_dsim *mipi_dsim =
  60. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  61. reg = readl(&mipi_dsim->fifoctrl);
  62. writel(reg & ~(cfg), &mipi_dsim->fifoctrl);
  63. udelay(10 * 1000);
  64. reg |= cfg;
  65. writel(reg, &mipi_dsim->fifoctrl);
  66. }
  67. /*
  68. * this function set PLL P, M and S value in D-PHY
  69. */
  70. void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
  71. unsigned int value)
  72. {
  73. struct exynos_mipi_dsim *mipi_dsim =
  74. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  75. writel(DSIM_AFC_CTL(value), &mipi_dsim->phyacchr);
  76. }
  77. void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
  78. unsigned int width_resol, unsigned int height_resol)
  79. {
  80. unsigned int reg;
  81. struct exynos_mipi_dsim *mipi_dsim =
  82. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  83. /* standby should be set after configuration so set to not ready*/
  84. reg = (readl(&mipi_dsim->mdresol)) & ~(DSIM_MAIN_STAND_BY);
  85. writel(reg, &mipi_dsim->mdresol);
  86. /* reset resolution */
  87. reg &= ~(DSIM_MAIN_VRESOL(0x7ff) | DSIM_MAIN_HRESOL(0x7ff));
  88. reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);
  89. reg |= DSIM_MAIN_STAND_BY;
  90. writel(reg, &mipi_dsim->mdresol);
  91. }
  92. void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
  93. unsigned int cmd_allow, unsigned int vfront, unsigned int vback)
  94. {
  95. unsigned int reg;
  96. struct exynos_mipi_dsim *mipi_dsim =
  97. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  98. reg = (readl(&mipi_dsim->mvporch)) &
  99. ~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) |
  100. (DSIM_MAIN_VBP_MASK));
  101. reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) |
  102. ((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) |
  103. ((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT);
  104. writel(reg, &mipi_dsim->mvporch);
  105. }
  106. void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
  107. unsigned int front, unsigned int back)
  108. {
  109. unsigned int reg;
  110. struct exynos_mipi_dsim *mipi_dsim =
  111. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  112. reg = (readl(&mipi_dsim->mhporch)) &
  113. ~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK));
  114. reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT);
  115. writel(reg, &mipi_dsim->mhporch);
  116. }
  117. void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
  118. unsigned int vert, unsigned int hori)
  119. {
  120. unsigned int reg;
  121. struct exynos_mipi_dsim *mipi_dsim =
  122. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  123. reg = (readl(&mipi_dsim->msync)) &
  124. ~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK));
  125. reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) |
  126. (hori << DSIM_MAIN_HSA_SHIFT);
  127. writel(reg, &mipi_dsim->msync);
  128. }
  129. void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
  130. unsigned int vert, unsigned int hori)
  131. {
  132. unsigned int reg;
  133. struct exynos_mipi_dsim *mipi_dsim =
  134. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  135. reg = (readl(&mipi_dsim->sdresol)) &
  136. ~(DSIM_SUB_STANDY_MASK);
  137. writel(reg, &mipi_dsim->sdresol);
  138. reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);
  139. reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) |
  140. ((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT);
  141. writel(reg, &mipi_dsim->sdresol);
  142. /* DSIM STANDBY */
  143. reg |= (1 << DSIM_SUB_STANDY_SHIFT);
  144. writel(reg, &mipi_dsim->sdresol);
  145. }
  146. void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim)
  147. {
  148. struct mipi_dsim_config *dsim_config = dsim->dsim_config;
  149. struct exynos_mipi_dsim *mipi_dsim =
  150. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  151. unsigned int cfg = (readl(&mipi_dsim->config)) &
  152. ~((1 << DSIM_EOT_PACKET_SHIFT) |
  153. (0x1f << DSIM_HSA_MODE_SHIFT) |
  154. (0x3 << DSIM_NUM_OF_DATALANE_SHIFT));
  155. cfg |= (dsim_config->auto_flush << DSIM_AUTO_FLUSH_SHIFT) |
  156. (dsim_config->eot_disable << DSIM_EOT_PACKET_SHIFT) |
  157. (dsim_config->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) |
  158. (dsim_config->hse << DSIM_HSE_MODE_SHIFT) |
  159. (dsim_config->hfp << DSIM_HFP_MODE_SHIFT) |
  160. (dsim_config->hbp << DSIM_HBP_MODE_SHIFT) |
  161. (dsim_config->hsa << DSIM_HSA_MODE_SHIFT) |
  162. (dsim_config->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT);
  163. writel(cfg, &mipi_dsim->config);
  164. }
  165. void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
  166. struct mipi_dsim_config *dsim_config)
  167. {
  168. struct exynos_mipi_dsim *mipi_dsim =
  169. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  170. u32 reg = (readl(&mipi_dsim->config)) &
  171. ~((0x3 << DSIM_BURST_MODE_SHIFT) | (1 << DSIM_VIDEO_MODE_SHIFT)
  172. | (0x3 << DSIM_MAINVC_SHIFT) | (0x7 << DSIM_MAINPIX_SHIFT)
  173. | (0x3 << DSIM_SUBVC_SHIFT) | (0x7 << DSIM_SUBPIX_SHIFT));
  174. if (dsim_config->e_interface == DSIM_VIDEO)
  175. reg |= (1 << DSIM_VIDEO_MODE_SHIFT);
  176. else if (dsim_config->e_interface == DSIM_COMMAND)
  177. reg &= ~(1 << DSIM_VIDEO_MODE_SHIFT);
  178. else {
  179. printf("unknown lcd type.\n");
  180. return;
  181. }
  182. /* main lcd */
  183. reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << DSIM_BURST_MODE_SHIFT
  184. | ((u8) (dsim_config->e_virtual_ch) & 0x3) << DSIM_MAINVC_SHIFT
  185. | ((u8) (dsim_config->e_pixel_format) & 0x7) << DSIM_MAINPIX_SHIFT;
  186. writel(reg, &mipi_dsim->config);
  187. }
  188. void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim,
  189. unsigned int lane, unsigned int enable)
  190. {
  191. unsigned int reg;
  192. struct exynos_mipi_dsim *mipi_dsim =
  193. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  194. reg = readl(&mipi_dsim->config);
  195. if (enable)
  196. reg |= DSIM_LANE_ENx(lane);
  197. else
  198. reg &= ~DSIM_LANE_ENx(lane);
  199. writel(reg, &mipi_dsim->config);
  200. }
  201. void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
  202. unsigned int count)
  203. {
  204. unsigned int cfg;
  205. struct exynos_mipi_dsim *mipi_dsim =
  206. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  207. /* get the data lane number. */
  208. cfg = DSIM_NUM_OF_DATA_LANE(count);
  209. writel(cfg, &mipi_dsim->config);
  210. }
  211. void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim,
  212. unsigned int enable, unsigned int afc_code)
  213. {
  214. struct exynos_mipi_dsim *mipi_dsim =
  215. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  216. unsigned int reg = readl(&mipi_dsim->phyacchr);
  217. reg = 0;
  218. if (enable) {
  219. reg |= DSIM_AFC_EN;
  220. reg &= ~(0x7 << DSIM_AFC_CTL_SHIFT);
  221. reg |= DSIM_AFC_CTL(afc_code);
  222. } else
  223. reg &= ~DSIM_AFC_EN;
  224. writel(reg, &mipi_dsim->phyacchr);
  225. }
  226. void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
  227. unsigned int enable)
  228. {
  229. struct exynos_mipi_dsim *mipi_dsim =
  230. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  231. unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
  232. ~(DSIM_PLL_BYPASS_EXTERNAL);
  233. reg |= enable << DSIM_PLL_BYPASS_SHIFT;
  234. writel(reg, &mipi_dsim->clkctrl);
  235. }
  236. void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
  237. unsigned int freq_band)
  238. {
  239. struct exynos_mipi_dsim *mipi_dsim =
  240. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  241. unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
  242. ~(0x1f << DSIM_FREQ_BAND_SHIFT);
  243. reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT);
  244. writel(reg, &mipi_dsim->pllctrl);
  245. }
  246. void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
  247. unsigned int pre_divider, unsigned int main_divider,
  248. unsigned int scaler)
  249. {
  250. struct exynos_mipi_dsim *mipi_dsim =
  251. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  252. unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
  253. ~(0x7ffff << 1);
  254. reg |= ((pre_divider & 0x3f) << DSIM_PREDIV_SHIFT) |
  255. ((main_divider & 0x1ff) << DSIM_MAIN_SHIFT) |
  256. ((scaler & 0x7) << DSIM_SCALER_SHIFT);
  257. writel(reg, &mipi_dsim->pllctrl);
  258. }
  259. void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
  260. unsigned int lock_time)
  261. {
  262. struct exynos_mipi_dsim *mipi_dsim =
  263. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  264. writel(lock_time, &mipi_dsim->plltmr);
  265. }
  266. void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim,
  267. unsigned int enable)
  268. {
  269. struct exynos_mipi_dsim *mipi_dsim =
  270. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  271. unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
  272. ~(0x1 << DSIM_PLL_EN_SHIFT);
  273. reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT);
  274. writel(reg, &mipi_dsim->pllctrl);
  275. }
  276. void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
  277. unsigned int src)
  278. {
  279. struct exynos_mipi_dsim *mipi_dsim =
  280. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  281. unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
  282. ~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT);
  283. reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT;
  284. writel(reg, &mipi_dsim->clkctrl);
  285. }
  286. void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
  287. unsigned int enable)
  288. {
  289. struct exynos_mipi_dsim *mipi_dsim =
  290. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  291. unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
  292. ~(1 << DSIM_BYTE_CLKEN_SHIFT);
  293. reg |= enable << DSIM_BYTE_CLKEN_SHIFT;
  294. writel(reg, &mipi_dsim->clkctrl);
  295. }
  296. void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
  297. unsigned int enable, unsigned int prs_val)
  298. {
  299. struct exynos_mipi_dsim *mipi_dsim =
  300. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  301. unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
  302. ~((1 << DSIM_ESC_CLKEN_SHIFT) | (0xffff));
  303. reg |= enable << DSIM_ESC_CLKEN_SHIFT;
  304. if (enable)
  305. reg |= prs_val;
  306. writel(reg, &mipi_dsim->clkctrl);
  307. }
  308. void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
  309. unsigned int lane_sel, unsigned int enable)
  310. {
  311. struct exynos_mipi_dsim *mipi_dsim =
  312. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  313. unsigned int reg = readl(&mipi_dsim->clkctrl);
  314. if (enable)
  315. reg |= DSIM_LANE_ESC_CLKEN(lane_sel);
  316. else
  317. reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);
  318. writel(reg, &mipi_dsim->clkctrl);
  319. }
  320. void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
  321. unsigned int enable)
  322. {
  323. struct exynos_mipi_dsim *mipi_dsim =
  324. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  325. unsigned int reg = (readl(&mipi_dsim->escmode)) &
  326. ~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT);
  327. reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT);
  328. writel(reg, &mipi_dsim->escmode);
  329. }
  330. unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim)
  331. {
  332. struct exynos_mipi_dsim *mipi_dsim =
  333. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  334. unsigned int reg = readl(&mipi_dsim->status);
  335. /**
  336. * check clock and data lane states.
  337. * if MIPI-DSI controller was enabled at bootloader then
  338. * TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK.
  339. * so it should be checked for two case.
  340. */
  341. if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&
  342. ((reg & DSIM_STOP_STATE_CLK) ||
  343. (reg & DSIM_TX_READY_HS_CLK)))
  344. return 1;
  345. else
  346. return 0;
  347. }
  348. void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
  349. unsigned int cnt_val)
  350. {
  351. struct exynos_mipi_dsim *mipi_dsim =
  352. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  353. unsigned int reg = (readl(&mipi_dsim->escmode)) &
  354. ~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT);
  355. reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT);
  356. writel(reg, &mipi_dsim->escmode);
  357. }
  358. void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
  359. unsigned int timeout)
  360. {
  361. struct exynos_mipi_dsim *mipi_dsim =
  362. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  363. unsigned int reg = (readl(&mipi_dsim->timeout)) &
  364. ~(0xff << DSIM_BTA_TOUT_SHIFT);
  365. reg |= (timeout << DSIM_BTA_TOUT_SHIFT);
  366. writel(reg, &mipi_dsim->timeout);
  367. }
  368. void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
  369. unsigned int timeout)
  370. {
  371. struct exynos_mipi_dsim *mipi_dsim =
  372. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  373. unsigned int reg = (readl(&mipi_dsim->timeout)) &
  374. ~(0xffff << DSIM_LPDR_TOUT_SHIFT);
  375. reg |= (timeout << DSIM_LPDR_TOUT_SHIFT);
  376. writel(reg, &mipi_dsim->timeout);
  377. }
  378. void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
  379. unsigned int lp)
  380. {
  381. struct exynos_mipi_dsim *mipi_dsim =
  382. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  383. unsigned int reg = readl(&mipi_dsim->escmode);
  384. reg &= ~DSIM_CMD_LPDT_LP;
  385. if (lp)
  386. reg |= DSIM_CMD_LPDT_LP;
  387. writel(reg, &mipi_dsim->escmode);
  388. }
  389. void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
  390. unsigned int lp)
  391. {
  392. struct exynos_mipi_dsim *mipi_dsim =
  393. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  394. unsigned int reg = readl(&mipi_dsim->escmode);
  395. reg &= ~DSIM_TX_LPDT_LP;
  396. if (lp)
  397. reg |= DSIM_TX_LPDT_LP;
  398. writel(reg, &mipi_dsim->escmode);
  399. }
  400. void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
  401. unsigned int enable)
  402. {
  403. struct exynos_mipi_dsim *mipi_dsim =
  404. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  405. unsigned int reg = (readl(&mipi_dsim->clkctrl)) &
  406. ~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT);
  407. reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT;
  408. writel(reg, &mipi_dsim->clkctrl);
  409. }
  410. void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
  411. unsigned int swap_en)
  412. {
  413. struct exynos_mipi_dsim *mipi_dsim =
  414. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  415. unsigned int reg = readl(&mipi_dsim->phyacchr1);
  416. reg &= ~(0x3 << DSIM_DPDN_SWAP_DATA_SHIFT);
  417. reg |= (swap_en & 0x3) << DSIM_DPDN_SWAP_DATA_SHIFT;
  418. writel(reg, &mipi_dsim->phyacchr1);
  419. }
  420. void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
  421. unsigned int hs_zero)
  422. {
  423. struct exynos_mipi_dsim *mipi_dsim =
  424. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  425. unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
  426. ~(0xf << DSIM_ZEROCTRL_SHIFT);
  427. reg |= ((hs_zero & 0xf) << DSIM_ZEROCTRL_SHIFT);
  428. writel(reg, &mipi_dsim->pllctrl);
  429. }
  430. void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep)
  431. {
  432. struct exynos_mipi_dsim *mipi_dsim =
  433. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  434. unsigned int reg = (readl(&mipi_dsim->pllctrl)) &
  435. ~(0x7 << DSIM_PRECTRL_SHIFT);
  436. reg |= ((prep & 0x7) << DSIM_PRECTRL_SHIFT);
  437. writel(reg, &mipi_dsim->pllctrl);
  438. }
  439. void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim)
  440. {
  441. struct exynos_mipi_dsim *mipi_dsim =
  442. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  443. unsigned int reg = readl(&mipi_dsim->intsrc);
  444. reg |= INTSRC_PLL_STABLE;
  445. writel(reg, &mipi_dsim->intsrc);
  446. }
  447. void exynos_mipi_dsi_clear_all_interrupt(struct mipi_dsim_device *dsim)
  448. {
  449. struct exynos_mipi_dsim *mipi_dsim =
  450. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  451. writel(0xffffffff, &mipi_dsim->intsrc);
  452. }
  453. unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim)
  454. {
  455. unsigned int reg;
  456. struct exynos_mipi_dsim *mipi_dsim =
  457. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  458. reg = readl(&mipi_dsim->status);
  459. return reg & DSIM_PLL_STABLE ? 1 : 0;
  460. }
  461. unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim)
  462. {
  463. struct exynos_mipi_dsim *mipi_dsim =
  464. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  465. return readl(&mipi_dsim->fifoctrl) & ~(0x1f);
  466. }
  467. void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
  468. unsigned int di, const unsigned char data0, const unsigned char data1)
  469. {
  470. struct exynos_mipi_dsim *mipi_dsim =
  471. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  472. unsigned int reg = (DSIM_PKTHDR_DAT1(data1) | DSIM_PKTHDR_DAT0(data0) |
  473. DSIM_PKTHDR_DI(di));
  474. writel(reg, &mipi_dsim->pkthdr);
  475. }
  476. unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device
  477. *dsim)
  478. {
  479. struct exynos_mipi_dsim *mipi_dsim =
  480. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  481. unsigned int reg = readl(&mipi_dsim->intsrc);
  482. return (reg & INTSRC_FRAME_DONE) ? 1 : 0;
  483. }
  484. void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
  485. {
  486. struct exynos_mipi_dsim *mipi_dsim =
  487. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  488. unsigned int reg = readl(&mipi_dsim->intsrc);
  489. writel(reg | INTSRC_FRAME_DONE, &mipi_dsim->intsrc);
  490. }
  491. void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
  492. unsigned int tx_data)
  493. {
  494. struct exynos_mipi_dsim *mipi_dsim =
  495. (struct exynos_mipi_dsim *)samsung_get_base_mipi_dsim();
  496. writel(tx_data, &mipi_dsim->payload);
  497. }