exynos_mipi_dsi_common.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. *
  5. * Author: InKi Dae <inki.dae@samsung.com>
  6. * Author: Donghwa Lee <dh09.lee@samsung.com>
  7. */
  8. #include <common.h>
  9. #include <lcd.h>
  10. #include <log.h>
  11. #include <linux/delay.h>
  12. #include <linux/err.h>
  13. #include <asm/arch/dsim.h>
  14. #include <asm/arch/mipi_dsim.h>
  15. #include "exynos_mipi_dsi_lowlevel.h"
  16. #define MHZ (1000 * 1000)
  17. #define FIN_HZ (24 * MHZ)
  18. #define DFIN_PLL_MIN_HZ (6 * MHZ)
  19. #define DFIN_PLL_MAX_HZ (12 * MHZ)
  20. #define DFVCO_MIN_HZ (500 * MHZ)
  21. #define DFVCO_MAX_HZ (1000 * MHZ)
  22. #define TRY_GET_FIFO_TIMEOUT (5000 * 2)
  23. /* MIPI-DSIM status types. */
  24. enum {
  25. DSIM_STATE_INIT, /* should be initialized. */
  26. DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
  27. DSIM_STATE_HSCLKEN, /* HS clock was enabled. */
  28. DSIM_STATE_ULPS
  29. };
  30. /* define DSI lane types. */
  31. enum {
  32. DSIM_LANE_CLOCK = (1 << 0),
  33. DSIM_LANE_DATA0 = (1 << 1),
  34. DSIM_LANE_DATA1 = (1 << 2),
  35. DSIM_LANE_DATA2 = (1 << 3),
  36. DSIM_LANE_DATA3 = (1 << 4)
  37. };
  38. static unsigned int dpll_table[15] = {
  39. 100, 120, 170, 220, 270,
  40. 320, 390, 450, 510, 560,
  41. 640, 690, 770, 870, 950
  42. };
  43. static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
  44. const unsigned char *data0, unsigned int data1)
  45. {
  46. unsigned int data_cnt = 0, payload = 0;
  47. /* in case that data count is more then 4 */
  48. for (data_cnt = 0; data_cnt < data1; data_cnt += 4) {
  49. /*
  50. * after sending 4bytes per one time,
  51. * send remainder data less then 4.
  52. */
  53. if ((data1 - data_cnt) < 4) {
  54. if ((data1 - data_cnt) == 3) {
  55. payload = data0[data_cnt] |
  56. data0[data_cnt + 1] << 8 |
  57. data0[data_cnt + 2] << 16;
  58. debug("count = 3 payload = %x, %x %x %x\n",
  59. payload, data0[data_cnt],
  60. data0[data_cnt + 1],
  61. data0[data_cnt + 2]);
  62. } else if ((data1 - data_cnt) == 2) {
  63. payload = data0[data_cnt] |
  64. data0[data_cnt + 1] << 8;
  65. debug("count = 2 payload = %x, %x %x\n", payload,
  66. data0[data_cnt], data0[data_cnt + 1]);
  67. } else if ((data1 - data_cnt) == 1) {
  68. payload = data0[data_cnt];
  69. }
  70. } else {
  71. /* send 4bytes per one time. */
  72. payload = data0[data_cnt] |
  73. data0[data_cnt + 1] << 8 |
  74. data0[data_cnt + 2] << 16 |
  75. data0[data_cnt + 3] << 24;
  76. debug("count = 4 payload = %x, %x %x %x %x\n",
  77. payload, *(u8 *)(data0 + data_cnt),
  78. data0[data_cnt + 1],
  79. data0[data_cnt + 2],
  80. data0[data_cnt + 3]);
  81. }
  82. exynos_mipi_dsi_wr_tx_data(dsim, payload);
  83. }
  84. }
  85. int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
  86. const unsigned char *data0, unsigned int data1)
  87. {
  88. unsigned int timeout = TRY_GET_FIFO_TIMEOUT;
  89. unsigned long delay_val, delay;
  90. unsigned int check_rx_ack = 0;
  91. if (dsim->state == DSIM_STATE_ULPS) {
  92. debug("state is ULPS.\n");
  93. return -EINVAL;
  94. }
  95. delay_val = MHZ / dsim->dsim_config->esc_clk;
  96. delay = 10 * delay_val;
  97. mdelay(delay);
  98. /* only if transfer mode is LPDT, wait SFR becomes empty. */
  99. if (dsim->state == DSIM_STATE_STOP) {
  100. while (!(exynos_mipi_dsi_get_fifo_state(dsim) &
  101. SFR_HEADER_EMPTY)) {
  102. if ((timeout--) > 0)
  103. mdelay(1);
  104. else {
  105. debug("SRF header fifo is not empty.\n");
  106. return -EINVAL;
  107. }
  108. }
  109. }
  110. switch (data_id) {
  111. /* short packet types of packet types for command. */
  112. case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
  113. case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
  114. case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
  115. case MIPI_DSI_DCS_SHORT_WRITE:
  116. case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
  117. case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
  118. debug("data0 = %x data1 = %x\n",
  119. data0[0], data0[1]);
  120. exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
  121. if (check_rx_ack) {
  122. /* process response func should be implemented */
  123. return 0;
  124. } else {
  125. return -EINVAL;
  126. }
  127. /* general command */
  128. case MIPI_DSI_COLOR_MODE_OFF:
  129. case MIPI_DSI_COLOR_MODE_ON:
  130. case MIPI_DSI_SHUTDOWN_PERIPHERAL:
  131. case MIPI_DSI_TURN_ON_PERIPHERAL:
  132. exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
  133. if (check_rx_ack) {
  134. /* process response func should be implemented. */
  135. return 0;
  136. } else {
  137. return -EINVAL;
  138. }
  139. /* packet types for video data */
  140. case MIPI_DSI_V_SYNC_START:
  141. case MIPI_DSI_V_SYNC_END:
  142. case MIPI_DSI_H_SYNC_START:
  143. case MIPI_DSI_H_SYNC_END:
  144. case MIPI_DSI_END_OF_TRANSMISSION:
  145. return 0;
  146. /* short and response packet types for command */
  147. case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
  148. case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
  149. case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
  150. case MIPI_DSI_DCS_READ:
  151. exynos_mipi_dsi_clear_all_interrupt(dsim);
  152. exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
  153. /* process response func should be implemented. */
  154. return 0;
  155. /* long packet type and null packet */
  156. case MIPI_DSI_NULL_PACKET:
  157. case MIPI_DSI_BLANKING_PACKET:
  158. return 0;
  159. case MIPI_DSI_GENERIC_LONG_WRITE:
  160. case MIPI_DSI_DCS_LONG_WRITE:
  161. {
  162. unsigned int payload = 0;
  163. /* if data count is less then 4, then send 3bytes data. */
  164. if (data1 < 4) {
  165. payload = data0[0] |
  166. data0[1] << 8 |
  167. data0[2] << 16;
  168. exynos_mipi_dsi_wr_tx_data(dsim, payload);
  169. debug("count = %d payload = %x,%x %x %x\n",
  170. data1, payload, data0[0],
  171. data0[1], data0[2]);
  172. } else {
  173. /* in case that data count is more then 4 */
  174. exynos_mipi_dsi_long_data_wr(dsim, data0, data1);
  175. }
  176. /* put data into header fifo */
  177. exynos_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff,
  178. (data1 & 0xff00) >> 8);
  179. }
  180. if (check_rx_ack)
  181. /* process response func should be implemented. */
  182. return 0;
  183. else
  184. return -EINVAL;
  185. /* packet typo for video data */
  186. case MIPI_DSI_PACKED_PIXEL_STREAM_16:
  187. case MIPI_DSI_PACKED_PIXEL_STREAM_18:
  188. case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
  189. case MIPI_DSI_PACKED_PIXEL_STREAM_24:
  190. if (check_rx_ack) {
  191. /* process response func should be implemented. */
  192. return 0;
  193. } else {
  194. return -EINVAL;
  195. }
  196. default:
  197. debug("data id %x is not supported current DSI spec.\n",
  198. data_id);
  199. return -EINVAL;
  200. }
  201. return 0;
  202. }
  203. int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable)
  204. {
  205. int sw_timeout;
  206. if (enable) {
  207. sw_timeout = 1000;
  208. exynos_mipi_dsi_clear_interrupt(dsim);
  209. exynos_mipi_dsi_enable_pll(dsim, 1);
  210. while (1) {
  211. sw_timeout--;
  212. if (exynos_mipi_dsi_is_pll_stable(dsim))
  213. return 0;
  214. if (sw_timeout == 0)
  215. return -EINVAL;
  216. }
  217. } else
  218. exynos_mipi_dsi_enable_pll(dsim, 0);
  219. return 0;
  220. }
  221. unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
  222. unsigned int pre_divider, unsigned int main_divider,
  223. unsigned int scaler)
  224. {
  225. unsigned long dfin_pll, dfvco, dpll_out;
  226. unsigned int i, freq_band = 0xf;
  227. dfin_pll = (FIN_HZ / pre_divider);
  228. /******************************************************
  229. * Serial Clock(=ByteClk X 8) FreqBand[3:0] *
  230. ******************************************************
  231. * ~ 99.99 MHz 0000
  232. * 100 ~ 119.99 MHz 0001
  233. * 120 ~ 159.99 MHz 0010
  234. * 160 ~ 199.99 MHz 0011
  235. * 200 ~ 239.99 MHz 0100
  236. * 140 ~ 319.99 MHz 0101
  237. * 320 ~ 389.99 MHz 0110
  238. * 390 ~ 449.99 MHz 0111
  239. * 450 ~ 509.99 MHz 1000
  240. * 510 ~ 559.99 MHz 1001
  241. * 560 ~ 639.99 MHz 1010
  242. * 640 ~ 689.99 MHz 1011
  243. * 690 ~ 769.99 MHz 1100
  244. * 770 ~ 869.99 MHz 1101
  245. * 870 ~ 949.99 MHz 1110
  246. * 950 ~ 1000 MHz 1111
  247. ******************************************************/
  248. if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
  249. debug("fin_pll range should be 6MHz ~ 12MHz\n");
  250. exynos_mipi_dsi_enable_afc(dsim, 0, 0);
  251. } else {
  252. if (dfin_pll < 7 * MHZ)
  253. exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
  254. else if (dfin_pll < 8 * MHZ)
  255. exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
  256. else if (dfin_pll < 9 * MHZ)
  257. exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
  258. else if (dfin_pll < 10 * MHZ)
  259. exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
  260. else if (dfin_pll < 11 * MHZ)
  261. exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
  262. else
  263. exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
  264. }
  265. dfvco = dfin_pll * main_divider;
  266. debug("dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
  267. dfvco, dfin_pll, main_divider);
  268. if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
  269. debug("fvco range should be 500MHz ~ 1000MHz\n");
  270. dpll_out = dfvco / (1 << scaler);
  271. debug("dpll_out = %lu, dfvco = %lu, scaler = %d\n",
  272. dpll_out, dfvco, scaler);
  273. for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
  274. if (dpll_out < dpll_table[i] * MHZ) {
  275. freq_band = i;
  276. break;
  277. }
  278. }
  279. debug("freq_band = %d\n", freq_band);
  280. exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
  281. exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
  282. exynos_mipi_dsi_prep_ctrl(dsim, 0);
  283. /* Freq Band */
  284. exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
  285. /* Stable time */
  286. exynos_mipi_dsi_pll_stable_time(dsim,
  287. dsim->dsim_config->pll_stable_time);
  288. /* Enable PLL */
  289. debug("FOUT of mipi dphy pll is %luMHz\n",
  290. (dpll_out / MHZ));
  291. return dpll_out;
  292. }
  293. int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
  294. unsigned int byte_clk_sel, unsigned int enable)
  295. {
  296. unsigned int esc_div;
  297. unsigned long esc_clk_error_rate;
  298. unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
  299. if (enable) {
  300. dsim->e_clk_src = byte_clk_sel;
  301. /* Escape mode clock and byte clock source */
  302. exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
  303. /* DPHY, DSIM Link : D-PHY clock out */
  304. if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
  305. hs_clk = exynos_mipi_dsi_change_pll(dsim,
  306. dsim->dsim_config->p, dsim->dsim_config->m,
  307. dsim->dsim_config->s);
  308. if (hs_clk == 0) {
  309. debug("failed to get hs clock.\n");
  310. return -EINVAL;
  311. }
  312. byte_clk = hs_clk / 8;
  313. exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
  314. exynos_mipi_dsi_pll_on(dsim, 1);
  315. /* DPHY : D-PHY clock out, DSIM link : external clock out */
  316. } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)
  317. debug("not support EXT CLK source for MIPI DSIM\n");
  318. else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)
  319. debug("not support EXT CLK source for MIPI DSIM\n");
  320. /* escape clock divider */
  321. esc_div = byte_clk / (dsim->dsim_config->esc_clk);
  322. debug("esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
  323. esc_div, byte_clk, dsim->dsim_config->esc_clk);
  324. if ((byte_clk / esc_div) >= (20 * MHZ) ||
  325. (byte_clk / esc_div) > dsim->dsim_config->esc_clk)
  326. esc_div += 1;
  327. escape_clk = byte_clk / esc_div;
  328. debug("escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
  329. escape_clk, byte_clk, esc_div);
  330. /* enable escape clock. */
  331. exynos_mipi_dsi_enable_byte_clock(dsim, 1);
  332. /* enable byte clk and escape clock */
  333. exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
  334. /* escape clock on lane */
  335. exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
  336. (DSIM_LANE_CLOCK | dsim->data_lane), 1);
  337. debug("byte clock is %luMHz\n",
  338. (byte_clk / MHZ));
  339. debug("escape clock that user's need is %lu\n",
  340. (dsim->dsim_config->esc_clk / MHZ));
  341. debug("escape clock divider is %x\n", esc_div);
  342. debug("escape clock is %luMHz\n",
  343. ((byte_clk / esc_div) / MHZ));
  344. if ((byte_clk / esc_div) > escape_clk) {
  345. esc_clk_error_rate = escape_clk /
  346. (byte_clk / esc_div);
  347. debug("error rate is %lu over.\n",
  348. (esc_clk_error_rate / 100));
  349. } else if ((byte_clk / esc_div) < (escape_clk)) {
  350. esc_clk_error_rate = (byte_clk / esc_div) /
  351. escape_clk;
  352. debug("error rate is %lu under.\n",
  353. (esc_clk_error_rate / 100));
  354. }
  355. } else {
  356. exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
  357. (DSIM_LANE_CLOCK | dsim->data_lane), 0);
  358. exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
  359. /* disable escape clock. */
  360. exynos_mipi_dsi_enable_byte_clock(dsim, 0);
  361. if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
  362. exynos_mipi_dsi_pll_on(dsim, 0);
  363. }
  364. return 0;
  365. }
  366. int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
  367. {
  368. dsim->state = DSIM_STATE_INIT;
  369. switch (dsim->dsim_config->e_no_data_lane) {
  370. case DSIM_DATA_LANE_1:
  371. dsim->data_lane = DSIM_LANE_DATA0;
  372. break;
  373. case DSIM_DATA_LANE_2:
  374. dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
  375. break;
  376. case DSIM_DATA_LANE_3:
  377. dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
  378. DSIM_LANE_DATA2;
  379. break;
  380. case DSIM_DATA_LANE_4:
  381. dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
  382. DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
  383. break;
  384. default:
  385. debug("data lane is invalid.\n");
  386. return -EINVAL;
  387. };
  388. exynos_mipi_dsi_sw_reset(dsim);
  389. exynos_mipi_dsi_dp_dn_swap(dsim, 0);
  390. return 0;
  391. }
  392. int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
  393. unsigned int enable)
  394. {
  395. /* enable only frame done interrupt */
  396. exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
  397. return 0;
  398. }
  399. static void convert_to_fb_videomode(struct fb_videomode *mode1,
  400. struct vidinfo *mode2)
  401. {
  402. mode1->xres = mode2->vl_width;
  403. mode1->yres = mode2->vl_height;
  404. mode1->upper_margin = mode2->vl_vfpd;
  405. mode1->lower_margin = mode2->vl_vbpd;
  406. mode1->left_margin = mode2->vl_hfpd;
  407. mode1->right_margin = mode2->vl_hbpd;
  408. mode1->vsync_len = mode2->vl_vspw;
  409. mode1->hsync_len = mode2->vl_hspw;
  410. }
  411. int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
  412. struct mipi_dsim_config *dsim_config)
  413. {
  414. struct exynos_platform_mipi_dsim *dsim_pd;
  415. struct fb_videomode lcd_video;
  416. struct vidinfo *vid;
  417. dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;
  418. vid = (struct vidinfo *)dsim_pd->lcd_panel_info;
  419. convert_to_fb_videomode(&lcd_video, vid);
  420. /* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
  421. if (dsim->dsim_config->e_interface == (u32) DSIM_VIDEO) {
  422. if (dsim->dsim_config->auto_vertical_cnt == 0) {
  423. exynos_mipi_dsi_set_main_disp_vporch(dsim,
  424. vid->vl_cmd_allow_len,
  425. lcd_video.upper_margin,
  426. lcd_video.lower_margin);
  427. exynos_mipi_dsi_set_main_disp_hporch(dsim,
  428. lcd_video.left_margin,
  429. lcd_video.right_margin);
  430. exynos_mipi_dsi_set_main_disp_sync_area(dsim,
  431. lcd_video.vsync_len,
  432. lcd_video.hsync_len);
  433. }
  434. }
  435. exynos_mipi_dsi_set_main_disp_resol(dsim, lcd_video.xres,
  436. lcd_video.yres);
  437. exynos_mipi_dsi_display_config(dsim, dsim->dsim_config);
  438. debug("lcd panel ==> width = %d, height = %d\n",
  439. lcd_video.xres, lcd_video.yres);
  440. return 0;
  441. }
  442. int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
  443. {
  444. unsigned int time_out = 100;
  445. switch (dsim->state) {
  446. case DSIM_STATE_INIT:
  447. exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
  448. /* dsi configuration */
  449. exynos_mipi_dsi_init_config(dsim);
  450. exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
  451. exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
  452. /* set clock configuration */
  453. exynos_mipi_dsi_set_clock(dsim,
  454. dsim->dsim_config->e_byte_clk, 1);
  455. /* check clock and data lane state are stop state */
  456. while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
  457. time_out--;
  458. if (time_out == 0) {
  459. debug("DSI Master is not stop state.\n");
  460. debug("Check initialization process\n");
  461. return -EINVAL;
  462. }
  463. }
  464. dsim->state = DSIM_STATE_STOP;
  465. /* BTA sequence counters */
  466. exynos_mipi_dsi_set_stop_state_counter(dsim,
  467. dsim->dsim_config->stop_holding_cnt);
  468. exynos_mipi_dsi_set_bta_timeout(dsim,
  469. dsim->dsim_config->bta_timeout);
  470. exynos_mipi_dsi_set_lpdr_timeout(dsim,
  471. dsim->dsim_config->rx_timeout);
  472. return 0;
  473. default:
  474. debug("DSI Master is already init.\n");
  475. return 0;
  476. }
  477. return 0;
  478. }
  479. int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
  480. {
  481. if (dsim->state == DSIM_STATE_STOP) {
  482. if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
  483. dsim->state = DSIM_STATE_HSCLKEN;
  484. /* set LCDC and CPU transfer mode to HS. */
  485. exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
  486. exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
  487. exynos_mipi_dsi_enable_hs_clock(dsim, 1);
  488. return 0;
  489. } else
  490. debug("clock source is external bypass.\n");
  491. } else
  492. debug("DSIM is not stop state.\n");
  493. return 0;
  494. }
  495. int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
  496. unsigned int mode)
  497. {
  498. if (mode) {
  499. if (dsim->state != DSIM_STATE_HSCLKEN) {
  500. debug("HS Clock lane is not enabled.\n");
  501. return -EINVAL;
  502. }
  503. exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
  504. } else {
  505. if (dsim->state == DSIM_STATE_INIT || dsim->state ==
  506. DSIM_STATE_ULPS) {
  507. debug("DSI Master is not STOP or HSDT state.\n");
  508. return -EINVAL;
  509. }
  510. exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
  511. }
  512. return 0;
  513. }
  514. int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
  515. {
  516. return _exynos_mipi_dsi_get_frame_done_status(dsim);
  517. }
  518. int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
  519. {
  520. _exynos_mipi_dsi_clear_frame_done(dsim);
  521. return 0;
  522. }