exynos_dp_lowlevel.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. *
  5. * Author: Donghwa Lee <dh09.lee@samsung.com>
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <log.h>
  10. #include <linux/delay.h>
  11. #include <linux/err.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/dp_info.h>
  14. #include <asm/arch/dp.h>
  15. #include <fdtdec.h>
  16. #include <linux/libfdt.h>
  17. #include "exynos_dp_lowlevel.h"
  18. /* Declare global data pointer */
  19. static void exynos_dp_enable_video_input(struct exynos_dp *dp_regs,
  20. unsigned int enable)
  21. {
  22. unsigned int reg;
  23. reg = readl(&dp_regs->video_ctl1);
  24. reg &= ~VIDEO_EN_MASK;
  25. /* enable video input */
  26. if (enable)
  27. reg |= VIDEO_EN_MASK;
  28. writel(reg, &dp_regs->video_ctl1);
  29. return;
  30. }
  31. void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs, unsigned int enable)
  32. {
  33. /* enable video bist */
  34. unsigned int reg;
  35. reg = readl(&dp_regs->video_ctl4);
  36. reg &= ~VIDEO_BIST_MASK;
  37. /* enable video bist */
  38. if (enable)
  39. reg |= VIDEO_BIST_MASK;
  40. writel(reg, &dp_regs->video_ctl4);
  41. return;
  42. }
  43. void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs, unsigned int enable)
  44. {
  45. unsigned int reg;
  46. reg = readl(&dp_regs->video_ctl1);
  47. reg &= ~(VIDEO_MUTE_MASK);
  48. if (enable)
  49. reg |= VIDEO_MUTE_MASK;
  50. writel(reg, &dp_regs->video_ctl1);
  51. return;
  52. }
  53. static void exynos_dp_init_analog_param(struct exynos_dp *dp_regs)
  54. {
  55. unsigned int reg;
  56. /*
  57. * Set termination
  58. * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
  59. * 24M Phy clock, TX digital logic power is 100:1.0625V
  60. */
  61. reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
  62. SWING_A_30PER_G_NORMAL;
  63. writel(reg, &dp_regs->analog_ctl1);
  64. reg = SEL_24M | TX_DVDD_BIT_1_0625V;
  65. writel(reg, &dp_regs->analog_ctl2);
  66. /*
  67. * Set power source for internal clk driver to 1.0625v.
  68. * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
  69. * Set VCO range of PLL +- 0uA
  70. */
  71. reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
  72. writel(reg, &dp_regs->analog_ctl3);
  73. /*
  74. * Set AUX TX terminal resistor to 102 ohm
  75. * Set AUX channel amplitude control
  76. */
  77. reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
  78. writel(reg, &dp_regs->pll_filter_ctl1);
  79. /*
  80. * PLL loop filter bandwidth
  81. * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
  82. * PLL digital power select: 1.2500V
  83. */
  84. reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
  85. writel(reg, &dp_regs->amp_tuning_ctl);
  86. /*
  87. * PLL loop filter bandwidth
  88. * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
  89. * PLL digital power select: 1.1250V
  90. */
  91. reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
  92. writel(reg, &dp_regs->pll_ctl);
  93. }
  94. static void exynos_dp_init_interrupt(struct exynos_dp *dp_regs)
  95. {
  96. /* Set interrupt registers to initial states */
  97. /*
  98. * Disable interrupt
  99. * INT pin assertion polarity. It must be configured
  100. * correctly according to ICU setting.
  101. * 1 = assert high, 0 = assert low
  102. */
  103. writel(INT_POL, &dp_regs->int_ctl);
  104. /* Clear pending registers */
  105. writel(0xff, &dp_regs->common_int_sta1);
  106. writel(0xff, &dp_regs->common_int_sta2);
  107. writel(0xff, &dp_regs->common_int_sta3);
  108. writel(0xff, &dp_regs->common_int_sta4);
  109. writel(0xff, &dp_regs->int_sta);
  110. /* 0:mask,1: unmask */
  111. writel(0x00, &dp_regs->int_sta_mask1);
  112. writel(0x00, &dp_regs->int_sta_mask2);
  113. writel(0x00, &dp_regs->int_sta_mask3);
  114. writel(0x00, &dp_regs->int_sta_mask4);
  115. writel(0x00, &dp_regs->int_sta_mask);
  116. }
  117. void exynos_dp_reset(struct exynos_dp *dp_regs)
  118. {
  119. unsigned int reg_func_1;
  120. /* dp tx sw reset */
  121. writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
  122. exynos_dp_enable_video_input(dp_regs, DP_DISABLE);
  123. exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
  124. exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
  125. /* software reset */
  126. reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
  127. AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
  128. HDCP_FUNC_EN_N | SW_FUNC_EN_N;
  129. writel(reg_func_1, &dp_regs->func_en1);
  130. writel(reg_func_1, &dp_regs->func_en2);
  131. mdelay(1);
  132. exynos_dp_init_analog_param(dp_regs);
  133. exynos_dp_init_interrupt(dp_regs);
  134. return;
  135. }
  136. void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable)
  137. {
  138. unsigned int reg;
  139. reg = readl(&dp_regs->func_en1);
  140. reg &= ~(SW_FUNC_EN_N);
  141. if (!enable)
  142. reg |= SW_FUNC_EN_N;
  143. writel(reg, &dp_regs->func_en1);
  144. return;
  145. }
  146. unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs,
  147. unsigned int block, u32 enable)
  148. {
  149. unsigned int reg;
  150. reg = readl(&dp_regs->phy_pd);
  151. switch (block) {
  152. case AUX_BLOCK:
  153. reg &= ~(AUX_PD);
  154. if (enable)
  155. reg |= AUX_PD;
  156. break;
  157. case CH0_BLOCK:
  158. reg &= ~(CH0_PD);
  159. if (enable)
  160. reg |= CH0_PD;
  161. break;
  162. case CH1_BLOCK:
  163. reg &= ~(CH1_PD);
  164. if (enable)
  165. reg |= CH1_PD;
  166. break;
  167. case CH2_BLOCK:
  168. reg &= ~(CH2_PD);
  169. if (enable)
  170. reg |= CH2_PD;
  171. break;
  172. case CH3_BLOCK:
  173. reg &= ~(CH3_PD);
  174. if (enable)
  175. reg |= CH3_PD;
  176. break;
  177. case ANALOG_TOTAL:
  178. reg &= ~PHY_PD;
  179. if (enable)
  180. reg |= PHY_PD;
  181. break;
  182. case POWER_ALL:
  183. reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
  184. CH3_PD);
  185. if (enable)
  186. reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
  187. CH2_PD | CH3_PD);
  188. break;
  189. default:
  190. printf("DP undefined block number : %d\n", block);
  191. return -1;
  192. }
  193. writel(reg, &dp_regs->phy_pd);
  194. return 0;
  195. }
  196. unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs)
  197. {
  198. unsigned int reg;
  199. reg = readl(&dp_regs->debug_ctl);
  200. if (reg & PLL_LOCK)
  201. return PLL_LOCKED;
  202. else
  203. return PLL_UNLOCKED;
  204. }
  205. static void exynos_dp_set_pll_power(struct exynos_dp *dp_regs,
  206. unsigned int enable)
  207. {
  208. unsigned int reg;
  209. reg = readl(&dp_regs->pll_ctl);
  210. reg &= ~(DP_PLL_PD);
  211. if (!enable)
  212. reg |= DP_PLL_PD;
  213. writel(reg, &dp_regs->pll_ctl);
  214. }
  215. int exynos_dp_init_analog_func(struct exynos_dp *dp_regs)
  216. {
  217. int ret = EXYNOS_DP_SUCCESS;
  218. unsigned int retry_cnt = 10;
  219. unsigned int reg;
  220. /* Power On All Analog block */
  221. exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, DP_DISABLE);
  222. reg = PLL_LOCK_CHG;
  223. writel(reg, &dp_regs->common_int_sta1);
  224. reg = readl(&dp_regs->debug_ctl);
  225. reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
  226. writel(reg, &dp_regs->debug_ctl);
  227. /* Assert DP PLL Reset */
  228. reg = readl(&dp_regs->pll_ctl);
  229. reg |= DP_PLL_RESET;
  230. writel(reg, &dp_regs->pll_ctl);
  231. mdelay(1);
  232. /* Deassert DP PLL Reset */
  233. reg = readl(&dp_regs->pll_ctl);
  234. reg &= ~(DP_PLL_RESET);
  235. writel(reg, &dp_regs->pll_ctl);
  236. exynos_dp_set_pll_power(dp_regs, DP_ENABLE);
  237. while (exynos_dp_get_pll_lock_status(dp_regs) == PLL_UNLOCKED) {
  238. mdelay(1);
  239. retry_cnt--;
  240. if (retry_cnt == 0) {
  241. printf("DP dp's pll lock failed : retry : %d\n",
  242. retry_cnt);
  243. return -EINVAL;
  244. }
  245. }
  246. debug("dp's pll lock success(%d)\n", retry_cnt);
  247. /* Enable Serdes FIFO function and Link symbol clock domain module */
  248. reg = readl(&dp_regs->func_en2);
  249. reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
  250. | AUX_FUNC_EN_N);
  251. writel(reg, &dp_regs->func_en2);
  252. return ret;
  253. }
  254. void exynos_dp_init_hpd(struct exynos_dp *dp_regs)
  255. {
  256. unsigned int reg;
  257. /* Clear interrupts related to Hot Plug Detect */
  258. reg = HOTPLUG_CHG | HPD_LOST | PLUG;
  259. writel(reg, &dp_regs->common_int_sta4);
  260. reg = INT_HPD;
  261. writel(reg, &dp_regs->int_sta);
  262. reg = readl(&dp_regs->sys_ctl3);
  263. reg &= ~(F_HPD | HPD_CTRL);
  264. writel(reg, &dp_regs->sys_ctl3);
  265. return;
  266. }
  267. static inline void exynos_dp_reset_aux(struct exynos_dp *dp_regs)
  268. {
  269. unsigned int reg;
  270. /* Disable AUX channel module */
  271. reg = readl(&dp_regs->func_en2);
  272. reg |= AUX_FUNC_EN_N;
  273. writel(reg, &dp_regs->func_en2);
  274. return;
  275. }
  276. void exynos_dp_init_aux(struct exynos_dp *dp_regs)
  277. {
  278. unsigned int reg;
  279. /* Clear interrupts related to AUX channel */
  280. reg = RPLY_RECEIV | AUX_ERR;
  281. writel(reg, &dp_regs->int_sta);
  282. exynos_dp_reset_aux(dp_regs);
  283. /* Disable AUX transaction H/W retry */
  284. reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
  285. AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
  286. writel(reg, &dp_regs->aux_hw_retry_ctl);
  287. /* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */
  288. reg = DEFER_CTRL_EN | DEFER_COUNT(1);
  289. writel(reg, &dp_regs->aux_ch_defer_ctl);
  290. /* Enable AUX channel module */
  291. reg = readl(&dp_regs->func_en2);
  292. reg &= ~AUX_FUNC_EN_N;
  293. writel(reg, &dp_regs->func_en2);
  294. return;
  295. }
  296. void exynos_dp_config_interrupt(struct exynos_dp *dp_regs)
  297. {
  298. unsigned int reg;
  299. /* 0: mask, 1: unmask */
  300. reg = COMMON_INT_MASK_1;
  301. writel(reg, &dp_regs->common_int_mask1);
  302. reg = COMMON_INT_MASK_2;
  303. writel(reg, &dp_regs->common_int_mask2);
  304. reg = COMMON_INT_MASK_3;
  305. writel(reg, &dp_regs->common_int_mask3);
  306. reg = COMMON_INT_MASK_4;
  307. writel(reg, &dp_regs->common_int_mask4);
  308. reg = INT_STA_MASK;
  309. writel(reg, &dp_regs->int_sta_mask);
  310. return;
  311. }
  312. unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs)
  313. {
  314. unsigned int reg;
  315. reg = readl(&dp_regs->sys_ctl3);
  316. if (reg & HPD_STATUS)
  317. return 0;
  318. return -1;
  319. }
  320. unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs)
  321. {
  322. int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
  323. mdelay(2);
  324. while (exynos_dp_get_plug_in_status(dp_regs) != 0) {
  325. if (timeout_loop == 0)
  326. return -EINVAL;
  327. mdelay(10);
  328. timeout_loop--;
  329. }
  330. return EXYNOS_DP_SUCCESS;
  331. }
  332. unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs)
  333. {
  334. unsigned int reg;
  335. unsigned int ret = 0;
  336. unsigned int retry_cnt;
  337. /* Enable AUX CH operation */
  338. reg = readl(&dp_regs->aux_ch_ctl2);
  339. reg |= AUX_EN;
  340. writel(reg, &dp_regs->aux_ch_ctl2);
  341. retry_cnt = 10;
  342. while (retry_cnt) {
  343. reg = readl(&dp_regs->int_sta);
  344. if (!(reg & RPLY_RECEIV)) {
  345. if (retry_cnt == 0) {
  346. printf("DP Reply Timeout!!\n");
  347. ret = -EAGAIN;
  348. return ret;
  349. }
  350. mdelay(1);
  351. retry_cnt--;
  352. } else
  353. break;
  354. }
  355. /* Clear interrupt source for AUX CH command reply */
  356. writel(reg, &dp_regs->int_sta);
  357. /* Clear interrupt source for AUX CH access error */
  358. reg = readl(&dp_regs->int_sta);
  359. if (reg & AUX_ERR) {
  360. printf("DP Aux Access Error\n");
  361. writel(AUX_ERR, &dp_regs->int_sta);
  362. ret = -EAGAIN;
  363. return ret;
  364. }
  365. /* Check AUX CH error access status */
  366. reg = readl(&dp_regs->aux_ch_sta);
  367. if ((reg & AUX_STATUS_MASK) != 0) {
  368. debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
  369. ret = -EAGAIN;
  370. return ret;
  371. }
  372. return EXYNOS_DP_SUCCESS;
  373. }
  374. unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs,
  375. unsigned int reg_addr,
  376. unsigned char data)
  377. {
  378. unsigned int reg, ret;
  379. /* Clear AUX CH data buffer */
  380. reg = BUF_CLR;
  381. writel(reg, &dp_regs->buffer_data_ctl);
  382. /* Select DPCD device address */
  383. reg = AUX_ADDR_7_0(reg_addr);
  384. writel(reg, &dp_regs->aux_addr_7_0);
  385. reg = AUX_ADDR_15_8(reg_addr);
  386. writel(reg, &dp_regs->aux_addr_15_8);
  387. reg = AUX_ADDR_19_16(reg_addr);
  388. writel(reg, &dp_regs->aux_addr_19_16);
  389. /* Write data buffer */
  390. reg = (unsigned int)data;
  391. writel(reg, &dp_regs->buf_data0);
  392. /*
  393. * Set DisplayPort transaction and write 1 byte
  394. * If bit 3 is 1, DisplayPort transaction.
  395. * If Bit 3 is 0, I2C transaction.
  396. */
  397. reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
  398. writel(reg, &dp_regs->aux_ch_ctl1);
  399. /* Start AUX transaction */
  400. ret = exynos_dp_start_aux_transaction(dp_regs);
  401. if (ret != EXYNOS_DP_SUCCESS) {
  402. printf("DP Aux transaction failed\n");
  403. return ret;
  404. }
  405. return ret;
  406. }
  407. unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs,
  408. unsigned int reg_addr,
  409. unsigned char *data)
  410. {
  411. unsigned int reg;
  412. int retval;
  413. /* Clear AUX CH data buffer */
  414. reg = BUF_CLR;
  415. writel(reg, &dp_regs->buffer_data_ctl);
  416. /* Select DPCD device address */
  417. reg = AUX_ADDR_7_0(reg_addr);
  418. writel(reg, &dp_regs->aux_addr_7_0);
  419. reg = AUX_ADDR_15_8(reg_addr);
  420. writel(reg, &dp_regs->aux_addr_15_8);
  421. reg = AUX_ADDR_19_16(reg_addr);
  422. writel(reg, &dp_regs->aux_addr_19_16);
  423. /*
  424. * Set DisplayPort transaction and read 1 byte
  425. * If bit 3 is 1, DisplayPort transaction.
  426. * If Bit 3 is 0, I2C transaction.
  427. */
  428. reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
  429. writel(reg, &dp_regs->aux_ch_ctl1);
  430. /* Start AUX transaction */
  431. retval = exynos_dp_start_aux_transaction(dp_regs);
  432. if (!retval)
  433. debug("DP Aux Transaction fail!\n");
  434. /* Read data buffer */
  435. reg = readl(&dp_regs->buf_data0);
  436. *data = (unsigned char)(reg & 0xff);
  437. return retval;
  438. }
  439. unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs,
  440. unsigned int reg_addr,
  441. unsigned int count,
  442. unsigned char data[])
  443. {
  444. unsigned int reg;
  445. unsigned int start_offset;
  446. unsigned int cur_data_count;
  447. unsigned int cur_data_idx;
  448. unsigned int retry_cnt;
  449. unsigned int ret = 0;
  450. /* Clear AUX CH data buffer */
  451. reg = BUF_CLR;
  452. writel(reg, &dp_regs->buffer_data_ctl);
  453. start_offset = 0;
  454. while (start_offset < count) {
  455. /* Buffer size of AUX CH is 16 * 4bytes */
  456. if ((count - start_offset) > 16)
  457. cur_data_count = 16;
  458. else
  459. cur_data_count = count - start_offset;
  460. retry_cnt = 5;
  461. while (retry_cnt) {
  462. /* Select DPCD device address */
  463. reg = AUX_ADDR_7_0(reg_addr + start_offset);
  464. writel(reg, &dp_regs->aux_addr_7_0);
  465. reg = AUX_ADDR_15_8(reg_addr + start_offset);
  466. writel(reg, &dp_regs->aux_addr_15_8);
  467. reg = AUX_ADDR_19_16(reg_addr + start_offset);
  468. writel(reg, &dp_regs->aux_addr_19_16);
  469. for (cur_data_idx = 0; cur_data_idx < cur_data_count;
  470. cur_data_idx++) {
  471. reg = data[start_offset + cur_data_idx];
  472. writel(reg, (unsigned int)&dp_regs->buf_data0 +
  473. (4 * cur_data_idx));
  474. }
  475. /*
  476. * Set DisplayPort transaction and write
  477. * If bit 3 is 1, DisplayPort transaction.
  478. * If Bit 3 is 0, I2C transaction.
  479. */
  480. reg = AUX_LENGTH(cur_data_count) |
  481. AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
  482. writel(reg, &dp_regs->aux_ch_ctl1);
  483. /* Start AUX transaction */
  484. ret = exynos_dp_start_aux_transaction(dp_regs);
  485. if (ret != EXYNOS_DP_SUCCESS) {
  486. if (retry_cnt == 0) {
  487. printf("DP Aux Transaction failed\n");
  488. return ret;
  489. }
  490. retry_cnt--;
  491. } else
  492. break;
  493. }
  494. start_offset += cur_data_count;
  495. }
  496. return ret;
  497. }
  498. unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs,
  499. unsigned int reg_addr,
  500. unsigned int count,
  501. unsigned char data[])
  502. {
  503. unsigned int reg;
  504. unsigned int start_offset;
  505. unsigned int cur_data_count;
  506. unsigned int cur_data_idx;
  507. unsigned int retry_cnt;
  508. unsigned int ret = 0;
  509. /* Clear AUX CH data buffer */
  510. reg = BUF_CLR;
  511. writel(reg, &dp_regs->buffer_data_ctl);
  512. start_offset = 0;
  513. while (start_offset < count) {
  514. /* Buffer size of AUX CH is 16 * 4bytes */
  515. if ((count - start_offset) > 16)
  516. cur_data_count = 16;
  517. else
  518. cur_data_count = count - start_offset;
  519. retry_cnt = 5;
  520. while (retry_cnt) {
  521. /* Select DPCD device address */
  522. reg = AUX_ADDR_7_0(reg_addr + start_offset);
  523. writel(reg, &dp_regs->aux_addr_7_0);
  524. reg = AUX_ADDR_15_8(reg_addr + start_offset);
  525. writel(reg, &dp_regs->aux_addr_15_8);
  526. reg = AUX_ADDR_19_16(reg_addr + start_offset);
  527. writel(reg, &dp_regs->aux_addr_19_16);
  528. /*
  529. * Set DisplayPort transaction and read
  530. * If bit 3 is 1, DisplayPort transaction.
  531. * If Bit 3 is 0, I2C transaction.
  532. */
  533. reg = AUX_LENGTH(cur_data_count) |
  534. AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
  535. writel(reg, &dp_regs->aux_ch_ctl1);
  536. /* Start AUX transaction */
  537. ret = exynos_dp_start_aux_transaction(dp_regs);
  538. if (ret != EXYNOS_DP_SUCCESS) {
  539. if (retry_cnt == 0) {
  540. printf("DP Aux Transaction failed\n");
  541. return ret;
  542. }
  543. retry_cnt--;
  544. } else
  545. break;
  546. }
  547. for (cur_data_idx = 0; cur_data_idx < cur_data_count;
  548. cur_data_idx++) {
  549. reg = readl((unsigned int)&dp_regs->buf_data0 +
  550. 4 * cur_data_idx);
  551. data[start_offset + cur_data_idx] = (unsigned char)reg;
  552. }
  553. start_offset += cur_data_count;
  554. }
  555. return ret;
  556. }
  557. int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs,
  558. unsigned int device_addr, unsigned int reg_addr)
  559. {
  560. unsigned int reg;
  561. int retval;
  562. /* Set EDID device address */
  563. reg = device_addr;
  564. writel(reg, &dp_regs->aux_addr_7_0);
  565. writel(0x0, &dp_regs->aux_addr_15_8);
  566. writel(0x0, &dp_regs->aux_addr_19_16);
  567. /* Set offset from base address of EDID device */
  568. writel(reg_addr, &dp_regs->buf_data0);
  569. /*
  570. * Set I2C transaction and write address
  571. * If bit 3 is 1, DisplayPort transaction.
  572. * If Bit 3 is 0, I2C transaction.
  573. */
  574. reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
  575. AUX_TX_COMM_WRITE;
  576. writel(reg, &dp_regs->aux_ch_ctl1);
  577. /* Start AUX transaction */
  578. retval = exynos_dp_start_aux_transaction(dp_regs);
  579. if (retval != 0)
  580. printf("%s: DP Aux Transaction fail!\n", __func__);
  581. return retval;
  582. }
  583. int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs,
  584. unsigned int device_addr,
  585. unsigned int reg_addr, unsigned int *data)
  586. {
  587. unsigned int reg;
  588. int i;
  589. int retval;
  590. for (i = 0; i < 10; i++) {
  591. /* Clear AUX CH data buffer */
  592. reg = BUF_CLR;
  593. writel(reg, &dp_regs->buffer_data_ctl);
  594. /* Select EDID device */
  595. retval = exynos_dp_select_i2c_device(dp_regs, device_addr,
  596. reg_addr);
  597. if (retval != 0) {
  598. printf("DP Select EDID device fail. retry !\n");
  599. continue;
  600. }
  601. /*
  602. * Set I2C transaction and read data
  603. * If bit 3 is 1, DisplayPort transaction.
  604. * If Bit 3 is 0, I2C transaction.
  605. */
  606. reg = AUX_TX_COMM_I2C_TRANSACTION |
  607. AUX_TX_COMM_READ;
  608. writel(reg, &dp_regs->aux_ch_ctl1);
  609. /* Start AUX transaction */
  610. retval = exynos_dp_start_aux_transaction(dp_regs);
  611. if (retval != EXYNOS_DP_SUCCESS)
  612. printf("%s: DP Aux Transaction fail!\n", __func__);
  613. }
  614. /* Read data */
  615. if (retval == 0)
  616. *data = readl(&dp_regs->buf_data0);
  617. return retval;
  618. }
  619. int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs,
  620. unsigned int device_addr,
  621. unsigned int reg_addr, unsigned int count,
  622. unsigned char edid[])
  623. {
  624. unsigned int reg;
  625. unsigned int i, j;
  626. unsigned int cur_data_idx;
  627. unsigned int defer = 0;
  628. int retval = 0;
  629. for (i = 0; i < count; i += 16) { /* use 16 burst */
  630. for (j = 0; j < 100; j++) {
  631. /* Clear AUX CH data buffer */
  632. reg = BUF_CLR;
  633. writel(reg, &dp_regs->buffer_data_ctl);
  634. /* Set normal AUX CH command */
  635. reg = readl(&dp_regs->aux_ch_ctl2);
  636. reg &= ~ADDR_ONLY;
  637. writel(reg, &dp_regs->aux_ch_ctl2);
  638. /*
  639. * If Rx sends defer, Tx sends only reads
  640. * request without sending addres
  641. */
  642. if (!defer)
  643. retval = exynos_dp_select_i2c_device(
  644. dp_regs, device_addr, reg_addr + i);
  645. else
  646. defer = 0;
  647. if (retval == EXYNOS_DP_SUCCESS) {
  648. /*
  649. * Set I2C transaction and write data
  650. * If bit 3 is 1, DisplayPort transaction.
  651. * If Bit 3 is 0, I2C transaction.
  652. */
  653. reg = AUX_LENGTH(16) |
  654. AUX_TX_COMM_I2C_TRANSACTION |
  655. AUX_TX_COMM_READ;
  656. writel(reg, &dp_regs->aux_ch_ctl1);
  657. /* Start AUX transaction */
  658. retval = exynos_dp_start_aux_transaction(
  659. dp_regs);
  660. if (retval == 0)
  661. break;
  662. else
  663. printf("DP Aux Transaction fail!\n");
  664. }
  665. /* Check if Rx sends defer */
  666. reg = readl(&dp_regs->aux_rx_comm);
  667. if (reg == AUX_RX_COMM_AUX_DEFER ||
  668. reg == AUX_RX_COMM_I2C_DEFER) {
  669. printf("DP Defer: %d\n", reg);
  670. defer = 1;
  671. }
  672. }
  673. for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
  674. reg = readl((unsigned int)&dp_regs->buf_data0
  675. + 4 * cur_data_idx);
  676. edid[i + cur_data_idx] = (unsigned char)reg;
  677. }
  678. }
  679. return retval;
  680. }
  681. void exynos_dp_reset_macro(struct exynos_dp *dp_regs)
  682. {
  683. unsigned int reg;
  684. reg = readl(&dp_regs->phy_test);
  685. reg |= MACRO_RST;
  686. writel(reg, &dp_regs->phy_test);
  687. /* 10 us is the minimum Macro reset time. */
  688. mdelay(1);
  689. reg &= ~MACRO_RST;
  690. writel(reg, &dp_regs->phy_test);
  691. }
  692. void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs,
  693. unsigned char bwtype)
  694. {
  695. unsigned int reg;
  696. reg = (unsigned int)bwtype;
  697. /* Set bandwidth to 2.7G or 1.62G */
  698. if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
  699. writel(reg, &dp_regs->link_bw_set);
  700. }
  701. unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs)
  702. {
  703. unsigned char ret;
  704. unsigned int reg;
  705. reg = readl(&dp_regs->link_bw_set);
  706. ret = (unsigned char)reg;
  707. return ret;
  708. }
  709. void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count)
  710. {
  711. unsigned int reg;
  712. reg = (unsigned int)count;
  713. if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
  714. (count == DP_LANE_CNT_4))
  715. writel(reg, &dp_regs->lane_count_set);
  716. }
  717. unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs)
  718. {
  719. return readl(&dp_regs->lane_count_set);
  720. }
  721. unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
  722. unsigned char lanecnt)
  723. {
  724. unsigned int reg_list[DP_LANE_CNT_4] = {
  725. (unsigned int)&dp_regs->ln0_link_training_ctl,
  726. (unsigned int)&dp_regs->ln1_link_training_ctl,
  727. (unsigned int)&dp_regs->ln2_link_training_ctl,
  728. (unsigned int)&dp_regs->ln3_link_training_ctl,
  729. };
  730. return readl(reg_list[lanecnt]);
  731. }
  732. void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs,
  733. unsigned char request_val,
  734. unsigned char lanecnt)
  735. {
  736. unsigned int reg_list[DP_LANE_CNT_4] = {
  737. (unsigned int)&dp_regs->ln0_link_training_ctl,
  738. (unsigned int)&dp_regs->ln1_link_training_ctl,
  739. (unsigned int)&dp_regs->ln2_link_training_ctl,
  740. (unsigned int)&dp_regs->ln3_link_training_ctl,
  741. };
  742. writel(request_val, reg_list[lanecnt]);
  743. }
  744. void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs,
  745. unsigned int level, unsigned char lanecnt)
  746. {
  747. unsigned char i;
  748. unsigned int reg;
  749. unsigned int reg_list[DP_LANE_CNT_4] = {
  750. (unsigned int)&dp_regs->ln0_link_training_ctl,
  751. (unsigned int)&dp_regs->ln1_link_training_ctl,
  752. (unsigned int)&dp_regs->ln2_link_training_ctl,
  753. (unsigned int)&dp_regs->ln3_link_training_ctl,
  754. };
  755. unsigned int reg_shift[DP_LANE_CNT_4] = {
  756. PRE_EMPHASIS_SET_0_SHIFT,
  757. PRE_EMPHASIS_SET_1_SHIFT,
  758. PRE_EMPHASIS_SET_2_SHIFT,
  759. PRE_EMPHASIS_SET_3_SHIFT
  760. };
  761. for (i = 0; i < lanecnt; i++) {
  762. reg = level << reg_shift[i];
  763. writel(reg, reg_list[i]);
  764. }
  765. }
  766. void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs,
  767. unsigned int pattern)
  768. {
  769. unsigned int reg = 0;
  770. switch (pattern) {
  771. case PRBS7:
  772. reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
  773. break;
  774. case D10_2:
  775. reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
  776. break;
  777. case TRAINING_PTN1:
  778. reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
  779. break;
  780. case TRAINING_PTN2:
  781. reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
  782. break;
  783. case DP_NONE:
  784. reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
  785. SW_TRAINING_PATTERN_SET_NORMAL;
  786. break;
  787. default:
  788. break;
  789. }
  790. writel(reg, &dp_regs->training_ptn_set);
  791. }
  792. void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs,
  793. unsigned char enable)
  794. {
  795. unsigned int reg;
  796. reg = readl(&dp_regs->sys_ctl4);
  797. reg &= ~ENHANCED;
  798. if (enable)
  799. reg |= ENHANCED;
  800. writel(reg, &dp_regs->sys_ctl4);
  801. }
  802. void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs, unsigned int enable)
  803. {
  804. unsigned int reg;
  805. reg = readl(&dp_regs->training_ptn_set);
  806. reg &= ~(SCRAMBLING_DISABLE);
  807. if (!enable)
  808. reg |= SCRAMBLING_DISABLE;
  809. writel(reg, &dp_regs->training_ptn_set);
  810. }
  811. int exynos_dp_init_video(struct exynos_dp *dp_regs)
  812. {
  813. unsigned int reg;
  814. /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
  815. reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
  816. writel(reg, &dp_regs->common_int_sta1);
  817. /* I_STRM__CLK detect : DE_CTL : Auto detect */
  818. reg &= ~DET_CTRL;
  819. writel(reg, &dp_regs->sys_ctl1);
  820. return 0;
  821. }
  822. void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
  823. struct edp_video_info *video_info)
  824. {
  825. unsigned int reg;
  826. /* Video Slave mode setting */
  827. reg = readl(&dp_regs->func_en1);
  828. reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
  829. reg |= MASTER_VID_FUNC_EN_N;
  830. writel(reg, &dp_regs->func_en1);
  831. /* Configure Interlaced for slave mode video */
  832. reg = readl(&dp_regs->video_ctl10);
  833. reg &= ~INTERACE_SCAN_CFG;
  834. reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
  835. writel(reg, &dp_regs->video_ctl10);
  836. /* Configure V sync polarity for slave mode video */
  837. reg = readl(&dp_regs->video_ctl10);
  838. reg &= ~VSYNC_POLARITY_CFG;
  839. reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
  840. writel(reg, &dp_regs->video_ctl10);
  841. /* Configure H sync polarity for slave mode video */
  842. reg = readl(&dp_regs->video_ctl10);
  843. reg &= ~HSYNC_POLARITY_CFG;
  844. reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
  845. writel(reg, &dp_regs->video_ctl10);
  846. /* Set video mode to slave mode */
  847. reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
  848. writel(reg, &dp_regs->soc_general_ctl);
  849. }
  850. void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
  851. struct edp_video_info *video_info)
  852. {
  853. unsigned int reg;
  854. /* Configure the input color depth, color space, dynamic range */
  855. reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
  856. (video_info->color_depth << IN_BPC_SHIFT) |
  857. (video_info->color_space << IN_COLOR_F_SHIFT);
  858. writel(reg, &dp_regs->video_ctl2);
  859. /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
  860. reg = readl(&dp_regs->video_ctl3);
  861. reg &= ~IN_YC_COEFFI_MASK;
  862. if (video_info->ycbcr_coeff)
  863. reg |= IN_YC_COEFFI_ITU709;
  864. else
  865. reg |= IN_YC_COEFFI_ITU601;
  866. writel(reg, &dp_regs->video_ctl3);
  867. }
  868. int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
  869. struct exynos_dp_priv *priv)
  870. {
  871. unsigned int reg;
  872. unsigned int bist_type = 0;
  873. struct edp_video_info video_info = priv->video_info;
  874. /* For master mode, you don't need to set the video format */
  875. if (video_info.master_mode == 0) {
  876. writel(TOTAL_LINE_CFG_L(priv->disp_info.v_total),
  877. &dp_regs->total_ln_cfg_l);
  878. writel(TOTAL_LINE_CFG_H(priv->disp_info.v_total),
  879. &dp_regs->total_ln_cfg_h);
  880. writel(ACTIVE_LINE_CFG_L(priv->disp_info.v_res),
  881. &dp_regs->active_ln_cfg_l);
  882. writel(ACTIVE_LINE_CFG_H(priv->disp_info.v_res),
  883. &dp_regs->active_ln_cfg_h);
  884. writel(priv->disp_info.v_sync_width, &dp_regs->vsw_cfg);
  885. writel(priv->disp_info.v_back_porch, &dp_regs->vbp_cfg);
  886. writel(priv->disp_info.v_front_porch, &dp_regs->vfp_cfg);
  887. writel(TOTAL_PIXEL_CFG_L(priv->disp_info.h_total),
  888. &dp_regs->total_pix_cfg_l);
  889. writel(TOTAL_PIXEL_CFG_H(priv->disp_info.h_total),
  890. &dp_regs->total_pix_cfg_h);
  891. writel(ACTIVE_PIXEL_CFG_L(priv->disp_info.h_res),
  892. &dp_regs->active_pix_cfg_l);
  893. writel(ACTIVE_PIXEL_CFG_H(priv->disp_info.h_res),
  894. &dp_regs->active_pix_cfg_h);
  895. writel(H_F_PORCH_CFG_L(priv->disp_info.h_front_porch),
  896. &dp_regs->hfp_cfg_l);
  897. writel(H_F_PORCH_CFG_H(priv->disp_info.h_front_porch),
  898. &dp_regs->hfp_cfg_h);
  899. writel(H_SYNC_PORCH_CFG_L(priv->disp_info.h_sync_width),
  900. &dp_regs->hsw_cfg_l);
  901. writel(H_SYNC_PORCH_CFG_H(priv->disp_info.h_sync_width),
  902. &dp_regs->hsw_cfg_h);
  903. writel(H_B_PORCH_CFG_L(priv->disp_info.h_back_porch),
  904. &dp_regs->hbp_cfg_l);
  905. writel(H_B_PORCH_CFG_H(priv->disp_info.h_back_porch),
  906. &dp_regs->hbp_cfg_h);
  907. /*
  908. * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
  909. * HSYNC_P_CFG[0] properly
  910. */
  911. reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT |
  912. video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT |
  913. video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
  914. writel(reg, &dp_regs->video_ctl10);
  915. }
  916. /* BIST color bar width set--set to each bar is 32 pixel width */
  917. switch (video_info.bist_pattern) {
  918. case COLORBAR_32:
  919. bist_type = BIST_WIDTH_BAR_32_PIXEL |
  920. BIST_TYPE_COLOR_BAR;
  921. break;
  922. case COLORBAR_64:
  923. bist_type = BIST_WIDTH_BAR_64_PIXEL |
  924. BIST_TYPE_COLOR_BAR;
  925. break;
  926. case WHITE_GRAY_BALCKBAR_32:
  927. bist_type = BIST_WIDTH_BAR_32_PIXEL |
  928. BIST_TYPE_WHITE_GRAY_BLACK_BAR;
  929. break;
  930. case WHITE_GRAY_BALCKBAR_64:
  931. bist_type = BIST_WIDTH_BAR_64_PIXEL |
  932. BIST_TYPE_WHITE_GRAY_BLACK_BAR;
  933. break;
  934. case MOBILE_WHITEBAR_32:
  935. bist_type = BIST_WIDTH_BAR_32_PIXEL |
  936. BIST_TYPE_MOBILE_WHITE_BAR;
  937. break;
  938. case MOBILE_WHITEBAR_64:
  939. bist_type = BIST_WIDTH_BAR_64_PIXEL |
  940. BIST_TYPE_MOBILE_WHITE_BAR;
  941. break;
  942. default:
  943. return -1;
  944. }
  945. reg = bist_type;
  946. writel(reg, &dp_regs->video_ctl4);
  947. return 0;
  948. }
  949. unsigned int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp *dp_regs)
  950. {
  951. unsigned int reg;
  952. /* Update Video stream clk detect status */
  953. reg = readl(&dp_regs->sys_ctl1);
  954. writel(reg, &dp_regs->sys_ctl1);
  955. reg = readl(&dp_regs->sys_ctl1);
  956. if (!(reg & DET_STA)) {
  957. debug("DP Input stream clock not detected.\n");
  958. return -EIO;
  959. }
  960. return EXYNOS_DP_SUCCESS;
  961. }
  962. void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
  963. unsigned int m_value, unsigned int n_value)
  964. {
  965. unsigned int reg;
  966. if (type == REGISTER_M) {
  967. reg = readl(&dp_regs->sys_ctl4);
  968. reg |= FIX_M_VID;
  969. writel(reg, &dp_regs->sys_ctl4);
  970. reg = M_VID0_CFG(m_value);
  971. writel(reg, &dp_regs->m_vid0);
  972. reg = M_VID1_CFG(m_value);
  973. writel(reg, &dp_regs->m_vid1);
  974. reg = M_VID2_CFG(m_value);
  975. writel(reg, &dp_regs->m_vid2);
  976. reg = N_VID0_CFG(n_value);
  977. writel(reg, &dp_regs->n_vid0);
  978. reg = N_VID1_CFG(n_value);
  979. writel(reg, &dp_regs->n_vid1);
  980. reg = N_VID2_CFG(n_value);
  981. writel(reg, &dp_regs->n_vid2);
  982. } else {
  983. reg = readl(&dp_regs->sys_ctl4);
  984. reg &= ~FIX_M_VID;
  985. writel(reg, &dp_regs->sys_ctl4);
  986. }
  987. }
  988. void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs,
  989. unsigned int type)
  990. {
  991. unsigned int reg;
  992. reg = readl(&dp_regs->video_ctl10);
  993. reg &= ~FORMAT_SEL;
  994. if (type != VIDEO_TIMING_FROM_CAPTURE)
  995. reg |= FORMAT_SEL;
  996. writel(reg, &dp_regs->video_ctl10);
  997. }
  998. void exynos_dp_enable_video_master(struct exynos_dp *dp_regs,
  999. unsigned int enable)
  1000. {
  1001. unsigned int reg;
  1002. reg = readl(&dp_regs->soc_general_ctl);
  1003. if (enable) {
  1004. reg &= ~VIDEO_MODE_MASK;
  1005. reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
  1006. } else {
  1007. reg &= ~VIDEO_MODE_MASK;
  1008. reg |= VIDEO_MODE_SLAVE_MODE;
  1009. }
  1010. writel(reg, &dp_regs->soc_general_ctl);
  1011. }
  1012. void exynos_dp_start_video(struct exynos_dp *dp_regs)
  1013. {
  1014. unsigned int reg;
  1015. /* Enable Video input and disable Mute */
  1016. reg = readl(&dp_regs->video_ctl1);
  1017. reg |= VIDEO_EN;
  1018. writel(reg, &dp_regs->video_ctl1);
  1019. }
  1020. unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs)
  1021. {
  1022. unsigned int reg;
  1023. /* Update STRM_VALID */
  1024. reg = readl(&dp_regs->sys_ctl3);
  1025. writel(reg, &dp_regs->sys_ctl3);
  1026. reg = readl(&dp_regs->sys_ctl3);
  1027. if (!(reg & STRM_VALID))
  1028. return -EIO;
  1029. return EXYNOS_DP_SUCCESS;
  1030. }