exynos_dp.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics
  4. *
  5. * Author: Donghwa Lee <dh09.lee@samsung.com>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <common.h>
  10. #include <display.h>
  11. #include <fdtdec.h>
  12. #include <log.h>
  13. #include <linux/delay.h>
  14. #include <linux/libfdt.h>
  15. #include <malloc.h>
  16. #include <video_bridge.h>
  17. #include <linux/compat.h>
  18. #include <linux/err.h>
  19. #include <asm/arch/clk.h>
  20. #include <asm/arch/cpu.h>
  21. #include <asm/arch/dp_info.h>
  22. #include <asm/arch/dp.h>
  23. #include <asm/arch/pinmux.h>
  24. #include <asm/arch/power.h>
  25. #include "exynos_dp_lowlevel.h"
  26. DECLARE_GLOBAL_DATA_PTR;
  27. static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
  28. {
  29. disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
  30. disp_info->h_back_porch + disp_info->h_front_porch;
  31. disp_info->v_total = disp_info->v_res + disp_info->v_sync_width +
  32. disp_info->v_back_porch + disp_info->v_front_porch;
  33. return;
  34. }
  35. static int exynos_dp_init_dp(struct exynos_dp *regs)
  36. {
  37. int ret;
  38. exynos_dp_reset(regs);
  39. /* SW defined function Normal operation */
  40. exynos_dp_enable_sw_func(regs, DP_ENABLE);
  41. ret = exynos_dp_init_analog_func(regs);
  42. if (ret != EXYNOS_DP_SUCCESS)
  43. return ret;
  44. exynos_dp_init_hpd(regs);
  45. exynos_dp_init_aux(regs);
  46. return ret;
  47. }
  48. static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  49. {
  50. int i;
  51. unsigned char sum = 0;
  52. for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  53. sum = sum + edid_data[i];
  54. return sum;
  55. }
  56. static unsigned int exynos_dp_read_edid(struct exynos_dp *regs)
  57. {
  58. unsigned char edid[EDID_BLOCK_LENGTH * 2];
  59. unsigned int extend_block = 0;
  60. unsigned char sum;
  61. unsigned char test_vector;
  62. int retval;
  63. /*
  64. * EDID device address is 0x50.
  65. * However, if necessary, you must have set upper address
  66. * into E-EDID in I2C device, 0x30.
  67. */
  68. /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  69. exynos_dp_read_byte_from_i2c(regs, I2C_EDID_DEVICE_ADDR,
  70. EDID_EXTENSION_FLAG, &extend_block);
  71. if (extend_block > 0) {
  72. printf("DP EDID data includes a single extension!\n");
  73. /* Read EDID data */
  74. retval = exynos_dp_read_bytes_from_i2c(regs,
  75. I2C_EDID_DEVICE_ADDR,
  76. EDID_HEADER_PATTERN,
  77. EDID_BLOCK_LENGTH,
  78. &edid[EDID_HEADER_PATTERN]);
  79. if (retval != 0) {
  80. printf("DP EDID Read failed!\n");
  81. return -1;
  82. }
  83. sum = exynos_dp_calc_edid_check_sum(edid);
  84. if (sum != 0) {
  85. printf("DP EDID bad checksum!\n");
  86. return -1;
  87. }
  88. /* Read additional EDID data */
  89. retval = exynos_dp_read_bytes_from_i2c(regs,
  90. I2C_EDID_DEVICE_ADDR,
  91. EDID_BLOCK_LENGTH,
  92. EDID_BLOCK_LENGTH,
  93. &edid[EDID_BLOCK_LENGTH]);
  94. if (retval != 0) {
  95. printf("DP EDID Read failed!\n");
  96. return -1;
  97. }
  98. sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
  99. if (sum != 0) {
  100. printf("DP EDID bad checksum!\n");
  101. return -1;
  102. }
  103. exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
  104. &test_vector);
  105. if (test_vector & DPCD_TEST_EDID_READ) {
  106. exynos_dp_write_byte_to_dpcd(regs,
  107. DPCD_TEST_EDID_CHECKSUM,
  108. edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
  109. exynos_dp_write_byte_to_dpcd(regs,
  110. DPCD_TEST_RESPONSE,
  111. DPCD_TEST_EDID_CHECKSUM_WRITE);
  112. }
  113. } else {
  114. debug("DP EDID data does not include any extensions.\n");
  115. /* Read EDID data */
  116. retval = exynos_dp_read_bytes_from_i2c(regs,
  117. I2C_EDID_DEVICE_ADDR,
  118. EDID_HEADER_PATTERN,
  119. EDID_BLOCK_LENGTH,
  120. &edid[EDID_HEADER_PATTERN]);
  121. if (retval != 0) {
  122. printf("DP EDID Read failed!\n");
  123. return -1;
  124. }
  125. sum = exynos_dp_calc_edid_check_sum(edid);
  126. if (sum != 0) {
  127. printf("DP EDID bad checksum!\n");
  128. return -1;
  129. }
  130. exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
  131. &test_vector);
  132. if (test_vector & DPCD_TEST_EDID_READ) {
  133. exynos_dp_write_byte_to_dpcd(regs,
  134. DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
  135. exynos_dp_write_byte_to_dpcd(regs,
  136. DPCD_TEST_RESPONSE,
  137. DPCD_TEST_EDID_CHECKSUM_WRITE);
  138. }
  139. }
  140. debug("DP EDID Read success!\n");
  141. return 0;
  142. }
  143. static unsigned int exynos_dp_handle_edid(struct exynos_dp *regs,
  144. struct exynos_dp_priv *priv)
  145. {
  146. unsigned char buf[12];
  147. unsigned int ret;
  148. unsigned char temp;
  149. unsigned char retry_cnt;
  150. unsigned char dpcd_rev[16];
  151. unsigned char lane_bw[16];
  152. unsigned char lane_cnt[16];
  153. memset(dpcd_rev, 0, 16);
  154. memset(lane_bw, 0, 16);
  155. memset(lane_cnt, 0, 16);
  156. memset(buf, 0, 12);
  157. retry_cnt = 5;
  158. while (retry_cnt) {
  159. /* Read DPCD 0x0000-0x000b */
  160. ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_DPCD_REV, 12,
  161. buf);
  162. if (ret != EXYNOS_DP_SUCCESS) {
  163. if (retry_cnt == 0) {
  164. printf("DP read_byte_from_dpcd() failed\n");
  165. return ret;
  166. }
  167. retry_cnt--;
  168. } else
  169. break;
  170. }
  171. /* */
  172. temp = buf[DPCD_DPCD_REV];
  173. if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
  174. priv->dpcd_rev = temp;
  175. else {
  176. printf("DP Wrong DPCD Rev : %x\n", temp);
  177. return -ENODEV;
  178. }
  179. temp = buf[DPCD_MAX_LINK_RATE];
  180. if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
  181. priv->lane_bw = temp;
  182. else {
  183. printf("DP Wrong MAX LINK RATE : %x\n", temp);
  184. return -EINVAL;
  185. }
  186. /* Refer VESA Display Port Standard Ver1.1a Page 120 */
  187. if (priv->dpcd_rev == DP_DPCD_REV_11) {
  188. temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
  189. if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
  190. priv->dpcd_efc = 1;
  191. else
  192. priv->dpcd_efc = 0;
  193. } else {
  194. temp = buf[DPCD_MAX_LANE_COUNT];
  195. priv->dpcd_efc = 0;
  196. }
  197. if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
  198. temp == DP_LANE_CNT_4) {
  199. priv->lane_cnt = temp;
  200. } else {
  201. printf("DP Wrong MAX LANE COUNT : %x\n", temp);
  202. return -EINVAL;
  203. }
  204. ret = exynos_dp_read_edid(regs);
  205. if (ret != EXYNOS_DP_SUCCESS) {
  206. printf("DP exynos_dp_read_edid() failed\n");
  207. return -EINVAL;
  208. }
  209. return ret;
  210. }
  211. static void exynos_dp_init_training(struct exynos_dp *regs)
  212. {
  213. /*
  214. * MACRO_RST must be applied after the PLL_LOCK to avoid
  215. * the DP inter pair skew issue for at least 10 us
  216. */
  217. exynos_dp_reset_macro(regs);
  218. /* All DP analog module power up */
  219. exynos_dp_set_analog_power_down(regs, POWER_ALL, 0);
  220. }
  221. static unsigned int exynos_dp_link_start(struct exynos_dp *regs,
  222. struct exynos_dp_priv *priv)
  223. {
  224. unsigned char buf[5];
  225. unsigned int ret = 0;
  226. debug("DP: %s was called\n", __func__);
  227. priv->lt_info.lt_status = DP_LT_CR;
  228. priv->lt_info.ep_loop = 0;
  229. priv->lt_info.cr_loop[0] = 0;
  230. priv->lt_info.cr_loop[1] = 0;
  231. priv->lt_info.cr_loop[2] = 0;
  232. priv->lt_info.cr_loop[3] = 0;
  233. /* Set sink to D0 (Sink Not Ready) mode. */
  234. ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_SINK_POWER_STATE,
  235. DPCD_SET_POWER_STATE_D0);
  236. if (ret != EXYNOS_DP_SUCCESS) {
  237. printf("DP write_dpcd_byte failed\n");
  238. return ret;
  239. }
  240. /* Set link rate and count as you want to establish */
  241. exynos_dp_set_link_bandwidth(regs, priv->lane_bw);
  242. exynos_dp_set_lane_count(regs, priv->lane_cnt);
  243. /* Setup RX configuration */
  244. buf[0] = priv->lane_bw;
  245. buf[1] = priv->lane_cnt;
  246. ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_LINK_BW_SET, 2, buf);
  247. if (ret != EXYNOS_DP_SUCCESS) {
  248. printf("DP write_dpcd_byte failed\n");
  249. return ret;
  250. }
  251. exynos_dp_set_lane_pre_emphasis(regs, PRE_EMPHASIS_LEVEL_0,
  252. priv->lane_cnt);
  253. /* Set training pattern 1 */
  254. exynos_dp_set_training_pattern(regs, TRAINING_PTN1);
  255. /* Set RX training pattern */
  256. buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
  257. buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
  258. DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
  259. buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
  260. DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
  261. buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
  262. DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
  263. buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
  264. DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
  265. ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
  266. 5, buf);
  267. if (ret != EXYNOS_DP_SUCCESS) {
  268. printf("DP write_dpcd_byte failed\n");
  269. return ret;
  270. }
  271. return ret;
  272. }
  273. static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
  274. {
  275. unsigned int ret;
  276. exynos_dp_set_training_pattern(regs, DP_NONE);
  277. ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
  278. DPCD_TRAINING_PATTERN_DISABLED);
  279. if (ret != EXYNOS_DP_SUCCESS) {
  280. printf("DP request_link_training_req failed\n");
  281. return -EAGAIN;
  282. }
  283. return ret;
  284. }
  285. static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
  286. struct exynos_dp *regs, unsigned char enable)
  287. {
  288. unsigned char data;
  289. unsigned int ret;
  290. ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
  291. &data);
  292. if (ret != EXYNOS_DP_SUCCESS) {
  293. printf("DP read_from_dpcd failed\n");
  294. return -EAGAIN;
  295. }
  296. if (enable)
  297. data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data);
  298. else
  299. data = DPCD_LN_COUNT_SET(data);
  300. ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_LANE_COUNT_SET, data);
  301. if (ret != EXYNOS_DP_SUCCESS) {
  302. printf("DP write_to_dpcd failed\n");
  303. return -EAGAIN;
  304. }
  305. return ret;
  306. }
  307. static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
  308. unsigned char enhance_mode)
  309. {
  310. unsigned int ret;
  311. ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
  312. if (ret != EXYNOS_DP_SUCCESS) {
  313. printf("DP rx_enhance_mode failed\n");
  314. return -EAGAIN;
  315. }
  316. exynos_dp_enable_enhanced_mode(regs, enhance_mode);
  317. return ret;
  318. }
  319. static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs,
  320. struct exynos_dp_priv *priv,
  321. unsigned char *status)
  322. {
  323. unsigned int ret, i;
  324. unsigned char buf[2];
  325. unsigned char lane_stat[DP_LANE_CNT_4] = {0,};
  326. unsigned char shift_val[DP_LANE_CNT_4] = {0,};
  327. shift_val[0] = 0;
  328. shift_val[1] = 4;
  329. shift_val[2] = 0;
  330. shift_val[3] = 4;
  331. ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_LANE0_1_STATUS, 2,
  332. buf);
  333. if (ret != EXYNOS_DP_SUCCESS) {
  334. printf("DP read lane status failed\n");
  335. return ret;
  336. }
  337. for (i = 0; i < priv->lane_cnt; i++) {
  338. lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
  339. if (lane_stat[0] != lane_stat[i]) {
  340. printf("Wrong lane status\n");
  341. return -EINVAL;
  342. }
  343. }
  344. *status = lane_stat[0];
  345. return ret;
  346. }
  347. static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
  348. unsigned char lane_num, unsigned char *sw, unsigned char *em)
  349. {
  350. unsigned int ret;
  351. unsigned char buf;
  352. unsigned int dpcd_addr;
  353. unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4};
  354. /* lane_num value is used as array index, so this range 0 ~ 3 */
  355. dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
  356. ret = exynos_dp_read_byte_from_dpcd(regs, dpcd_addr, &buf);
  357. if (ret != EXYNOS_DP_SUCCESS) {
  358. printf("DP read adjust request failed\n");
  359. return -EAGAIN;
  360. }
  361. *sw = ((buf >> shift_val[lane_num]) & 0x03);
  362. *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2;
  363. return ret;
  364. }
  365. static int exynos_dp_equalizer_err_link(struct exynos_dp *regs,
  366. struct exynos_dp_priv *priv)
  367. {
  368. int ret;
  369. ret = exynos_dp_training_pattern_dis(regs);
  370. if (ret != EXYNOS_DP_SUCCESS) {
  371. printf("DP training_pattern_disable() failed\n");
  372. priv->lt_info.lt_status = DP_LT_FAIL;
  373. }
  374. ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
  375. if (ret != EXYNOS_DP_SUCCESS) {
  376. printf("DP set_enhanced_mode() failed\n");
  377. priv->lt_info.lt_status = DP_LT_FAIL;
  378. }
  379. return ret;
  380. }
  381. static int exynos_dp_reduce_link_rate(struct exynos_dp *regs,
  382. struct exynos_dp_priv *priv)
  383. {
  384. int ret;
  385. if (priv->lane_bw == DP_LANE_BW_2_70) {
  386. priv->lane_bw = DP_LANE_BW_1_62;
  387. printf("DP Change lane bw to 1.62Gbps\n");
  388. priv->lt_info.lt_status = DP_LT_START;
  389. ret = EXYNOS_DP_SUCCESS;
  390. } else {
  391. ret = exynos_dp_training_pattern_dis(regs);
  392. if (ret != EXYNOS_DP_SUCCESS)
  393. printf("DP training_patter_disable() failed\n");
  394. ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
  395. if (ret != EXYNOS_DP_SUCCESS)
  396. printf("DP set_enhanced_mode() failed\n");
  397. priv->lt_info.lt_status = DP_LT_FAIL;
  398. }
  399. return ret;
  400. }
  401. static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
  402. struct exynos_dp_priv *priv)
  403. {
  404. unsigned int ret;
  405. unsigned char lane_stat;
  406. unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, };
  407. unsigned int i;
  408. unsigned char adj_req_sw;
  409. unsigned char adj_req_em;
  410. unsigned char buf[5];
  411. debug("DP: %s was called\n", __func__);
  412. mdelay(1);
  413. ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
  414. if (ret != EXYNOS_DP_SUCCESS) {
  415. printf("DP read lane status failed\n");
  416. priv->lt_info.lt_status = DP_LT_FAIL;
  417. return ret;
  418. }
  419. if (lane_stat & DP_LANE_STAT_CR_DONE) {
  420. debug("DP clock Recovery training succeed\n");
  421. exynos_dp_set_training_pattern(regs, TRAINING_PTN2);
  422. for (i = 0; i < priv->lane_cnt; i++) {
  423. ret = exynos_dp_read_dpcd_adj_req(regs, i,
  424. &adj_req_sw, &adj_req_em);
  425. if (ret != EXYNOS_DP_SUCCESS) {
  426. priv->lt_info.lt_status = DP_LT_FAIL;
  427. return ret;
  428. }
  429. lt_ctl_val[i] = 0;
  430. lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
  431. if ((adj_req_sw == VOLTAGE_LEVEL_3)
  432. || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
  433. lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
  434. MAX_PRE_EMPHASIS_REACH_3;
  435. }
  436. exynos_dp_set_lanex_pre_emphasis(regs,
  437. lt_ctl_val[i], i);
  438. }
  439. buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
  440. buf[1] = lt_ctl_val[0];
  441. buf[2] = lt_ctl_val[1];
  442. buf[3] = lt_ctl_val[2];
  443. buf[4] = lt_ctl_val[3];
  444. ret = exynos_dp_write_bytes_to_dpcd(regs,
  445. DPCD_TRAINING_PATTERN_SET, 5, buf);
  446. if (ret != EXYNOS_DP_SUCCESS) {
  447. printf("DP write training pattern1 failed\n");
  448. priv->lt_info.lt_status = DP_LT_FAIL;
  449. return ret;
  450. } else
  451. priv->lt_info.lt_status = DP_LT_ET;
  452. } else {
  453. for (i = 0; i < priv->lane_cnt; i++) {
  454. lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(
  455. regs, i);
  456. ret = exynos_dp_read_dpcd_adj_req(regs, i,
  457. &adj_req_sw, &adj_req_em);
  458. if (ret != EXYNOS_DP_SUCCESS) {
  459. printf("DP read adj req failed\n");
  460. priv->lt_info.lt_status = DP_LT_FAIL;
  461. return ret;
  462. }
  463. if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
  464. (adj_req_em == PRE_EMPHASIS_LEVEL_3))
  465. ret = exynos_dp_reduce_link_rate(regs,
  466. priv);
  467. if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
  468. adj_req_sw) &&
  469. (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
  470. adj_req_em)) {
  471. priv->lt_info.cr_loop[i]++;
  472. if (priv->lt_info.cr_loop[i] == MAX_CR_LOOP)
  473. ret = exynos_dp_reduce_link_rate(
  474. regs, priv);
  475. }
  476. lt_ctl_val[i] = 0;
  477. lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
  478. if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
  479. (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
  480. lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
  481. MAX_PRE_EMPHASIS_REACH_3;
  482. }
  483. exynos_dp_set_lanex_pre_emphasis(regs,
  484. lt_ctl_val[i], i);
  485. }
  486. ret = exynos_dp_write_bytes_to_dpcd(regs,
  487. DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
  488. if (ret != EXYNOS_DP_SUCCESS) {
  489. printf("DP write training pattern2 failed\n");
  490. priv->lt_info.lt_status = DP_LT_FAIL;
  491. return ret;
  492. }
  493. }
  494. return ret;
  495. }
  496. static unsigned int exynos_dp_process_equalizer_training(
  497. struct exynos_dp *regs, struct exynos_dp_priv *priv)
  498. {
  499. unsigned int ret;
  500. unsigned char lane_stat, adj_req_sw, adj_req_em, i;
  501. unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,};
  502. unsigned char interlane_aligned = 0;
  503. unsigned char f_bw;
  504. unsigned char f_lane_cnt;
  505. unsigned char sink_stat;
  506. mdelay(1);
  507. ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
  508. if (ret != EXYNOS_DP_SUCCESS) {
  509. printf("DP read lane status failed\n");
  510. priv->lt_info.lt_status = DP_LT_FAIL;
  511. return ret;
  512. }
  513. debug("DP lane stat : %x\n", lane_stat);
  514. if (lane_stat & DP_LANE_STAT_CR_DONE) {
  515. ret = exynos_dp_read_byte_from_dpcd(regs,
  516. DPCD_LN_ALIGN_UPDATED,
  517. &sink_stat);
  518. if (ret != EXYNOS_DP_SUCCESS) {
  519. priv->lt_info.lt_status = DP_LT_FAIL;
  520. return ret;
  521. }
  522. interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
  523. for (i = 0; i < priv->lane_cnt; i++) {
  524. ret = exynos_dp_read_dpcd_adj_req(regs, i,
  525. &adj_req_sw, &adj_req_em);
  526. if (ret != EXYNOS_DP_SUCCESS) {
  527. printf("DP read adj req 1 failed\n");
  528. priv->lt_info.lt_status = DP_LT_FAIL;
  529. return ret;
  530. }
  531. lt_ctl_val[i] = 0;
  532. lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw;
  533. if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
  534. (adj_req_em == PRE_EMPHASIS_LEVEL_3)) {
  535. lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3;
  536. lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3;
  537. }
  538. }
  539. if (((lane_stat&DP_LANE_STAT_CE_DONE) &&
  540. (lane_stat&DP_LANE_STAT_SYM_LOCK))
  541. && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
  542. debug("DP Equalizer training succeed\n");
  543. f_bw = exynos_dp_get_link_bandwidth(regs);
  544. f_lane_cnt = exynos_dp_get_lane_count(regs);
  545. debug("DP final BandWidth : %x\n", f_bw);
  546. debug("DP final Lane Count : %x\n", f_lane_cnt);
  547. priv->lt_info.lt_status = DP_LT_FINISHED;
  548. exynos_dp_equalizer_err_link(regs, priv);
  549. } else {
  550. priv->lt_info.ep_loop++;
  551. if (priv->lt_info.ep_loop > MAX_EQ_LOOP) {
  552. if (priv->lane_bw == DP_LANE_BW_2_70) {
  553. ret = exynos_dp_reduce_link_rate(
  554. regs, priv);
  555. } else {
  556. priv->lt_info.lt_status =
  557. DP_LT_FAIL;
  558. exynos_dp_equalizer_err_link(regs,
  559. priv);
  560. }
  561. } else {
  562. for (i = 0; i < priv->lane_cnt; i++)
  563. exynos_dp_set_lanex_pre_emphasis(
  564. regs, lt_ctl_val[i], i);
  565. ret = exynos_dp_write_bytes_to_dpcd(regs,
  566. DPCD_TRAINING_LANE0_SET,
  567. 4, lt_ctl_val);
  568. if (ret != EXYNOS_DP_SUCCESS) {
  569. printf("DP set lt pattern failed\n");
  570. priv->lt_info.lt_status =
  571. DP_LT_FAIL;
  572. exynos_dp_equalizer_err_link(regs,
  573. priv);
  574. }
  575. }
  576. }
  577. } else if (priv->lane_bw == DP_LANE_BW_2_70) {
  578. ret = exynos_dp_reduce_link_rate(regs, priv);
  579. } else {
  580. priv->lt_info.lt_status = DP_LT_FAIL;
  581. exynos_dp_equalizer_err_link(regs, priv);
  582. }
  583. return ret;
  584. }
  585. static unsigned int exynos_dp_sw_link_training(struct exynos_dp *regs,
  586. struct exynos_dp_priv *priv)
  587. {
  588. unsigned int ret = 0;
  589. int training_finished;
  590. /* Turn off unnecessary lane */
  591. if (priv->lane_cnt == 1)
  592. exynos_dp_set_analog_power_down(regs, CH1_BLOCK, 1);
  593. training_finished = 0;
  594. priv->lt_info.lt_status = DP_LT_START;
  595. /* Process here */
  596. while (!training_finished) {
  597. switch (priv->lt_info.lt_status) {
  598. case DP_LT_START:
  599. ret = exynos_dp_link_start(regs, priv);
  600. if (ret != EXYNOS_DP_SUCCESS) {
  601. printf("DP LT:link start failed\n");
  602. return ret;
  603. }
  604. break;
  605. case DP_LT_CR:
  606. ret = exynos_dp_process_clock_recovery(regs,
  607. priv);
  608. if (ret != EXYNOS_DP_SUCCESS) {
  609. printf("DP LT:clock recovery failed\n");
  610. return ret;
  611. }
  612. break;
  613. case DP_LT_ET:
  614. ret = exynos_dp_process_equalizer_training(regs,
  615. priv);
  616. if (ret != EXYNOS_DP_SUCCESS) {
  617. printf("DP LT:equalizer training failed\n");
  618. return ret;
  619. }
  620. break;
  621. case DP_LT_FINISHED:
  622. training_finished = 1;
  623. break;
  624. case DP_LT_FAIL:
  625. return -1;
  626. }
  627. }
  628. return ret;
  629. }
  630. static unsigned int exynos_dp_set_link_train(struct exynos_dp *regs,
  631. struct exynos_dp_priv *priv)
  632. {
  633. unsigned int ret;
  634. exynos_dp_init_training(regs);
  635. ret = exynos_dp_sw_link_training(regs, priv);
  636. if (ret != EXYNOS_DP_SUCCESS)
  637. printf("DP dp_sw_link_training() failed\n");
  638. return ret;
  639. }
  640. static void exynos_dp_enable_scramble(struct exynos_dp *regs,
  641. unsigned int enable)
  642. {
  643. unsigned char data;
  644. if (enable) {
  645. exynos_dp_enable_scrambling(regs, DP_ENABLE);
  646. exynos_dp_read_byte_from_dpcd(regs,
  647. DPCD_TRAINING_PATTERN_SET, &data);
  648. exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
  649. (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
  650. } else {
  651. exynos_dp_enable_scrambling(regs, DP_DISABLE);
  652. exynos_dp_read_byte_from_dpcd(regs,
  653. DPCD_TRAINING_PATTERN_SET, &data);
  654. exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
  655. (u8)(data | DPCD_SCRAMBLING_DISABLED));
  656. }
  657. }
  658. static unsigned int exynos_dp_config_video(struct exynos_dp *regs,
  659. struct exynos_dp_priv *priv)
  660. {
  661. unsigned int ret = 0;
  662. unsigned int retry_cnt;
  663. mdelay(1);
  664. if (priv->video_info.master_mode) {
  665. printf("DP does not support master mode\n");
  666. return -ENODEV;
  667. } else {
  668. /* debug slave */
  669. exynos_dp_config_video_slave_mode(regs,
  670. &priv->video_info);
  671. }
  672. exynos_dp_set_video_color_format(regs, &priv->video_info);
  673. if (priv->video_info.bist_mode) {
  674. if (exynos_dp_config_video_bist(regs, priv) != 0)
  675. return -1;
  676. }
  677. ret = exynos_dp_get_pll_lock_status(regs);
  678. if (ret != PLL_LOCKED) {
  679. printf("DP PLL is not locked yet\n");
  680. return -EIO;
  681. }
  682. if (priv->video_info.master_mode == 0) {
  683. retry_cnt = 10;
  684. while (retry_cnt) {
  685. ret = exynos_dp_is_slave_video_stream_clock_on(regs);
  686. if (ret != EXYNOS_DP_SUCCESS) {
  687. if (retry_cnt == 0) {
  688. printf("DP stream_clock_on failed\n");
  689. return ret;
  690. }
  691. retry_cnt--;
  692. mdelay(1);
  693. } else
  694. break;
  695. }
  696. }
  697. /* Set to use the register calculated M/N video */
  698. exynos_dp_set_video_cr_mn(regs, CALCULATED_M, 0, 0);
  699. /* For video bist, Video timing must be generated by register */
  700. exynos_dp_set_video_timing_mode(regs, VIDEO_TIMING_FROM_CAPTURE);
  701. /* Enable video bist */
  702. if (priv->video_info.bist_pattern != COLOR_RAMP &&
  703. priv->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
  704. priv->video_info.bist_pattern != COLOR_SQUARE)
  705. exynos_dp_enable_video_bist(regs,
  706. priv->video_info.bist_mode);
  707. else
  708. exynos_dp_enable_video_bist(regs, DP_DISABLE);
  709. /* Disable video mute */
  710. exynos_dp_enable_video_mute(regs, DP_DISABLE);
  711. /* Configure video Master or Slave mode */
  712. exynos_dp_enable_video_master(regs,
  713. priv->video_info.master_mode);
  714. /* Enable video */
  715. exynos_dp_start_video(regs);
  716. if (priv->video_info.master_mode == 0) {
  717. retry_cnt = 100;
  718. while (retry_cnt) {
  719. ret = exynos_dp_is_video_stream_on(regs);
  720. if (ret != EXYNOS_DP_SUCCESS) {
  721. if (retry_cnt == 0) {
  722. printf("DP Timeout of video stream\n");
  723. return ret;
  724. }
  725. retry_cnt--;
  726. mdelay(5);
  727. } else
  728. break;
  729. }
  730. }
  731. return ret;
  732. }
  733. static int exynos_dp_ofdata_to_platdata(struct udevice *dev)
  734. {
  735. struct exynos_dp_priv *priv = dev_get_priv(dev);
  736. const void *blob = gd->fdt_blob;
  737. unsigned int node = dev_of_offset(dev);
  738. fdt_addr_t addr;
  739. addr = dev_read_addr(dev);
  740. if (addr == FDT_ADDR_T_NONE) {
  741. debug("Can't get the DP base address\n");
  742. return -EINVAL;
  743. }
  744. priv->regs = (struct exynos_dp *)addr;
  745. priv->disp_info.h_res = fdtdec_get_int(blob, node,
  746. "samsung,h-res", 0);
  747. priv->disp_info.h_sync_width = fdtdec_get_int(blob, node,
  748. "samsung,h-sync-width", 0);
  749. priv->disp_info.h_back_porch = fdtdec_get_int(blob, node,
  750. "samsung,h-back-porch", 0);
  751. priv->disp_info.h_front_porch = fdtdec_get_int(blob, node,
  752. "samsung,h-front-porch", 0);
  753. priv->disp_info.v_res = fdtdec_get_int(blob, node,
  754. "samsung,v-res", 0);
  755. priv->disp_info.v_sync_width = fdtdec_get_int(blob, node,
  756. "samsung,v-sync-width", 0);
  757. priv->disp_info.v_back_porch = fdtdec_get_int(blob, node,
  758. "samsung,v-back-porch", 0);
  759. priv->disp_info.v_front_porch = fdtdec_get_int(blob, node,
  760. "samsung,v-front-porch", 0);
  761. priv->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
  762. "samsung,v-sync-rate", 0);
  763. priv->lt_info.lt_status = fdtdec_get_int(blob, node,
  764. "samsung,lt-status", 0);
  765. priv->video_info.master_mode = fdtdec_get_int(blob, node,
  766. "samsung,master-mode", 0);
  767. priv->video_info.bist_mode = fdtdec_get_int(blob, node,
  768. "samsung,bist-mode", 0);
  769. priv->video_info.bist_pattern = fdtdec_get_int(blob, node,
  770. "samsung,bist-pattern", 0);
  771. priv->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
  772. "samsung,h-sync-polarity", 0);
  773. priv->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
  774. "samsung,v-sync-polarity", 0);
  775. priv->video_info.interlaced = fdtdec_get_int(blob, node,
  776. "samsung,interlaced", 0);
  777. priv->video_info.color_space = fdtdec_get_int(blob, node,
  778. "samsung,color-space", 0);
  779. priv->video_info.dynamic_range = fdtdec_get_int(blob, node,
  780. "samsung,dynamic-range", 0);
  781. priv->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
  782. "samsung,ycbcr-coeff", 0);
  783. priv->video_info.color_depth = fdtdec_get_int(blob, node,
  784. "samsung,color-depth", 0);
  785. return 0;
  786. }
  787. static int exynos_dp_bridge_init(struct udevice *dev)
  788. {
  789. const int max_tries = 10;
  790. int num_tries;
  791. int ret;
  792. debug("%s\n", __func__);
  793. ret = video_bridge_attach(dev);
  794. if (ret) {
  795. debug("video bridge init failed: %d\n", ret);
  796. return ret;
  797. }
  798. /*
  799. * We need to wait for 90ms after bringing up the bridge since there
  800. * is a phantom "high" on the HPD chip during its bootup. The phantom
  801. * high comes within 7ms of de-asserting PD and persists for at least
  802. * 15ms. The real high comes roughly 50ms after PD is de-asserted. The
  803. * phantom high makes it hard for us to know when the NXP chip is up.
  804. */
  805. mdelay(90);
  806. for (num_tries = 0; num_tries < max_tries; num_tries++) {
  807. /* Check HPD. If it's high, or we don't have it, all is well */
  808. ret = video_bridge_check_attached(dev);
  809. if (!ret || ret == -ENOENT)
  810. return 0;
  811. debug("%s: eDP bridge failed to come up; try %d of %d\n",
  812. __func__, num_tries, max_tries);
  813. }
  814. /* Immediately go into bridge reset if the hp line is not high */
  815. return -EIO;
  816. }
  817. static int exynos_dp_bridge_setup(const void *blob)
  818. {
  819. const int max_tries = 2;
  820. int num_tries;
  821. struct udevice *dev;
  822. int ret;
  823. /* Configure I2C registers for Parade bridge */
  824. ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
  825. if (ret) {
  826. debug("video bridge init failed: %d\n", ret);
  827. return ret;
  828. }
  829. if (strncmp(dev->driver->name, "parade", 6)) {
  830. /* Mux HPHPD to the special hotplug detect mode */
  831. exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
  832. }
  833. for (num_tries = 0; num_tries < max_tries; num_tries++) {
  834. ret = exynos_dp_bridge_init(dev);
  835. if (!ret)
  836. return 0;
  837. if (num_tries == max_tries - 1)
  838. break;
  839. /*
  840. * If we're here, the bridge chip failed to initialise.
  841. * Power down the bridge in an attempt to reset.
  842. */
  843. video_bridge_set_active(dev, false);
  844. /*
  845. * Arbitrarily wait 300ms here with DP_N low. Don't know for
  846. * sure how long we should wait, but we're being paranoid.
  847. */
  848. mdelay(300);
  849. }
  850. return ret;
  851. }
  852. int exynos_dp_enable(struct udevice *dev, int panel_bpp,
  853. const struct display_timing *timing)
  854. {
  855. struct exynos_dp_priv *priv = dev_get_priv(dev);
  856. struct exynos_dp *regs = priv->regs;
  857. unsigned int ret;
  858. debug("%s: start\n", __func__);
  859. exynos_dp_disp_info(&priv->disp_info);
  860. ret = exynos_dp_bridge_setup(gd->fdt_blob);
  861. if (ret && ret != -ENODEV)
  862. printf("LCD bridge failed to enable: %d\n", ret);
  863. exynos_dp_phy_ctrl(1);
  864. ret = exynos_dp_init_dp(regs);
  865. if (ret != EXYNOS_DP_SUCCESS) {
  866. printf("DP exynos_dp_init_dp() failed\n");
  867. return ret;
  868. }
  869. ret = exynos_dp_handle_edid(regs, priv);
  870. if (ret != EXYNOS_DP_SUCCESS) {
  871. printf("EDP handle_edid fail\n");
  872. return ret;
  873. }
  874. ret = exynos_dp_set_link_train(regs, priv);
  875. if (ret != EXYNOS_DP_SUCCESS) {
  876. printf("DP link training fail\n");
  877. return ret;
  878. }
  879. exynos_dp_enable_scramble(regs, DP_ENABLE);
  880. exynos_dp_enable_rx_to_enhanced_mode(regs, DP_ENABLE);
  881. exynos_dp_enable_enhanced_mode(regs, DP_ENABLE);
  882. exynos_dp_set_link_bandwidth(regs, priv->lane_bw);
  883. exynos_dp_set_lane_count(regs, priv->lane_cnt);
  884. exynos_dp_init_video(regs);
  885. ret = exynos_dp_config_video(regs, priv);
  886. if (ret != EXYNOS_DP_SUCCESS) {
  887. printf("Exynos DP init failed\n");
  888. return ret;
  889. }
  890. debug("Exynos DP init done\n");
  891. return ret;
  892. }
  893. static const struct dm_display_ops exynos_dp_ops = {
  894. .enable = exynos_dp_enable,
  895. };
  896. static const struct udevice_id exynos_dp_ids[] = {
  897. { .compatible = "samsung,exynos5-dp" },
  898. { }
  899. };
  900. U_BOOT_DRIVER(exynos_dp) = {
  901. .name = "exynos_dp",
  902. .id = UCLASS_DISPLAY,
  903. .of_match = exynos_dp_ids,
  904. .ops = &exynos_dp_ops,
  905. .ofdata_to_platdata = exynos_dp_ofdata_to_platdata,
  906. .priv_auto_alloc_size = sizeof(struct exynos_dp_priv),
  907. };