atmel_lcdfb.c 8.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for AT91/AT32 LCD Controller
  4. *
  5. * Copyright (C) 2007 Atmel Corporation
  6. */
  7. #include <common.h>
  8. #include <atmel_lcd.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <log.h>
  12. #include <part.h>
  13. #include <video.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/gpio.h>
  16. #include <asm/arch/clk.h>
  17. #include <lcd.h>
  18. #include <bmp_layout.h>
  19. #include <atmel_lcdc.h>
  20. #include <linux/delay.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #ifdef CONFIG_DM_VIDEO
  23. enum {
  24. /* Maximum LCD size we support */
  25. LCD_MAX_WIDTH = 1366,
  26. LCD_MAX_HEIGHT = 768,
  27. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  28. };
  29. #endif
  30. struct atmel_fb_priv {
  31. struct display_timing timing;
  32. };
  33. /* configurable parameters */
  34. #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
  35. #define ATMEL_LCDC_DMA_BURST_LEN 8
  36. #ifndef ATMEL_LCDC_GUARD_TIME
  37. #define ATMEL_LCDC_GUARD_TIME 1
  38. #endif
  39. #if defined(CONFIG_AT91SAM9263)
  40. #define ATMEL_LCDC_FIFO_SIZE 2048
  41. #else
  42. #define ATMEL_LCDC_FIFO_SIZE 512
  43. #endif
  44. #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
  45. #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
  46. #ifndef CONFIG_DM_VIDEO
  47. ushort *configuration_get_cmap(void)
  48. {
  49. return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  50. }
  51. #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
  52. void fb_put_word(uchar **fb, uchar **from)
  53. {
  54. *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
  55. *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
  56. *from += 2;
  57. }
  58. #endif
  59. #ifdef CONFIG_LCD_LOGO
  60. #include <bmp_logo.h>
  61. void lcd_logo_set_cmap(void)
  62. {
  63. int i;
  64. uint lut_entry;
  65. ushort colreg;
  66. uint *cmap = (uint *)configuration_get_cmap();
  67. for (i = 0; i < BMP_LOGO_COLORS; ++i) {
  68. colreg = bmp_logo_palette[i];
  69. #ifdef CONFIG_ATMEL_LCD_BGR555
  70. lut_entry = ((colreg & 0x000F) << 11) |
  71. ((colreg & 0x00F0) << 2) |
  72. ((colreg & 0x0F00) >> 7);
  73. #else
  74. lut_entry = ((colreg & 0x000F) << 1) |
  75. ((colreg & 0x00F0) << 3) |
  76. ((colreg & 0x0F00) << 4);
  77. #endif
  78. *(cmap + BMP_LOGO_OFFSET) = lut_entry;
  79. cmap++;
  80. }
  81. }
  82. #endif
  83. void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  84. {
  85. #if defined(CONFIG_ATMEL_LCD_BGR555)
  86. lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  87. (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
  88. #else
  89. lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  90. (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
  91. #endif
  92. }
  93. void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
  94. {
  95. int i;
  96. for (i = 0; i < colors; ++i) {
  97. struct bmp_color_table_entry cte = bmp->color_table[i];
  98. lcd_setcolreg(i, cte.red, cte.green, cte.blue);
  99. }
  100. }
  101. #endif
  102. static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
  103. bool tft, bool cont_pol_low, ulong lcdbase)
  104. {
  105. unsigned long value;
  106. void *reg = (void *)addr;
  107. /* Turn off the LCD controller and the DMA controller */
  108. lcdc_writel(reg, ATMEL_LCDC_PWRCON,
  109. ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
  110. /* Wait for the LCDC core to become idle */
  111. while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
  112. udelay(10);
  113. lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
  114. /* Reset LCDC DMA */
  115. lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
  116. /* ...set frame size and burst length = 8 words (?) */
  117. value = (timing->hactive.typ * timing->vactive.typ *
  118. (1 << bpix)) / 32;
  119. value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
  120. lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
  121. /* Set pixel clock */
  122. value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
  123. if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
  124. value++;
  125. value = (value / 2) - 1;
  126. if (!value) {
  127. lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
  128. } else
  129. lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
  130. value << ATMEL_LCDC_CLKVAL_OFFSET);
  131. /* Initialize control register 2 */
  132. value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
  133. if (tft)
  134. value |= ATMEL_LCDC_DISTYPE_TFT;
  135. if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
  136. value |= ATMEL_LCDC_INVLINE_INVERTED;
  137. if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
  138. value |= ATMEL_LCDC_INVFRAME_INVERTED;
  139. value |= bpix << 5;
  140. lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
  141. /* Vertical timing */
  142. value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
  143. value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
  144. value |= timing->vfront_porch.typ;
  145. /* Magic! (Datasheet says "Bit 31 must be written to 1") */
  146. value |= 1U << 31;
  147. lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
  148. /* Horizontal timing */
  149. value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
  150. value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
  151. value |= (timing->hback_porch.typ - 1);
  152. lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
  153. /* Display size */
  154. value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
  155. value |= timing->vactive.typ - 1;
  156. lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
  157. /* FIFO Threshold: Use formula from data sheet */
  158. value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
  159. lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
  160. /* Toggle LCD_MODE every frame */
  161. lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
  162. /* Disable all interrupts */
  163. lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
  164. /* Set contrast */
  165. value = ATMEL_LCDC_PS_DIV8 |
  166. ATMEL_LCDC_ENA_PWMENABLE;
  167. if (!cont_pol_low)
  168. value |= ATMEL_LCDC_POL_POSITIVE;
  169. lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
  170. lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
  171. /* Set framebuffer DMA base address and pixel offset */
  172. lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
  173. lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
  174. lcdc_writel(reg, ATMEL_LCDC_PWRCON,
  175. (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
  176. }
  177. #ifndef CONFIG_DM_VIDEO
  178. void lcd_ctrl_init(void *lcdbase)
  179. {
  180. struct display_timing timing;
  181. timing.flags = 0;
  182. if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
  183. timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
  184. if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
  185. timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
  186. timing.pixelclock.typ = panel_info.vl_clk;
  187. timing.hactive.typ = panel_info.vl_col;
  188. timing.hfront_porch.typ = panel_info.vl_right_margin;
  189. timing.hback_porch.typ = panel_info.vl_left_margin;
  190. timing.hsync_len.typ = panel_info.vl_hsync_len;
  191. timing.vactive.typ = panel_info.vl_row;
  192. timing.vfront_porch.typ = panel_info.vl_clk;
  193. timing.vback_porch.typ = panel_info.vl_clk;
  194. timing.vsync_len.typ = panel_info.vl_clk;
  195. atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
  196. panel_info.vl_tft, panel_info.vl_cont_pol_low,
  197. (ulong)lcdbase);
  198. }
  199. ulong calc_fbsize(void)
  200. {
  201. return ((panel_info.vl_col * panel_info.vl_row *
  202. NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
  203. }
  204. #endif
  205. #ifdef CONFIG_DM_VIDEO
  206. static int atmel_fb_lcd_probe(struct udevice *dev)
  207. {
  208. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  209. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  210. struct atmel_fb_priv *priv = dev_get_priv(dev);
  211. struct display_timing *timing = &priv->timing;
  212. /*
  213. * For now some values are hard-coded. We could use the device tree
  214. * bindings in simple-framebuffer.txt to specify the format/bpp and
  215. * some Atmel-specific binding for tft and cont_pol_low.
  216. */
  217. atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
  218. uc_plat->base);
  219. uc_priv->xsize = timing->hactive.typ;
  220. uc_priv->ysize = timing->vactive.typ;
  221. uc_priv->bpix = VIDEO_BPP16;
  222. video_set_flush_dcache(dev, true);
  223. debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
  224. uc_plat->size, uc_priv->xsize, uc_priv->ysize);
  225. return 0;
  226. }
  227. static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
  228. {
  229. struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
  230. struct atmel_fb_priv *priv = dev_get_priv(dev);
  231. struct display_timing *timing = &priv->timing;
  232. const void *blob = gd->fdt_blob;
  233. if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
  234. plat->timing_index, timing)) {
  235. debug("%s: Failed to decode display timing\n", __func__);
  236. return -EINVAL;
  237. }
  238. return 0;
  239. }
  240. static int atmel_fb_lcd_bind(struct udevice *dev)
  241. {
  242. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  243. uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  244. (1 << VIDEO_BPP16) / 8;
  245. debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  246. return 0;
  247. }
  248. static const struct udevice_id atmel_fb_lcd_ids[] = {
  249. { .compatible = "atmel,at91sam9g45-lcdc" },
  250. { }
  251. };
  252. U_BOOT_DRIVER(atmel_fb) = {
  253. .name = "atmel_fb",
  254. .id = UCLASS_VIDEO,
  255. .of_match = atmel_fb_lcd_ids,
  256. .bind = atmel_fb_lcd_bind,
  257. .ofdata_to_platdata = atmel_fb_ofdata_to_platdata,
  258. .probe = atmel_fb_lcd_probe,
  259. .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
  260. .priv_auto_alloc_size = sizeof(struct atmel_fb_priv),
  261. };
  262. #endif