atmel_hlcdfb.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for AT91/AT32 MULTI LAYER LCD Controller
  4. *
  5. * Copyright (C) 2012 Atmel Corporation
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <part.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/gpio.h>
  14. #include <asm/arch/clk.h>
  15. #include <clk.h>
  16. #include <dm.h>
  17. #include <fdtdec.h>
  18. #include <lcd.h>
  19. #include <video.h>
  20. #include <wait_bit.h>
  21. #include <atmel_hlcdc.h>
  22. #include <linux/bug.h>
  23. #if defined(CONFIG_LCD_LOGO)
  24. #include <bmp_logo.h>
  25. #endif
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #ifndef CONFIG_DM_VIDEO
  28. /* configurable parameters */
  29. #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
  30. #define ATMEL_LCDC_DMA_BURST_LEN 8
  31. #ifndef ATMEL_LCDC_GUARD_TIME
  32. #define ATMEL_LCDC_GUARD_TIME 1
  33. #endif
  34. #define ATMEL_LCDC_FIFO_SIZE 512
  35. /*
  36. * the CLUT register map as following
  37. * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
  38. */
  39. void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  40. {
  41. writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
  42. ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
  43. | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
  44. | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
  45. }
  46. ushort *configuration_get_cmap(void)
  47. {
  48. #if defined(CONFIG_LCD_LOGO)
  49. return bmp_logo_palette;
  50. #else
  51. return NULL;
  52. #endif
  53. }
  54. void lcd_ctrl_init(void *lcdbase)
  55. {
  56. unsigned long value;
  57. struct lcd_dma_desc *desc;
  58. struct atmel_hlcd_regs *regs;
  59. int ret;
  60. if (!has_lcdc())
  61. return; /* No lcdc */
  62. regs = (struct atmel_hlcd_regs *)panel_info.mmio;
  63. /* Disable DISP signal */
  64. writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
  65. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  66. false, 1000, false);
  67. if (ret)
  68. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  69. /* Disable synchronization */
  70. writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
  71. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  72. false, 1000, false);
  73. if (ret)
  74. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  75. /* Disable pixel clock */
  76. writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
  77. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  78. false, 1000, false);
  79. if (ret)
  80. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  81. /* Disable PWM */
  82. writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
  83. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  84. false, 1000, false);
  85. if (ret)
  86. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  87. /* Set pixel clock */
  88. value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
  89. if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
  90. value++;
  91. if (value < 1) {
  92. /* Using system clock as pixel clock */
  93. writel(LCDC_LCDCFG0_CLKDIV(0)
  94. | LCDC_LCDCFG0_CGDISHCR
  95. | LCDC_LCDCFG0_CGDISHEO
  96. | LCDC_LCDCFG0_CGDISOVR1
  97. | LCDC_LCDCFG0_CGDISBASE
  98. | panel_info.vl_clk_pol
  99. | LCDC_LCDCFG0_CLKSEL,
  100. &regs->lcdc_lcdcfg0);
  101. } else {
  102. writel(LCDC_LCDCFG0_CLKDIV(value - 2)
  103. | LCDC_LCDCFG0_CGDISHCR
  104. | LCDC_LCDCFG0_CGDISHEO
  105. | LCDC_LCDCFG0_CGDISOVR1
  106. | LCDC_LCDCFG0_CGDISBASE
  107. | panel_info.vl_clk_pol,
  108. &regs->lcdc_lcdcfg0);
  109. }
  110. /* Initialize control register 5 */
  111. value = 0;
  112. value |= panel_info.vl_sync;
  113. #ifndef LCD_OUTPUT_BPP
  114. /* Output is 24bpp */
  115. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  116. #else
  117. switch (LCD_OUTPUT_BPP) {
  118. case 12:
  119. value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
  120. break;
  121. case 16:
  122. value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
  123. break;
  124. case 18:
  125. value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
  126. break;
  127. case 24:
  128. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  129. break;
  130. default:
  131. BUG();
  132. break;
  133. }
  134. #endif
  135. value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
  136. value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
  137. writel(value, &regs->lcdc_lcdcfg5);
  138. /* Vertical & Horizontal Timing */
  139. value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
  140. value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
  141. writel(value, &regs->lcdc_lcdcfg1);
  142. value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
  143. value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
  144. writel(value, &regs->lcdc_lcdcfg2);
  145. value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
  146. value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
  147. writel(value, &regs->lcdc_lcdcfg3);
  148. /* Display size */
  149. value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
  150. value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
  151. writel(value, &regs->lcdc_lcdcfg4);
  152. writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
  153. &regs->lcdc_basecfg0);
  154. switch (NBITS(panel_info.vl_bpix)) {
  155. case 16:
  156. writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
  157. &regs->lcdc_basecfg1);
  158. break;
  159. case 32:
  160. writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
  161. &regs->lcdc_basecfg1);
  162. break;
  163. default:
  164. BUG();
  165. break;
  166. }
  167. writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
  168. writel(0, &regs->lcdc_basecfg3);
  169. writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
  170. /* Disable all interrupts */
  171. writel(~0UL, &regs->lcdc_lcdidr);
  172. writel(~0UL, &regs->lcdc_baseidr);
  173. /* Setup the DMA descriptor, this descriptor will loop to itself */
  174. desc = (struct lcd_dma_desc *)(lcdbase - 16);
  175. desc->address = (u32)lcdbase;
  176. /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
  177. desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
  178. | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
  179. desc->next = (u32)desc;
  180. /* Flush the DMA descriptor if we enabled dcache */
  181. flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
  182. writel(desc->address, &regs->lcdc_baseaddr);
  183. writel(desc->control, &regs->lcdc_basectrl);
  184. writel(desc->next, &regs->lcdc_basenext);
  185. writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
  186. &regs->lcdc_basecher);
  187. /* Enable LCD */
  188. value = readl(&regs->lcdc_lcden);
  189. writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
  190. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  191. true, 1000, false);
  192. if (ret)
  193. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  194. value = readl(&regs->lcdc_lcden);
  195. writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
  196. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  197. true, 1000, false);
  198. if (ret)
  199. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  200. value = readl(&regs->lcdc_lcden);
  201. writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
  202. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  203. true, 1000, false);
  204. if (ret)
  205. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  206. value = readl(&regs->lcdc_lcden);
  207. writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
  208. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  209. true, 1000, false);
  210. if (ret)
  211. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  212. /* Enable flushing if we enabled dcache */
  213. lcd_set_flush_dcache(1);
  214. }
  215. #else
  216. enum {
  217. LCD_MAX_WIDTH = 1024,
  218. LCD_MAX_HEIGHT = 768,
  219. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  220. };
  221. struct atmel_hlcdc_priv {
  222. struct atmel_hlcd_regs *regs;
  223. struct display_timing timing;
  224. unsigned int vl_bpix;
  225. unsigned int output_mode;
  226. unsigned int guard_time;
  227. ulong clk_rate;
  228. };
  229. static int at91_hlcdc_enable_clk(struct udevice *dev)
  230. {
  231. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  232. struct clk clk;
  233. ulong clk_rate;
  234. int ret;
  235. ret = clk_get_by_index(dev, 0, &clk);
  236. if (ret)
  237. return -EINVAL;
  238. ret = clk_enable(&clk);
  239. if (ret)
  240. return ret;
  241. clk_rate = clk_get_rate(&clk);
  242. if (!clk_rate) {
  243. clk_disable(&clk);
  244. return -ENODEV;
  245. }
  246. priv->clk_rate = clk_rate;
  247. clk_free(&clk);
  248. return 0;
  249. }
  250. static void atmel_hlcdc_init(struct udevice *dev)
  251. {
  252. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  253. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  254. struct atmel_hlcd_regs *regs = priv->regs;
  255. struct display_timing *timing = &priv->timing;
  256. struct lcd_dma_desc *desc;
  257. unsigned long value, vl_clk_pol;
  258. int ret;
  259. /* Disable DISP signal */
  260. writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
  261. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  262. false, 1000, false);
  263. if (ret)
  264. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  265. /* Disable synchronization */
  266. writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
  267. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  268. false, 1000, false);
  269. if (ret)
  270. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  271. /* Disable pixel clock */
  272. writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
  273. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  274. false, 1000, false);
  275. if (ret)
  276. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  277. /* Disable PWM */
  278. writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
  279. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  280. false, 1000, false);
  281. if (ret)
  282. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  283. /* Set pixel clock */
  284. value = priv->clk_rate / timing->pixelclock.typ;
  285. if (priv->clk_rate % timing->pixelclock.typ)
  286. value++;
  287. vl_clk_pol = 0;
  288. if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
  289. vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
  290. if (value < 1) {
  291. /* Using system clock as pixel clock */
  292. writel(LCDC_LCDCFG0_CLKDIV(0)
  293. | LCDC_LCDCFG0_CGDISHCR
  294. | LCDC_LCDCFG0_CGDISHEO
  295. | LCDC_LCDCFG0_CGDISOVR1
  296. | LCDC_LCDCFG0_CGDISBASE
  297. | vl_clk_pol
  298. | LCDC_LCDCFG0_CLKSEL,
  299. &regs->lcdc_lcdcfg0);
  300. } else {
  301. writel(LCDC_LCDCFG0_CLKDIV(value - 2)
  302. | LCDC_LCDCFG0_CGDISHCR
  303. | LCDC_LCDCFG0_CGDISHEO
  304. | LCDC_LCDCFG0_CGDISOVR1
  305. | LCDC_LCDCFG0_CGDISBASE
  306. | vl_clk_pol,
  307. &regs->lcdc_lcdcfg0);
  308. }
  309. /* Initialize control register 5 */
  310. value = 0;
  311. if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
  312. value |= LCDC_LCDCFG5_HSPOL;
  313. if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
  314. value |= LCDC_LCDCFG5_VSPOL;
  315. switch (priv->output_mode) {
  316. case 12:
  317. value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
  318. break;
  319. case 16:
  320. value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
  321. break;
  322. case 18:
  323. value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
  324. break;
  325. case 24:
  326. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  327. break;
  328. default:
  329. BUG();
  330. break;
  331. }
  332. value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
  333. value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
  334. writel(value, &regs->lcdc_lcdcfg5);
  335. /* Vertical & Horizontal Timing */
  336. value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
  337. value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
  338. writel(value, &regs->lcdc_lcdcfg1);
  339. value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
  340. value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
  341. writel(value, &regs->lcdc_lcdcfg2);
  342. value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
  343. value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
  344. writel(value, &regs->lcdc_lcdcfg3);
  345. /* Display size */
  346. value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
  347. value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
  348. writel(value, &regs->lcdc_lcdcfg4);
  349. writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
  350. &regs->lcdc_basecfg0);
  351. switch (VNBITS(priv->vl_bpix)) {
  352. case 16:
  353. writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
  354. &regs->lcdc_basecfg1);
  355. break;
  356. case 32:
  357. writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
  358. &regs->lcdc_basecfg1);
  359. break;
  360. default:
  361. BUG();
  362. break;
  363. }
  364. writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
  365. writel(0, &regs->lcdc_basecfg3);
  366. writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
  367. /* Disable all interrupts */
  368. writel(~0UL, &regs->lcdc_lcdidr);
  369. writel(~0UL, &regs->lcdc_baseidr);
  370. /* Setup the DMA descriptor, this descriptor will loop to itself */
  371. desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
  372. if (!desc)
  373. return;
  374. desc->address = (u32)uc_plat->base;
  375. /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
  376. desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
  377. | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
  378. desc->next = (u32)desc;
  379. /* Flush the DMA descriptor if we enabled dcache */
  380. flush_dcache_range((u32)desc,
  381. ALIGN(((u32)desc + sizeof(*desc)),
  382. CONFIG_SYS_CACHELINE_SIZE));
  383. writel(desc->address, &regs->lcdc_baseaddr);
  384. writel(desc->control, &regs->lcdc_basectrl);
  385. writel(desc->next, &regs->lcdc_basenext);
  386. writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
  387. &regs->lcdc_basecher);
  388. /* Enable LCD */
  389. value = readl(&regs->lcdc_lcden);
  390. writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
  391. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  392. true, 1000, false);
  393. if (ret)
  394. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  395. value = readl(&regs->lcdc_lcden);
  396. writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
  397. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  398. true, 1000, false);
  399. if (ret)
  400. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  401. value = readl(&regs->lcdc_lcden);
  402. writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
  403. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  404. true, 1000, false);
  405. if (ret)
  406. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  407. value = readl(&regs->lcdc_lcden);
  408. writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
  409. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  410. true, 1000, false);
  411. if (ret)
  412. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  413. }
  414. static int atmel_hlcdc_probe(struct udevice *dev)
  415. {
  416. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  417. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  418. int ret;
  419. ret = at91_hlcdc_enable_clk(dev);
  420. if (ret)
  421. return ret;
  422. atmel_hlcdc_init(dev);
  423. uc_priv->xsize = priv->timing.hactive.typ;
  424. uc_priv->ysize = priv->timing.vactive.typ;
  425. uc_priv->bpix = priv->vl_bpix;
  426. /* Enable flushing if we enabled dcache */
  427. video_set_flush_dcache(dev, true);
  428. return 0;
  429. }
  430. static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
  431. {
  432. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  433. const void *blob = gd->fdt_blob;
  434. int node = dev_of_offset(dev);
  435. priv->regs = dev_read_addr_ptr(dev);
  436. if (!priv->regs) {
  437. debug("%s: No display controller address\n", __func__);
  438. return -EINVAL;
  439. }
  440. if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
  441. 0, &priv->timing)) {
  442. debug("%s: Failed to decode display timing\n", __func__);
  443. return -EINVAL;
  444. }
  445. if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
  446. priv->timing.hactive.typ = LCD_MAX_WIDTH;
  447. if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
  448. priv->timing.vactive.typ = LCD_MAX_HEIGHT;
  449. priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
  450. if (!priv->vl_bpix) {
  451. debug("%s: Failed to get bits per pixel\n", __func__);
  452. return -EINVAL;
  453. }
  454. priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
  455. priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
  456. return 0;
  457. }
  458. static int atmel_hlcdc_bind(struct udevice *dev)
  459. {
  460. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  461. uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  462. (1 << LCD_MAX_LOG2_BPP) / 8;
  463. debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  464. return 0;
  465. }
  466. static const struct udevice_id atmel_hlcdc_ids[] = {
  467. { .compatible = "atmel,sama5d2-hlcdc" },
  468. { .compatible = "atmel,at91sam9x5-hlcdc" },
  469. { }
  470. };
  471. U_BOOT_DRIVER(atmel_hlcdfb) = {
  472. .name = "atmel_hlcdfb",
  473. .id = UCLASS_VIDEO,
  474. .of_match = atmel_hlcdc_ids,
  475. .bind = atmel_hlcdc_bind,
  476. .probe = atmel_hlcdc_probe,
  477. .ofdata_to_platdata = atmel_hlcdc_ofdata_to_platdata,
  478. .priv_auto_alloc_size = sizeof(struct atmel_hlcdc_priv),
  479. };
  480. #endif