musb_core.c 3.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Mentor USB OTG Core functionality common for both Host and Device
  4. * functionality.
  5. *
  6. * Copyright (c) 2008 Texas Instruments
  7. *
  8. * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
  9. */
  10. #include <common.h>
  11. #include <linux/bitops.h>
  12. #include "musb_core.h"
  13. struct musb_regs *musbr;
  14. /*
  15. * program the mentor core to start (enable interrupts, dma, etc.)
  16. */
  17. void musb_start(void)
  18. {
  19. #if defined(CONFIG_USB_MUSB_HCD)
  20. u8 devctl;
  21. u8 busctl;
  22. #endif
  23. /* disable all interrupts */
  24. writew(0, &musbr->intrtxe);
  25. writew(0, &musbr->intrrxe);
  26. writeb(0, &musbr->intrusbe);
  27. writeb(0, &musbr->testmode);
  28. /* put into basic highspeed mode and start session */
  29. writeb(MUSB_POWER_HSENAB, &musbr->power);
  30. #if defined(CONFIG_USB_MUSB_HCD)
  31. /* Program PHY to use EXT VBUS if required */
  32. if (musb_cfg.extvbus == 1) {
  33. busctl = musb_read_ulpi_buscontrol(musbr);
  34. musb_write_ulpi_buscontrol(musbr, busctl | ULPI_USE_EXTVBUS);
  35. }
  36. devctl = readb(&musbr->devctl);
  37. writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl);
  38. #endif
  39. }
  40. #ifdef MUSB_NO_DYNAMIC_FIFO
  41. # define config_fifo(dir, idx, addr)
  42. #else
  43. # define config_fifo(dir, idx, addr) \
  44. do { \
  45. writeb(idx, &musbr->dir##fifosz); \
  46. writew(fifoaddr >> 3, &musbr->dir##fifoadd); \
  47. } while (0)
  48. #endif
  49. /*
  50. * This function configures the endpoint configuration. The musb hcd or musb
  51. * device implementation can use this function to configure the endpoints
  52. * and set the FIFO sizes. Note: The summation of FIFO sizes of all endpoints
  53. * should not be more than the available FIFO size.
  54. *
  55. * epinfo - Pointer to EP configuration table
  56. * cnt - Number of entries in the EP conf table.
  57. */
  58. void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt)
  59. {
  60. u16 csr;
  61. u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */
  62. u32 fifosize;
  63. u8 idx;
  64. while (cnt--) {
  65. /* prepare fifosize to write to register */
  66. fifosize = epinfo->epsize >> 3;
  67. idx = ffs(fifosize) - 1;
  68. writeb(epinfo->epnum, &musbr->index);
  69. if (epinfo->epdir) {
  70. /* Configure fifo size and fifo base address */
  71. config_fifo(tx, idx, fifoaddr);
  72. csr = readw(&musbr->txcsr);
  73. #if defined(CONFIG_USB_MUSB_HCD)
  74. /* clear the data toggle bit */
  75. writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr);
  76. #endif
  77. /* Flush fifo if required */
  78. if (csr & MUSB_TXCSR_TXPKTRDY)
  79. writew(csr | MUSB_TXCSR_FLUSHFIFO,
  80. &musbr->txcsr);
  81. } else {
  82. /* Configure fifo size and fifo base address */
  83. config_fifo(rx, idx, fifoaddr);
  84. csr = readw(&musbr->rxcsr);
  85. #if defined(CONFIG_USB_MUSB_HCD)
  86. /* clear the data toggle bit */
  87. writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr);
  88. #endif
  89. /* Flush fifo if required */
  90. if (csr & MUSB_RXCSR_RXPKTRDY)
  91. writew(csr | MUSB_RXCSR_FLUSHFIFO,
  92. &musbr->rxcsr);
  93. }
  94. fifoaddr += epinfo->epsize;
  95. epinfo++;
  96. }
  97. }
  98. /*
  99. * This function writes data to endpoint fifo
  100. *
  101. * ep - endpoint number
  102. * length - number of bytes to write to FIFO
  103. * fifo_data - Pointer to data buffer that contains the data to write
  104. */
  105. __attribute__((weak))
  106. void write_fifo(u8 ep, u32 length, void *fifo_data)
  107. {
  108. u8 *data = (u8 *)fifo_data;
  109. /* select the endpoint index */
  110. writeb(ep, &musbr->index);
  111. /* write the data to the fifo */
  112. while (length--)
  113. writeb(*data++, &musbr->fifox[ep]);
  114. }
  115. /*
  116. * AM35x supports only 32bit read operations so
  117. * use seperate read_fifo() function for it.
  118. */
  119. #ifndef CONFIG_USB_AM35X
  120. /*
  121. * This function reads data from endpoint fifo
  122. *
  123. * ep - endpoint number
  124. * length - number of bytes to read from FIFO
  125. * fifo_data - pointer to data buffer into which data is read
  126. */
  127. __attribute__((weak))
  128. void read_fifo(u8 ep, u32 length, void *fifo_data)
  129. {
  130. u8 *data = (u8 *)fifo_data;
  131. /* select the endpoint index */
  132. writeb(ep, &musbr->index);
  133. /* read the data to the fifo */
  134. while (length--)
  135. *data++ = readb(&musbr->fifox[ep]);
  136. }
  137. #endif /* CONFIG_USB_AM35X */