musb_host.c 64 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MUSB OTG driver host support
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
  9. */
  10. #ifndef __UBOOT__
  11. #include <dm/device_compat.h>
  12. #include <dm/devres.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/delay.h>
  16. #include <linux/sched.h>
  17. #include <linux/slab.h>
  18. #include <linux/errno.h>
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/dma-mapping.h>
  22. #else
  23. #include <common.h>
  24. #include <dm.h>
  25. #include <dm/device_compat.h>
  26. #include <usb.h>
  27. #include <linux/bug.h>
  28. #include "linux-compat.h"
  29. #include "usb-compat.h"
  30. #endif
  31. #include "musb_core.h"
  32. #include "musb_host.h"
  33. /* MUSB HOST status 22-mar-2006
  34. *
  35. * - There's still lots of partial code duplication for fault paths, so
  36. * they aren't handled as consistently as they need to be.
  37. *
  38. * - PIO mostly behaved when last tested.
  39. * + including ep0, with all usbtest cases 9, 10
  40. * + usbtest 14 (ep0out) doesn't seem to run at all
  41. * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
  42. * configurations, but otherwise double buffering passes basic tests.
  43. * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
  44. *
  45. * - DMA (CPPI) ... partially behaves, not currently recommended
  46. * + about 1/15 the speed of typical EHCI implementations (PCI)
  47. * + RX, all too often reqpkt seems to misbehave after tx
  48. * + TX, no known issues (other than evident silicon issue)
  49. *
  50. * - DMA (Mentor/OMAP) ...has at least toggle update problems
  51. *
  52. * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
  53. * starvation ... nothing yet for TX, interrupt, or bulk.
  54. *
  55. * - Not tested with HNP, but some SRP paths seem to behave.
  56. *
  57. * NOTE 24-August-2006:
  58. *
  59. * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
  60. * extra endpoint for periodic use enabling hub + keybd + mouse. That
  61. * mostly works, except that with "usbnet" it's easy to trigger cases
  62. * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
  63. * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
  64. * although ARP RX wins. (That test was done with a full speed link.)
  65. */
  66. /*
  67. * NOTE on endpoint usage:
  68. *
  69. * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
  70. * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
  71. * (Yes, bulk _could_ use more of the endpoints than that, and would even
  72. * benefit from it.)
  73. *
  74. * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
  75. * So far that scheduling is both dumb and optimistic: the endpoint will be
  76. * "claimed" until its software queue is no longer refilled. No multiplexing
  77. * of transfers between endpoints, or anything clever.
  78. */
  79. static void musb_ep_program(struct musb *musb, u8 epnum,
  80. struct urb *urb, int is_out,
  81. u8 *buf, u32 offset, u32 len);
  82. /*
  83. * Clear TX fifo. Needed to avoid BABBLE errors.
  84. */
  85. static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
  86. {
  87. struct musb *musb = ep->musb;
  88. void __iomem *epio = ep->regs;
  89. u16 csr;
  90. u16 lastcsr = 0;
  91. int retries = 1000;
  92. csr = musb_readw(epio, MUSB_TXCSR);
  93. while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
  94. if (csr != lastcsr)
  95. dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
  96. lastcsr = csr;
  97. csr |= MUSB_TXCSR_FLUSHFIFO;
  98. musb_writew(epio, MUSB_TXCSR, csr);
  99. csr = musb_readw(epio, MUSB_TXCSR);
  100. if (WARN(retries-- < 1,
  101. "Could not flush host TX%d fifo: csr: %04x\n",
  102. ep->epnum, csr))
  103. return;
  104. mdelay(1);
  105. }
  106. }
  107. static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
  108. {
  109. void __iomem *epio = ep->regs;
  110. u16 csr;
  111. int retries = 5;
  112. /* scrub any data left in the fifo */
  113. do {
  114. csr = musb_readw(epio, MUSB_TXCSR);
  115. if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
  116. break;
  117. musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
  118. csr = musb_readw(epio, MUSB_TXCSR);
  119. udelay(10);
  120. } while (--retries);
  121. WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
  122. ep->epnum, csr);
  123. /* and reset for the next transfer */
  124. musb_writew(epio, MUSB_TXCSR, 0);
  125. }
  126. /*
  127. * Start transmit. Caller is responsible for locking shared resources.
  128. * musb must be locked.
  129. */
  130. static inline void musb_h_tx_start(struct musb_hw_ep *ep)
  131. {
  132. u16 txcsr;
  133. /* NOTE: no locks here; caller should lock and select EP */
  134. if (ep->epnum) {
  135. txcsr = musb_readw(ep->regs, MUSB_TXCSR);
  136. txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
  137. musb_writew(ep->regs, MUSB_TXCSR, txcsr);
  138. } else {
  139. txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
  140. musb_writew(ep->regs, MUSB_CSR0, txcsr);
  141. }
  142. }
  143. static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
  144. {
  145. u16 txcsr;
  146. /* NOTE: no locks here; caller should lock and select EP */
  147. txcsr = musb_readw(ep->regs, MUSB_TXCSR);
  148. txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
  149. if (is_cppi_enabled())
  150. txcsr |= MUSB_TXCSR_DMAMODE;
  151. musb_writew(ep->regs, MUSB_TXCSR, txcsr);
  152. }
  153. static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
  154. {
  155. if (is_in != 0 || ep->is_shared_fifo)
  156. ep->in_qh = qh;
  157. if (is_in == 0 || ep->is_shared_fifo)
  158. ep->out_qh = qh;
  159. }
  160. static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
  161. {
  162. return is_in ? ep->in_qh : ep->out_qh;
  163. }
  164. /*
  165. * Start the URB at the front of an endpoint's queue
  166. * end must be claimed from the caller.
  167. *
  168. * Context: controller locked, irqs blocked
  169. */
  170. static void
  171. musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
  172. {
  173. u16 frame;
  174. u32 len;
  175. void __iomem *mbase = musb->mregs;
  176. struct urb *urb = next_urb(qh);
  177. void *buf = urb->transfer_buffer;
  178. u32 offset = 0;
  179. struct musb_hw_ep *hw_ep = qh->hw_ep;
  180. unsigned pipe = urb->pipe;
  181. u8 address = usb_pipedevice(pipe);
  182. int epnum = hw_ep->epnum;
  183. /* initialize software qh state */
  184. qh->offset = 0;
  185. qh->segsize = 0;
  186. /* gather right source of data */
  187. switch (qh->type) {
  188. case USB_ENDPOINT_XFER_CONTROL:
  189. /* control transfers always start with SETUP */
  190. is_in = 0;
  191. musb->ep0_stage = MUSB_EP0_START;
  192. buf = urb->setup_packet;
  193. len = 8;
  194. break;
  195. #ifndef __UBOOT__
  196. case USB_ENDPOINT_XFER_ISOC:
  197. qh->iso_idx = 0;
  198. qh->frame = 0;
  199. offset = urb->iso_frame_desc[0].offset;
  200. len = urb->iso_frame_desc[0].length;
  201. break;
  202. #endif
  203. default: /* bulk, interrupt */
  204. /* actual_length may be nonzero on retry paths */
  205. buf = urb->transfer_buffer + urb->actual_length;
  206. len = urb->transfer_buffer_length - urb->actual_length;
  207. }
  208. dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
  209. qh, urb, address, qh->epnum,
  210. is_in ? "in" : "out",
  211. ({char *s; switch (qh->type) {
  212. case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
  213. case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
  214. #ifndef __UBOOT__
  215. case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
  216. #endif
  217. default: s = "-intr"; break;
  218. }; s; }),
  219. epnum, buf + offset, len);
  220. /* Configure endpoint */
  221. musb_ep_set_qh(hw_ep, is_in, qh);
  222. musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
  223. /* transmit may have more work: start it when it is time */
  224. if (is_in)
  225. return;
  226. /* determine if the time is right for a periodic transfer */
  227. switch (qh->type) {
  228. #ifndef __UBOOT__
  229. case USB_ENDPOINT_XFER_ISOC:
  230. #endif
  231. case USB_ENDPOINT_XFER_INT:
  232. dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
  233. frame = musb_readw(mbase, MUSB_FRAME);
  234. /* FIXME this doesn't implement that scheduling policy ...
  235. * or handle framecounter wrapping
  236. */
  237. #ifndef __UBOOT__
  238. if ((urb->transfer_flags & URB_ISO_ASAP)
  239. || (frame >= urb->start_frame)) {
  240. /* REVISIT the SOF irq handler shouldn't duplicate
  241. * this code; and we don't init urb->start_frame...
  242. */
  243. qh->frame = 0;
  244. goto start;
  245. } else {
  246. #endif
  247. qh->frame = urb->start_frame;
  248. /* enable SOF interrupt so we can count down */
  249. dev_dbg(musb->controller, "SOF for %d\n", epnum);
  250. #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
  251. musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
  252. #endif
  253. #ifndef __UBOOT__
  254. }
  255. #endif
  256. break;
  257. default:
  258. start:
  259. dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
  260. hw_ep->tx_channel ? "dma" : "pio");
  261. if (!hw_ep->tx_channel)
  262. musb_h_tx_start(hw_ep);
  263. else if (is_cppi_enabled() || tusb_dma_omap())
  264. musb_h_tx_dma_start(hw_ep);
  265. }
  266. }
  267. /* Context: caller owns controller lock, IRQs are blocked */
  268. static void musb_giveback(struct musb *musb, struct urb *urb, int status)
  269. __releases(musb->lock)
  270. __acquires(musb->lock)
  271. {
  272. dev_dbg(musb->controller,
  273. "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
  274. urb, urb->complete, status,
  275. usb_pipedevice(urb->pipe),
  276. usb_pipeendpoint(urb->pipe),
  277. usb_pipein(urb->pipe) ? "in" : "out",
  278. urb->actual_length, urb->transfer_buffer_length
  279. );
  280. usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
  281. spin_unlock(&musb->lock);
  282. usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
  283. spin_lock(&musb->lock);
  284. }
  285. /* For bulk/interrupt endpoints only */
  286. static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
  287. struct urb *urb)
  288. {
  289. void __iomem *epio = qh->hw_ep->regs;
  290. u16 csr;
  291. /*
  292. * FIXME: the current Mentor DMA code seems to have
  293. * problems getting toggle correct.
  294. */
  295. if (is_in)
  296. csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
  297. else
  298. csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
  299. usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
  300. }
  301. /*
  302. * Advance this hardware endpoint's queue, completing the specified URB and
  303. * advancing to either the next URB queued to that qh, or else invalidating
  304. * that qh and advancing to the next qh scheduled after the current one.
  305. *
  306. * Context: caller owns controller lock, IRQs are blocked
  307. */
  308. static void musb_advance_schedule(struct musb *musb, struct urb *urb,
  309. struct musb_hw_ep *hw_ep, int is_in)
  310. {
  311. struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
  312. struct musb_hw_ep *ep = qh->hw_ep;
  313. int ready = qh->is_ready;
  314. int status;
  315. status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
  316. /* save toggle eagerly, for paranoia */
  317. switch (qh->type) {
  318. case USB_ENDPOINT_XFER_BULK:
  319. case USB_ENDPOINT_XFER_INT:
  320. musb_save_toggle(qh, is_in, urb);
  321. break;
  322. #ifndef __UBOOT__
  323. case USB_ENDPOINT_XFER_ISOC:
  324. if (status == 0 && urb->error_count)
  325. status = -EXDEV;
  326. break;
  327. #endif
  328. }
  329. qh->is_ready = 0;
  330. musb_giveback(musb, urb, status);
  331. qh->is_ready = ready;
  332. /* reclaim resources (and bandwidth) ASAP; deschedule it, and
  333. * invalidate qh as soon as list_empty(&hep->urb_list)
  334. */
  335. if (list_empty(&qh->hep->urb_list)) {
  336. struct list_head *head;
  337. struct dma_controller *dma = musb->dma_controller;
  338. if (is_in) {
  339. ep->rx_reinit = 1;
  340. if (ep->rx_channel) {
  341. dma->channel_release(ep->rx_channel);
  342. ep->rx_channel = NULL;
  343. }
  344. } else {
  345. ep->tx_reinit = 1;
  346. if (ep->tx_channel) {
  347. dma->channel_release(ep->tx_channel);
  348. ep->tx_channel = NULL;
  349. }
  350. }
  351. /* Clobber old pointers to this qh */
  352. musb_ep_set_qh(ep, is_in, NULL);
  353. qh->hep->hcpriv = NULL;
  354. switch (qh->type) {
  355. case USB_ENDPOINT_XFER_CONTROL:
  356. case USB_ENDPOINT_XFER_BULK:
  357. /* fifo policy for these lists, except that NAKing
  358. * should rotate a qh to the end (for fairness).
  359. */
  360. if (qh->mux == 1) {
  361. head = qh->ring.prev;
  362. list_del(&qh->ring);
  363. kfree(qh);
  364. qh = first_qh(head);
  365. break;
  366. }
  367. case USB_ENDPOINT_XFER_ISOC:
  368. case USB_ENDPOINT_XFER_INT:
  369. /* this is where periodic bandwidth should be
  370. * de-allocated if it's tracked and allocated;
  371. * and where we'd update the schedule tree...
  372. */
  373. kfree(qh);
  374. qh = NULL;
  375. break;
  376. }
  377. }
  378. if (qh != NULL && qh->is_ready) {
  379. dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
  380. hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
  381. musb_start_urb(musb, is_in, qh);
  382. }
  383. }
  384. static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
  385. {
  386. /* we don't want fifo to fill itself again;
  387. * ignore dma (various models),
  388. * leave toggle alone (may not have been saved yet)
  389. */
  390. csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
  391. csr &= ~(MUSB_RXCSR_H_REQPKT
  392. | MUSB_RXCSR_H_AUTOREQ
  393. | MUSB_RXCSR_AUTOCLEAR);
  394. /* write 2x to allow double buffering */
  395. musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
  396. musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
  397. /* flush writebuffer */
  398. return musb_readw(hw_ep->regs, MUSB_RXCSR);
  399. }
  400. /*
  401. * PIO RX for a packet (or part of it).
  402. */
  403. static bool
  404. musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
  405. {
  406. u16 rx_count;
  407. u8 *buf;
  408. u16 csr;
  409. bool done = false;
  410. u32 length;
  411. int do_flush = 0;
  412. struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
  413. void __iomem *epio = hw_ep->regs;
  414. struct musb_qh *qh = hw_ep->in_qh;
  415. int pipe = urb->pipe;
  416. void *buffer = urb->transfer_buffer;
  417. /* musb_ep_select(mbase, epnum); */
  418. rx_count = musb_readw(epio, MUSB_RXCOUNT);
  419. dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
  420. urb->transfer_buffer, qh->offset,
  421. urb->transfer_buffer_length);
  422. /* unload FIFO */
  423. #ifndef __UBOOT__
  424. if (usb_pipeisoc(pipe)) {
  425. int status = 0;
  426. struct usb_iso_packet_descriptor *d;
  427. if (iso_err) {
  428. status = -EILSEQ;
  429. urb->error_count++;
  430. }
  431. d = urb->iso_frame_desc + qh->iso_idx;
  432. buf = buffer + d->offset;
  433. length = d->length;
  434. if (rx_count > length) {
  435. if (status == 0) {
  436. status = -EOVERFLOW;
  437. urb->error_count++;
  438. }
  439. dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
  440. do_flush = 1;
  441. } else
  442. length = rx_count;
  443. urb->actual_length += length;
  444. d->actual_length = length;
  445. d->status = status;
  446. /* see if we are done */
  447. done = (++qh->iso_idx >= urb->number_of_packets);
  448. } else {
  449. #endif
  450. /* non-isoch */
  451. buf = buffer + qh->offset;
  452. length = urb->transfer_buffer_length - qh->offset;
  453. if (rx_count > length) {
  454. if (urb->status == -EINPROGRESS)
  455. urb->status = -EOVERFLOW;
  456. dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
  457. do_flush = 1;
  458. } else
  459. length = rx_count;
  460. urb->actual_length += length;
  461. qh->offset += length;
  462. /* see if we are done */
  463. done = (urb->actual_length == urb->transfer_buffer_length)
  464. || (rx_count < qh->maxpacket)
  465. || (urb->status != -EINPROGRESS);
  466. if (done
  467. && (urb->status == -EINPROGRESS)
  468. && (urb->transfer_flags & URB_SHORT_NOT_OK)
  469. && (urb->actual_length
  470. < urb->transfer_buffer_length))
  471. urb->status = -EREMOTEIO;
  472. #ifndef __UBOOT__
  473. }
  474. #endif
  475. musb_read_fifo(hw_ep, length, buf);
  476. csr = musb_readw(epio, MUSB_RXCSR);
  477. csr |= MUSB_RXCSR_H_WZC_BITS;
  478. if (unlikely(do_flush))
  479. musb_h_flush_rxfifo(hw_ep, csr);
  480. else {
  481. /* REVISIT this assumes AUTOCLEAR is never set */
  482. csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
  483. if (!done)
  484. csr |= MUSB_RXCSR_H_REQPKT;
  485. musb_writew(epio, MUSB_RXCSR, csr);
  486. }
  487. return done;
  488. }
  489. /* we don't always need to reinit a given side of an endpoint...
  490. * when we do, use tx/rx reinit routine and then construct a new CSR
  491. * to address data toggle, NYET, and DMA or PIO.
  492. *
  493. * it's possible that driver bugs (especially for DMA) or aborting a
  494. * transfer might have left the endpoint busier than it should be.
  495. * the busy/not-empty tests are basically paranoia.
  496. */
  497. static void
  498. musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
  499. {
  500. u16 csr;
  501. /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
  502. * That always uses tx_reinit since ep0 repurposes TX register
  503. * offsets; the initial SETUP packet is also a kind of OUT.
  504. */
  505. /* if programmed for Tx, put it in RX mode */
  506. if (ep->is_shared_fifo) {
  507. csr = musb_readw(ep->regs, MUSB_TXCSR);
  508. if (csr & MUSB_TXCSR_MODE) {
  509. musb_h_tx_flush_fifo(ep);
  510. csr = musb_readw(ep->regs, MUSB_TXCSR);
  511. musb_writew(ep->regs, MUSB_TXCSR,
  512. csr | MUSB_TXCSR_FRCDATATOG);
  513. }
  514. /*
  515. * Clear the MODE bit (and everything else) to enable Rx.
  516. * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
  517. */
  518. if (csr & MUSB_TXCSR_DMAMODE)
  519. musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
  520. musb_writew(ep->regs, MUSB_TXCSR, 0);
  521. /* scrub all previous state, clearing toggle */
  522. } else {
  523. csr = musb_readw(ep->regs, MUSB_RXCSR);
  524. if (csr & MUSB_RXCSR_RXPKTRDY)
  525. WARNING("rx%d, packet/%d ready?\n", ep->epnum,
  526. musb_readw(ep->regs, MUSB_RXCOUNT));
  527. musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
  528. }
  529. /* target addr and (for multipoint) hub addr/port */
  530. if (musb->is_multipoint) {
  531. musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
  532. musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
  533. musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
  534. } else
  535. musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
  536. /* protocol/endpoint, interval/NAKlimit, i/o size */
  537. musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
  538. musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
  539. /* NOTE: bulk combining rewrites high bits of maxpacket */
  540. /* Set RXMAXP with the FIFO size of the endpoint
  541. * to disable double buffer mode.
  542. */
  543. if (musb->double_buffer_not_ok)
  544. musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
  545. else
  546. musb_writew(ep->regs, MUSB_RXMAXP,
  547. qh->maxpacket | ((qh->hb_mult - 1) << 11));
  548. ep->rx_reinit = 0;
  549. }
  550. static bool musb_tx_dma_program(struct dma_controller *dma,
  551. struct musb_hw_ep *hw_ep, struct musb_qh *qh,
  552. struct urb *urb, u32 offset, u32 length)
  553. {
  554. struct dma_channel *channel = hw_ep->tx_channel;
  555. void __iomem *epio = hw_ep->regs;
  556. u16 pkt_size = qh->maxpacket;
  557. u16 csr;
  558. u8 mode;
  559. #ifdef CONFIG_USB_INVENTRA_DMA
  560. if (length > channel->max_len)
  561. length = channel->max_len;
  562. csr = musb_readw(epio, MUSB_TXCSR);
  563. if (length > pkt_size) {
  564. mode = 1;
  565. csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
  566. /* autoset shouldn't be set in high bandwidth */
  567. if (qh->hb_mult == 1)
  568. csr |= MUSB_TXCSR_AUTOSET;
  569. } else {
  570. mode = 0;
  571. csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
  572. csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
  573. }
  574. channel->desired_mode = mode;
  575. musb_writew(epio, MUSB_TXCSR, csr);
  576. #else
  577. if (!is_cppi_enabled() && !tusb_dma_omap())
  578. return false;
  579. channel->actual_len = 0;
  580. /*
  581. * TX uses "RNDIS" mode automatically but needs help
  582. * to identify the zero-length-final-packet case.
  583. */
  584. mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
  585. #endif
  586. qh->segsize = length;
  587. /*
  588. * Ensure the data reaches to main memory before starting
  589. * DMA transfer
  590. */
  591. wmb();
  592. if (!dma->channel_program(channel, pkt_size, mode,
  593. urb->transfer_dma + offset, length)) {
  594. dma->channel_release(channel);
  595. hw_ep->tx_channel = NULL;
  596. csr = musb_readw(epio, MUSB_TXCSR);
  597. csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
  598. musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
  599. return false;
  600. }
  601. return true;
  602. }
  603. /*
  604. * Program an HDRC endpoint as per the given URB
  605. * Context: irqs blocked, controller lock held
  606. */
  607. static void musb_ep_program(struct musb *musb, u8 epnum,
  608. struct urb *urb, int is_out,
  609. u8 *buf, u32 offset, u32 len)
  610. {
  611. struct dma_controller *dma_controller;
  612. struct dma_channel *dma_channel;
  613. u8 dma_ok;
  614. void __iomem *mbase = musb->mregs;
  615. struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
  616. void __iomem *epio = hw_ep->regs;
  617. struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
  618. u16 packet_sz = qh->maxpacket;
  619. dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
  620. "h_addr%02x h_port%02x bytes %d\n",
  621. is_out ? "-->" : "<--",
  622. epnum, urb, urb->dev->speed,
  623. qh->addr_reg, qh->epnum, is_out ? "out" : "in",
  624. qh->h_addr_reg, qh->h_port_reg,
  625. len);
  626. musb_ep_select(mbase, epnum);
  627. /* candidate for DMA? */
  628. dma_controller = musb->dma_controller;
  629. if (is_dma_capable() && epnum && dma_controller) {
  630. dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
  631. if (!dma_channel) {
  632. dma_channel = dma_controller->channel_alloc(
  633. dma_controller, hw_ep, is_out);
  634. if (is_out)
  635. hw_ep->tx_channel = dma_channel;
  636. else
  637. hw_ep->rx_channel = dma_channel;
  638. }
  639. } else
  640. dma_channel = NULL;
  641. /* make sure we clear DMAEnab, autoSet bits from previous run */
  642. /* OUT/transmit/EP0 or IN/receive? */
  643. if (is_out) {
  644. u16 csr;
  645. u16 int_txe;
  646. u16 load_count;
  647. csr = musb_readw(epio, MUSB_TXCSR);
  648. /* disable interrupt in case we flush */
  649. int_txe = musb_readw(mbase, MUSB_INTRTXE);
  650. musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
  651. /* general endpoint setup */
  652. if (epnum) {
  653. /* flush all old state, set default */
  654. musb_h_tx_flush_fifo(hw_ep);
  655. /*
  656. * We must not clear the DMAMODE bit before or in
  657. * the same cycle with the DMAENAB bit, so we clear
  658. * the latter first...
  659. */
  660. csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
  661. | MUSB_TXCSR_AUTOSET
  662. | MUSB_TXCSR_DMAENAB
  663. | MUSB_TXCSR_FRCDATATOG
  664. | MUSB_TXCSR_H_RXSTALL
  665. | MUSB_TXCSR_H_ERROR
  666. | MUSB_TXCSR_TXPKTRDY
  667. );
  668. csr |= MUSB_TXCSR_MODE;
  669. if (usb_gettoggle(urb->dev, qh->epnum, 1))
  670. csr |= MUSB_TXCSR_H_WR_DATATOGGLE
  671. | MUSB_TXCSR_H_DATATOGGLE;
  672. else
  673. csr |= MUSB_TXCSR_CLRDATATOG;
  674. musb_writew(epio, MUSB_TXCSR, csr);
  675. /* REVISIT may need to clear FLUSHFIFO ... */
  676. csr &= ~MUSB_TXCSR_DMAMODE;
  677. musb_writew(epio, MUSB_TXCSR, csr);
  678. csr = musb_readw(epio, MUSB_TXCSR);
  679. } else {
  680. /* endpoint 0: just flush */
  681. musb_h_ep0_flush_fifo(hw_ep);
  682. }
  683. /* target addr and (for multipoint) hub addr/port */
  684. if (musb->is_multipoint) {
  685. musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
  686. musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
  687. musb_write_txhubport(mbase, epnum, qh->h_port_reg);
  688. /* FIXME if !epnum, do the same for RX ... */
  689. } else
  690. musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
  691. /* protocol/endpoint/interval/NAKlimit */
  692. if (epnum) {
  693. musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
  694. if (musb->double_buffer_not_ok)
  695. musb_writew(epio, MUSB_TXMAXP,
  696. hw_ep->max_packet_sz_tx);
  697. else if (can_bulk_split(musb, qh->type))
  698. musb_writew(epio, MUSB_TXMAXP, packet_sz
  699. | ((hw_ep->max_packet_sz_tx /
  700. packet_sz) - 1) << 11);
  701. else
  702. musb_writew(epio, MUSB_TXMAXP,
  703. qh->maxpacket |
  704. ((qh->hb_mult - 1) << 11));
  705. musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
  706. } else {
  707. musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
  708. if (musb->is_multipoint)
  709. musb_writeb(epio, MUSB_TYPE0,
  710. qh->type_reg);
  711. }
  712. if (can_bulk_split(musb, qh->type))
  713. load_count = min((u32) hw_ep->max_packet_sz_tx,
  714. len);
  715. else
  716. load_count = min((u32) packet_sz, len);
  717. if (dma_channel && musb_tx_dma_program(dma_controller,
  718. hw_ep, qh, urb, offset, len))
  719. load_count = 0;
  720. if (load_count) {
  721. /* PIO to load FIFO */
  722. qh->segsize = load_count;
  723. musb_write_fifo(hw_ep, load_count, buf);
  724. }
  725. /* re-enable interrupt */
  726. musb_writew(mbase, MUSB_INTRTXE, int_txe);
  727. /* IN/receive */
  728. } else {
  729. u16 csr;
  730. if (hw_ep->rx_reinit) {
  731. musb_rx_reinit(musb, qh, hw_ep);
  732. /* init new state: toggle and NYET, maybe DMA later */
  733. if (usb_gettoggle(urb->dev, qh->epnum, 0))
  734. csr = MUSB_RXCSR_H_WR_DATATOGGLE
  735. | MUSB_RXCSR_H_DATATOGGLE;
  736. else
  737. csr = 0;
  738. if (qh->type == USB_ENDPOINT_XFER_INT)
  739. csr |= MUSB_RXCSR_DISNYET;
  740. } else {
  741. csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
  742. if (csr & (MUSB_RXCSR_RXPKTRDY
  743. | MUSB_RXCSR_DMAENAB
  744. | MUSB_RXCSR_H_REQPKT))
  745. ERR("broken !rx_reinit, ep%d csr %04x\n",
  746. hw_ep->epnum, csr);
  747. /* scrub any stale state, leaving toggle alone */
  748. csr &= MUSB_RXCSR_DISNYET;
  749. }
  750. /* kick things off */
  751. if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
  752. /* Candidate for DMA */
  753. dma_channel->actual_len = 0L;
  754. qh->segsize = len;
  755. /* AUTOREQ is in a DMA register */
  756. musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
  757. csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
  758. /*
  759. * Unless caller treats short RX transfers as
  760. * errors, we dare not queue multiple transfers.
  761. */
  762. dma_ok = dma_controller->channel_program(dma_channel,
  763. packet_sz, !(urb->transfer_flags &
  764. URB_SHORT_NOT_OK),
  765. urb->transfer_dma + offset,
  766. qh->segsize);
  767. if (!dma_ok) {
  768. dma_controller->channel_release(dma_channel);
  769. hw_ep->rx_channel = dma_channel = NULL;
  770. } else
  771. csr |= MUSB_RXCSR_DMAENAB;
  772. }
  773. csr |= MUSB_RXCSR_H_REQPKT;
  774. dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
  775. musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
  776. csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
  777. }
  778. }
  779. /*
  780. * Service the default endpoint (ep0) as host.
  781. * Return true until it's time to start the status stage.
  782. */
  783. static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
  784. {
  785. bool more = false;
  786. u8 *fifo_dest = NULL;
  787. u16 fifo_count = 0;
  788. struct musb_hw_ep *hw_ep = musb->control_ep;
  789. struct musb_qh *qh = hw_ep->in_qh;
  790. struct usb_ctrlrequest *request;
  791. switch (musb->ep0_stage) {
  792. case MUSB_EP0_IN:
  793. fifo_dest = urb->transfer_buffer + urb->actual_length;
  794. fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
  795. urb->actual_length);
  796. if (fifo_count < len)
  797. urb->status = -EOVERFLOW;
  798. musb_read_fifo(hw_ep, fifo_count, fifo_dest);
  799. urb->actual_length += fifo_count;
  800. if (len < qh->maxpacket) {
  801. /* always terminate on short read; it's
  802. * rarely reported as an error.
  803. */
  804. } else if (urb->actual_length <
  805. urb->transfer_buffer_length)
  806. more = true;
  807. break;
  808. case MUSB_EP0_START:
  809. request = (struct usb_ctrlrequest *) urb->setup_packet;
  810. if (!request->wLength) {
  811. dev_dbg(musb->controller, "start no-DATA\n");
  812. break;
  813. } else if (request->bRequestType & USB_DIR_IN) {
  814. dev_dbg(musb->controller, "start IN-DATA\n");
  815. musb->ep0_stage = MUSB_EP0_IN;
  816. more = true;
  817. break;
  818. } else {
  819. dev_dbg(musb->controller, "start OUT-DATA\n");
  820. musb->ep0_stage = MUSB_EP0_OUT;
  821. more = true;
  822. }
  823. /* FALLTHROUGH */
  824. case MUSB_EP0_OUT:
  825. fifo_count = min_t(size_t, qh->maxpacket,
  826. urb->transfer_buffer_length -
  827. urb->actual_length);
  828. if (fifo_count) {
  829. fifo_dest = (u8 *) (urb->transfer_buffer
  830. + urb->actual_length);
  831. dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
  832. fifo_count,
  833. (fifo_count == 1) ? "" : "s",
  834. fifo_dest);
  835. musb_write_fifo(hw_ep, fifo_count, fifo_dest);
  836. urb->actual_length += fifo_count;
  837. more = true;
  838. }
  839. break;
  840. default:
  841. ERR("bogus ep0 stage %d\n", musb->ep0_stage);
  842. break;
  843. }
  844. return more;
  845. }
  846. /*
  847. * Handle default endpoint interrupt as host. Only called in IRQ time
  848. * from musb_interrupt().
  849. *
  850. * called with controller irqlocked
  851. */
  852. irqreturn_t musb_h_ep0_irq(struct musb *musb)
  853. {
  854. struct urb *urb;
  855. u16 csr, len;
  856. int status = 0;
  857. void __iomem *mbase = musb->mregs;
  858. struct musb_hw_ep *hw_ep = musb->control_ep;
  859. void __iomem *epio = hw_ep->regs;
  860. struct musb_qh *qh = hw_ep->in_qh;
  861. bool complete = false;
  862. irqreturn_t retval = IRQ_NONE;
  863. /* ep0 only has one queue, "in" */
  864. urb = next_urb(qh);
  865. musb_ep_select(mbase, 0);
  866. csr = musb_readw(epio, MUSB_CSR0);
  867. len = (csr & MUSB_CSR0_RXPKTRDY)
  868. ? musb_readb(epio, MUSB_COUNT0)
  869. : 0;
  870. dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
  871. csr, qh, len, urb, musb->ep0_stage);
  872. /* if we just did status stage, we are done */
  873. if (MUSB_EP0_STATUS == musb->ep0_stage) {
  874. retval = IRQ_HANDLED;
  875. complete = true;
  876. }
  877. /* prepare status */
  878. if (csr & MUSB_CSR0_H_RXSTALL) {
  879. dev_dbg(musb->controller, "STALLING ENDPOINT\n");
  880. status = -EPIPE;
  881. } else if (csr & MUSB_CSR0_H_ERROR) {
  882. dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
  883. status = -EPROTO;
  884. } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
  885. dev_dbg(musb->controller, "control NAK timeout\n");
  886. /* NOTE: this code path would be a good place to PAUSE a
  887. * control transfer, if another one is queued, so that
  888. * ep0 is more likely to stay busy. That's already done
  889. * for bulk RX transfers.
  890. *
  891. * if (qh->ring.next != &musb->control), then
  892. * we have a candidate... NAKing is *NOT* an error
  893. */
  894. musb_writew(epio, MUSB_CSR0, 0);
  895. retval = IRQ_HANDLED;
  896. }
  897. if (status) {
  898. dev_dbg(musb->controller, "aborting\n");
  899. retval = IRQ_HANDLED;
  900. if (urb)
  901. urb->status = status;
  902. complete = true;
  903. /* use the proper sequence to abort the transfer */
  904. if (csr & MUSB_CSR0_H_REQPKT) {
  905. csr &= ~MUSB_CSR0_H_REQPKT;
  906. musb_writew(epio, MUSB_CSR0, csr);
  907. csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
  908. musb_writew(epio, MUSB_CSR0, csr);
  909. } else {
  910. musb_h_ep0_flush_fifo(hw_ep);
  911. }
  912. musb_writeb(epio, MUSB_NAKLIMIT0, 0);
  913. /* clear it */
  914. musb_writew(epio, MUSB_CSR0, 0);
  915. }
  916. if (unlikely(!urb)) {
  917. /* stop endpoint since we have no place for its data, this
  918. * SHOULD NEVER HAPPEN! */
  919. ERR("no URB for end 0\n");
  920. musb_h_ep0_flush_fifo(hw_ep);
  921. goto done;
  922. }
  923. if (!complete) {
  924. /* call common logic and prepare response */
  925. if (musb_h_ep0_continue(musb, len, urb)) {
  926. /* more packets required */
  927. csr = (MUSB_EP0_IN == musb->ep0_stage)
  928. ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
  929. } else {
  930. /* data transfer complete; perform status phase */
  931. if (usb_pipeout(urb->pipe)
  932. || !urb->transfer_buffer_length)
  933. csr = MUSB_CSR0_H_STATUSPKT
  934. | MUSB_CSR0_H_REQPKT;
  935. else
  936. csr = MUSB_CSR0_H_STATUSPKT
  937. | MUSB_CSR0_TXPKTRDY;
  938. /* flag status stage */
  939. musb->ep0_stage = MUSB_EP0_STATUS;
  940. dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
  941. }
  942. musb_writew(epio, MUSB_CSR0, csr);
  943. retval = IRQ_HANDLED;
  944. } else
  945. musb->ep0_stage = MUSB_EP0_IDLE;
  946. /* call completion handler if done */
  947. if (complete)
  948. musb_advance_schedule(musb, urb, hw_ep, 1);
  949. done:
  950. return retval;
  951. }
  952. #ifdef CONFIG_USB_INVENTRA_DMA
  953. /* Host side TX (OUT) using Mentor DMA works as follows:
  954. submit_urb ->
  955. - if queue was empty, Program Endpoint
  956. - ... which starts DMA to fifo in mode 1 or 0
  957. DMA Isr (transfer complete) -> TxAvail()
  958. - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
  959. only in musb_cleanup_urb)
  960. - TxPktRdy has to be set in mode 0 or for
  961. short packets in mode 1.
  962. */
  963. #endif
  964. /* Service a Tx-Available or dma completion irq for the endpoint */
  965. void musb_host_tx(struct musb *musb, u8 epnum)
  966. {
  967. int pipe;
  968. bool done = false;
  969. u16 tx_csr;
  970. size_t length = 0;
  971. size_t offset = 0;
  972. struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
  973. void __iomem *epio = hw_ep->regs;
  974. struct musb_qh *qh = hw_ep->out_qh;
  975. struct urb *urb = next_urb(qh);
  976. u32 status = 0;
  977. void __iomem *mbase = musb->mregs;
  978. struct dma_channel *dma;
  979. bool transfer_pending = false;
  980. musb_ep_select(mbase, epnum);
  981. tx_csr = musb_readw(epio, MUSB_TXCSR);
  982. /* with CPPI, DMA sometimes triggers "extra" irqs */
  983. if (!urb) {
  984. dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
  985. return;
  986. }
  987. pipe = urb->pipe;
  988. dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
  989. dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
  990. dma ? ", dma" : "");
  991. /* check for errors */
  992. if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
  993. /* dma was disabled, fifo flushed */
  994. dev_dbg(musb->controller, "TX end %d stall\n", epnum);
  995. /* stall; record URB status */
  996. status = -EPIPE;
  997. } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
  998. /* (NON-ISO) dma was disabled, fifo flushed */
  999. dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
  1000. status = -ETIMEDOUT;
  1001. } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
  1002. dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
  1003. /* NOTE: this code path would be a good place to PAUSE a
  1004. * transfer, if there's some other (nonperiodic) tx urb
  1005. * that could use this fifo. (dma complicates it...)
  1006. * That's already done for bulk RX transfers.
  1007. *
  1008. * if (bulk && qh->ring.next != &musb->out_bulk), then
  1009. * we have a candidate... NAKing is *NOT* an error
  1010. */
  1011. musb_ep_select(mbase, epnum);
  1012. musb_writew(epio, MUSB_TXCSR,
  1013. MUSB_TXCSR_H_WZC_BITS
  1014. | MUSB_TXCSR_TXPKTRDY);
  1015. return;
  1016. }
  1017. if (status) {
  1018. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  1019. dma->status = MUSB_DMA_STATUS_CORE_ABORT;
  1020. (void) musb->dma_controller->channel_abort(dma);
  1021. }
  1022. /* do the proper sequence to abort the transfer in the
  1023. * usb core; the dma engine should already be stopped.
  1024. */
  1025. musb_h_tx_flush_fifo(hw_ep);
  1026. tx_csr &= ~(MUSB_TXCSR_AUTOSET
  1027. | MUSB_TXCSR_DMAENAB
  1028. | MUSB_TXCSR_H_ERROR
  1029. | MUSB_TXCSR_H_RXSTALL
  1030. | MUSB_TXCSR_H_NAKTIMEOUT
  1031. );
  1032. musb_ep_select(mbase, epnum);
  1033. musb_writew(epio, MUSB_TXCSR, tx_csr);
  1034. /* REVISIT may need to clear FLUSHFIFO ... */
  1035. musb_writew(epio, MUSB_TXCSR, tx_csr);
  1036. musb_writeb(epio, MUSB_TXINTERVAL, 0);
  1037. done = true;
  1038. }
  1039. /* second cppi case */
  1040. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  1041. dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
  1042. return;
  1043. }
  1044. if (is_dma_capable() && dma && !status) {
  1045. /*
  1046. * DMA has completed. But if we're using DMA mode 1 (multi
  1047. * packet DMA), we need a terminal TXPKTRDY interrupt before
  1048. * we can consider this transfer completed, lest we trash
  1049. * its last packet when writing the next URB's data. So we
  1050. * switch back to mode 0 to get that interrupt; we'll come
  1051. * back here once it happens.
  1052. */
  1053. if (tx_csr & MUSB_TXCSR_DMAMODE) {
  1054. /*
  1055. * We shouldn't clear DMAMODE with DMAENAB set; so
  1056. * clear them in a safe order. That should be OK
  1057. * once TXPKTRDY has been set (and I've never seen
  1058. * it being 0 at this moment -- DMA interrupt latency
  1059. * is significant) but if it hasn't been then we have
  1060. * no choice but to stop being polite and ignore the
  1061. * programmer's guide... :-)
  1062. *
  1063. * Note that we must write TXCSR with TXPKTRDY cleared
  1064. * in order not to re-trigger the packet send (this bit
  1065. * can't be cleared by CPU), and there's another caveat:
  1066. * TXPKTRDY may be set shortly and then cleared in the
  1067. * double-buffered FIFO mode, so we do an extra TXCSR
  1068. * read for debouncing...
  1069. */
  1070. tx_csr &= musb_readw(epio, MUSB_TXCSR);
  1071. if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
  1072. tx_csr &= ~(MUSB_TXCSR_DMAENAB |
  1073. MUSB_TXCSR_TXPKTRDY);
  1074. musb_writew(epio, MUSB_TXCSR,
  1075. tx_csr | MUSB_TXCSR_H_WZC_BITS);
  1076. }
  1077. tx_csr &= ~(MUSB_TXCSR_DMAMODE |
  1078. MUSB_TXCSR_TXPKTRDY);
  1079. musb_writew(epio, MUSB_TXCSR,
  1080. tx_csr | MUSB_TXCSR_H_WZC_BITS);
  1081. /*
  1082. * There is no guarantee that we'll get an interrupt
  1083. * after clearing DMAMODE as we might have done this
  1084. * too late (after TXPKTRDY was cleared by controller).
  1085. * Re-read TXCSR as we have spoiled its previous value.
  1086. */
  1087. tx_csr = musb_readw(epio, MUSB_TXCSR);
  1088. }
  1089. /*
  1090. * We may get here from a DMA completion or TXPKTRDY interrupt.
  1091. * In any case, we must check the FIFO status here and bail out
  1092. * only if the FIFO still has data -- that should prevent the
  1093. * "missed" TXPKTRDY interrupts and deal with double-buffered
  1094. * FIFO mode too...
  1095. */
  1096. if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
  1097. dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
  1098. "CSR %04x\n", tx_csr);
  1099. return;
  1100. }
  1101. }
  1102. if (!status || dma || usb_pipeisoc(pipe)) {
  1103. if (dma)
  1104. length = dma->actual_len;
  1105. else
  1106. length = qh->segsize;
  1107. qh->offset += length;
  1108. if (usb_pipeisoc(pipe)) {
  1109. #ifndef __UBOOT__
  1110. struct usb_iso_packet_descriptor *d;
  1111. d = urb->iso_frame_desc + qh->iso_idx;
  1112. d->actual_length = length;
  1113. d->status = status;
  1114. if (++qh->iso_idx >= urb->number_of_packets) {
  1115. done = true;
  1116. } else {
  1117. d++;
  1118. offset = d->offset;
  1119. length = d->length;
  1120. }
  1121. #endif
  1122. } else if (dma && urb->transfer_buffer_length == qh->offset) {
  1123. done = true;
  1124. } else {
  1125. /* see if we need to send more data, or ZLP */
  1126. if (qh->segsize < qh->maxpacket)
  1127. done = true;
  1128. else if (qh->offset == urb->transfer_buffer_length
  1129. && !(urb->transfer_flags
  1130. & URB_ZERO_PACKET))
  1131. done = true;
  1132. if (!done) {
  1133. offset = qh->offset;
  1134. length = urb->transfer_buffer_length - offset;
  1135. transfer_pending = true;
  1136. }
  1137. }
  1138. }
  1139. /* urb->status != -EINPROGRESS means request has been faulted,
  1140. * so we must abort this transfer after cleanup
  1141. */
  1142. if (urb->status != -EINPROGRESS) {
  1143. done = true;
  1144. if (status == 0)
  1145. status = urb->status;
  1146. }
  1147. if (done) {
  1148. /* set status */
  1149. urb->status = status;
  1150. urb->actual_length = qh->offset;
  1151. musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
  1152. return;
  1153. } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
  1154. if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
  1155. offset, length)) {
  1156. if (is_cppi_enabled() || tusb_dma_omap())
  1157. musb_h_tx_dma_start(hw_ep);
  1158. return;
  1159. }
  1160. } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
  1161. dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
  1162. return;
  1163. }
  1164. /*
  1165. * PIO: start next packet in this URB.
  1166. *
  1167. * REVISIT: some docs say that when hw_ep->tx_double_buffered,
  1168. * (and presumably, FIFO is not half-full) we should write *two*
  1169. * packets before updating TXCSR; other docs disagree...
  1170. */
  1171. if (length > qh->maxpacket)
  1172. length = qh->maxpacket;
  1173. /* Unmap the buffer so that CPU can use it */
  1174. usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
  1175. musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
  1176. qh->segsize = length;
  1177. musb_ep_select(mbase, epnum);
  1178. musb_writew(epio, MUSB_TXCSR,
  1179. MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
  1180. }
  1181. #ifdef CONFIG_USB_INVENTRA_DMA
  1182. /* Host side RX (IN) using Mentor DMA works as follows:
  1183. submit_urb ->
  1184. - if queue was empty, ProgramEndpoint
  1185. - first IN token is sent out (by setting ReqPkt)
  1186. LinuxIsr -> RxReady()
  1187. /\ => first packet is received
  1188. | - Set in mode 0 (DmaEnab, ~ReqPkt)
  1189. | -> DMA Isr (transfer complete) -> RxReady()
  1190. | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
  1191. | - if urb not complete, send next IN token (ReqPkt)
  1192. | | else complete urb.
  1193. | |
  1194. ---------------------------
  1195. *
  1196. * Nuances of mode 1:
  1197. * For short packets, no ack (+RxPktRdy) is sent automatically
  1198. * (even if AutoClear is ON)
  1199. * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
  1200. * automatically => major problem, as collecting the next packet becomes
  1201. * difficult. Hence mode 1 is not used.
  1202. *
  1203. * REVISIT
  1204. * All we care about at this driver level is that
  1205. * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
  1206. * (b) termination conditions are: short RX, or buffer full;
  1207. * (c) fault modes include
  1208. * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
  1209. * (and that endpoint's dma queue stops immediately)
  1210. * - overflow (full, PLUS more bytes in the terminal packet)
  1211. *
  1212. * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
  1213. * thus be a great candidate for using mode 1 ... for all but the
  1214. * last packet of one URB's transfer.
  1215. */
  1216. #endif
  1217. /* Schedule next QH from musb->in_bulk and move the current qh to
  1218. * the end; avoids starvation for other endpoints.
  1219. */
  1220. static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
  1221. {
  1222. struct dma_channel *dma;
  1223. struct urb *urb;
  1224. void __iomem *mbase = musb->mregs;
  1225. void __iomem *epio = ep->regs;
  1226. struct musb_qh *cur_qh, *next_qh;
  1227. u16 rx_csr;
  1228. musb_ep_select(mbase, ep->epnum);
  1229. dma = is_dma_capable() ? ep->rx_channel : NULL;
  1230. /* clear nak timeout bit */
  1231. rx_csr = musb_readw(epio, MUSB_RXCSR);
  1232. rx_csr |= MUSB_RXCSR_H_WZC_BITS;
  1233. rx_csr &= ~MUSB_RXCSR_DATAERROR;
  1234. musb_writew(epio, MUSB_RXCSR, rx_csr);
  1235. cur_qh = first_qh(&musb->in_bulk);
  1236. if (cur_qh) {
  1237. urb = next_urb(cur_qh);
  1238. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  1239. dma->status = MUSB_DMA_STATUS_CORE_ABORT;
  1240. musb->dma_controller->channel_abort(dma);
  1241. urb->actual_length += dma->actual_len;
  1242. dma->actual_len = 0L;
  1243. }
  1244. musb_save_toggle(cur_qh, 1, urb);
  1245. /* move cur_qh to end of queue */
  1246. list_move_tail(&cur_qh->ring, &musb->in_bulk);
  1247. /* get the next qh from musb->in_bulk */
  1248. next_qh = first_qh(&musb->in_bulk);
  1249. /* set rx_reinit and schedule the next qh */
  1250. ep->rx_reinit = 1;
  1251. musb_start_urb(musb, 1, next_qh);
  1252. }
  1253. }
  1254. /*
  1255. * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
  1256. * and high-bandwidth IN transfer cases.
  1257. */
  1258. void musb_host_rx(struct musb *musb, u8 epnum)
  1259. {
  1260. struct urb *urb;
  1261. struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
  1262. void __iomem *epio = hw_ep->regs;
  1263. struct musb_qh *qh = hw_ep->in_qh;
  1264. size_t xfer_len;
  1265. void __iomem *mbase = musb->mregs;
  1266. int pipe;
  1267. u16 rx_csr, val;
  1268. bool iso_err = false;
  1269. bool done = false;
  1270. u32 status;
  1271. struct dma_channel *dma;
  1272. musb_ep_select(mbase, epnum);
  1273. urb = next_urb(qh);
  1274. dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
  1275. status = 0;
  1276. xfer_len = 0;
  1277. rx_csr = musb_readw(epio, MUSB_RXCSR);
  1278. val = rx_csr;
  1279. if (unlikely(!urb)) {
  1280. /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
  1281. * usbtest #11 (unlinks) triggers it regularly, sometimes
  1282. * with fifo full. (Only with DMA??)
  1283. */
  1284. dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
  1285. musb_readw(epio, MUSB_RXCOUNT));
  1286. musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
  1287. return;
  1288. }
  1289. pipe = urb->pipe;
  1290. dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
  1291. epnum, rx_csr, urb->actual_length,
  1292. dma ? dma->actual_len : 0);
  1293. /* check for errors, concurrent stall & unlink is not really
  1294. * handled yet! */
  1295. if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
  1296. dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
  1297. /* stall; record URB status */
  1298. status = -EPIPE;
  1299. } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
  1300. dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
  1301. status = -EPROTO;
  1302. musb_writeb(epio, MUSB_RXINTERVAL, 0);
  1303. } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
  1304. if (USB_ENDPOINT_XFER_ISOC != qh->type) {
  1305. dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
  1306. /* NOTE: NAKing is *NOT* an error, so we want to
  1307. * continue. Except ... if there's a request for
  1308. * another QH, use that instead of starving it.
  1309. *
  1310. * Devices like Ethernet and serial adapters keep
  1311. * reads posted at all times, which will starve
  1312. * other devices without this logic.
  1313. */
  1314. if (usb_pipebulk(urb->pipe)
  1315. && qh->mux == 1
  1316. && !list_is_singular(&musb->in_bulk)) {
  1317. musb_bulk_rx_nak_timeout(musb, hw_ep);
  1318. return;
  1319. }
  1320. musb_ep_select(mbase, epnum);
  1321. rx_csr |= MUSB_RXCSR_H_WZC_BITS;
  1322. rx_csr &= ~MUSB_RXCSR_DATAERROR;
  1323. musb_writew(epio, MUSB_RXCSR, rx_csr);
  1324. goto finish;
  1325. } else {
  1326. dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
  1327. /* packet error reported later */
  1328. iso_err = true;
  1329. }
  1330. } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
  1331. dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
  1332. epnum);
  1333. status = -EPROTO;
  1334. }
  1335. /* faults abort the transfer */
  1336. if (status) {
  1337. /* clean up dma and collect transfer count */
  1338. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  1339. dma->status = MUSB_DMA_STATUS_CORE_ABORT;
  1340. (void) musb->dma_controller->channel_abort(dma);
  1341. xfer_len = dma->actual_len;
  1342. }
  1343. musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
  1344. musb_writeb(epio, MUSB_RXINTERVAL, 0);
  1345. done = true;
  1346. goto finish;
  1347. }
  1348. if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
  1349. /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
  1350. ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
  1351. goto finish;
  1352. }
  1353. /* thorough shutdown for now ... given more precise fault handling
  1354. * and better queueing support, we might keep a DMA pipeline going
  1355. * while processing this irq for earlier completions.
  1356. */
  1357. /* FIXME this is _way_ too much in-line logic for Mentor DMA */
  1358. #ifndef CONFIG_USB_INVENTRA_DMA
  1359. if (rx_csr & MUSB_RXCSR_H_REQPKT) {
  1360. /* REVISIT this happened for a while on some short reads...
  1361. * the cleanup still needs investigation... looks bad...
  1362. * and also duplicates dma cleanup code above ... plus,
  1363. * shouldn't this be the "half full" double buffer case?
  1364. */
  1365. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  1366. dma->status = MUSB_DMA_STATUS_CORE_ABORT;
  1367. (void) musb->dma_controller->channel_abort(dma);
  1368. xfer_len = dma->actual_len;
  1369. done = true;
  1370. }
  1371. dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
  1372. xfer_len, dma ? ", dma" : "");
  1373. rx_csr &= ~MUSB_RXCSR_H_REQPKT;
  1374. musb_ep_select(mbase, epnum);
  1375. musb_writew(epio, MUSB_RXCSR,
  1376. MUSB_RXCSR_H_WZC_BITS | rx_csr);
  1377. }
  1378. #endif
  1379. if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
  1380. xfer_len = dma->actual_len;
  1381. val &= ~(MUSB_RXCSR_DMAENAB
  1382. | MUSB_RXCSR_H_AUTOREQ
  1383. | MUSB_RXCSR_AUTOCLEAR
  1384. | MUSB_RXCSR_RXPKTRDY);
  1385. musb_writew(hw_ep->regs, MUSB_RXCSR, val);
  1386. #ifdef CONFIG_USB_INVENTRA_DMA
  1387. if (usb_pipeisoc(pipe)) {
  1388. struct usb_iso_packet_descriptor *d;
  1389. d = urb->iso_frame_desc + qh->iso_idx;
  1390. d->actual_length = xfer_len;
  1391. /* even if there was an error, we did the dma
  1392. * for iso_frame_desc->length
  1393. */
  1394. if (d->status != -EILSEQ && d->status != -EOVERFLOW)
  1395. d->status = 0;
  1396. if (++qh->iso_idx >= urb->number_of_packets)
  1397. done = true;
  1398. else
  1399. done = false;
  1400. } else {
  1401. /* done if urb buffer is full or short packet is recd */
  1402. done = (urb->actual_length + xfer_len >=
  1403. urb->transfer_buffer_length
  1404. || dma->actual_len < qh->maxpacket);
  1405. }
  1406. /* send IN token for next packet, without AUTOREQ */
  1407. if (!done) {
  1408. val |= MUSB_RXCSR_H_REQPKT;
  1409. musb_writew(epio, MUSB_RXCSR,
  1410. MUSB_RXCSR_H_WZC_BITS | val);
  1411. }
  1412. dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
  1413. done ? "off" : "reset",
  1414. musb_readw(epio, MUSB_RXCSR),
  1415. musb_readw(epio, MUSB_RXCOUNT));
  1416. #else
  1417. done = true;
  1418. #endif
  1419. } else if (urb->status == -EINPROGRESS) {
  1420. /* if no errors, be sure a packet is ready for unloading */
  1421. if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
  1422. status = -EPROTO;
  1423. ERR("Rx interrupt with no errors or packet!\n");
  1424. /* FIXME this is another "SHOULD NEVER HAPPEN" */
  1425. /* SCRUB (RX) */
  1426. /* do the proper sequence to abort the transfer */
  1427. musb_ep_select(mbase, epnum);
  1428. val &= ~MUSB_RXCSR_H_REQPKT;
  1429. musb_writew(epio, MUSB_RXCSR, val);
  1430. goto finish;
  1431. }
  1432. /* we are expecting IN packets */
  1433. #ifdef CONFIG_USB_INVENTRA_DMA
  1434. if (dma) {
  1435. struct dma_controller *c;
  1436. u16 rx_count;
  1437. int ret, length;
  1438. dma_addr_t buf;
  1439. rx_count = musb_readw(epio, MUSB_RXCOUNT);
  1440. dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n",
  1441. epnum, rx_count,
  1442. urb->transfer_dma
  1443. + urb->actual_length,
  1444. qh->offset,
  1445. urb->transfer_buffer_length);
  1446. c = musb->dma_controller;
  1447. if (usb_pipeisoc(pipe)) {
  1448. int d_status = 0;
  1449. struct usb_iso_packet_descriptor *d;
  1450. d = urb->iso_frame_desc + qh->iso_idx;
  1451. if (iso_err) {
  1452. d_status = -EILSEQ;
  1453. urb->error_count++;
  1454. }
  1455. if (rx_count > d->length) {
  1456. if (d_status == 0) {
  1457. d_status = -EOVERFLOW;
  1458. urb->error_count++;
  1459. }
  1460. dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
  1461. rx_count, d->length);
  1462. length = d->length;
  1463. } else
  1464. length = rx_count;
  1465. d->status = d_status;
  1466. buf = urb->transfer_dma + d->offset;
  1467. } else {
  1468. length = rx_count;
  1469. buf = urb->transfer_dma +
  1470. urb->actual_length;
  1471. }
  1472. dma->desired_mode = 0;
  1473. #ifdef USE_MODE1
  1474. /* because of the issue below, mode 1 will
  1475. * only rarely behave with correct semantics.
  1476. */
  1477. if ((urb->transfer_flags &
  1478. URB_SHORT_NOT_OK)
  1479. && (urb->transfer_buffer_length -
  1480. urb->actual_length)
  1481. > qh->maxpacket)
  1482. dma->desired_mode = 1;
  1483. if (rx_count < hw_ep->max_packet_sz_rx) {
  1484. length = rx_count;
  1485. dma->desired_mode = 0;
  1486. } else {
  1487. length = urb->transfer_buffer_length;
  1488. }
  1489. #endif
  1490. /* Disadvantage of using mode 1:
  1491. * It's basically usable only for mass storage class; essentially all
  1492. * other protocols also terminate transfers on short packets.
  1493. *
  1494. * Details:
  1495. * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
  1496. * If you try to use mode 1 for (transfer_buffer_length - 512), and try
  1497. * to use the extra IN token to grab the last packet using mode 0, then
  1498. * the problem is that you cannot be sure when the device will send the
  1499. * last packet and RxPktRdy set. Sometimes the packet is recd too soon
  1500. * such that it gets lost when RxCSR is re-set at the end of the mode 1
  1501. * transfer, while sometimes it is recd just a little late so that if you
  1502. * try to configure for mode 0 soon after the mode 1 transfer is
  1503. * completed, you will find rxcount 0. Okay, so you might think why not
  1504. * wait for an interrupt when the pkt is recd. Well, you won't get any!
  1505. */
  1506. val = musb_readw(epio, MUSB_RXCSR);
  1507. val &= ~MUSB_RXCSR_H_REQPKT;
  1508. if (dma->desired_mode == 0)
  1509. val &= ~MUSB_RXCSR_H_AUTOREQ;
  1510. else
  1511. val |= MUSB_RXCSR_H_AUTOREQ;
  1512. val |= MUSB_RXCSR_DMAENAB;
  1513. /* autoclear shouldn't be set in high bandwidth */
  1514. if (qh->hb_mult == 1)
  1515. val |= MUSB_RXCSR_AUTOCLEAR;
  1516. musb_writew(epio, MUSB_RXCSR,
  1517. MUSB_RXCSR_H_WZC_BITS | val);
  1518. /* REVISIT if when actual_length != 0,
  1519. * transfer_buffer_length needs to be
  1520. * adjusted first...
  1521. */
  1522. ret = c->channel_program(
  1523. dma, qh->maxpacket,
  1524. dma->desired_mode, buf, length);
  1525. if (!ret) {
  1526. c->channel_release(dma);
  1527. hw_ep->rx_channel = NULL;
  1528. dma = NULL;
  1529. val = musb_readw(epio, MUSB_RXCSR);
  1530. val &= ~(MUSB_RXCSR_DMAENAB
  1531. | MUSB_RXCSR_H_AUTOREQ
  1532. | MUSB_RXCSR_AUTOCLEAR);
  1533. musb_writew(epio, MUSB_RXCSR, val);
  1534. }
  1535. }
  1536. #endif /* Mentor DMA */
  1537. if (!dma) {
  1538. /* Unmap the buffer so that CPU can use it */
  1539. usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
  1540. done = musb_host_packet_rx(musb, urb,
  1541. epnum, iso_err);
  1542. dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
  1543. }
  1544. }
  1545. finish:
  1546. urb->actual_length += xfer_len;
  1547. qh->offset += xfer_len;
  1548. if (done) {
  1549. if (urb->status == -EINPROGRESS)
  1550. urb->status = status;
  1551. musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
  1552. }
  1553. }
  1554. /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
  1555. * the software schedule associates multiple such nodes with a given
  1556. * host side hardware endpoint + direction; scheduling may activate
  1557. * that hardware endpoint.
  1558. */
  1559. static int musb_schedule(
  1560. struct musb *musb,
  1561. struct musb_qh *qh,
  1562. int is_in)
  1563. {
  1564. int idle;
  1565. int best_diff;
  1566. int best_end, epnum;
  1567. struct musb_hw_ep *hw_ep = NULL;
  1568. struct list_head *head = NULL;
  1569. u8 toggle;
  1570. u8 txtype;
  1571. struct urb *urb = next_urb(qh);
  1572. /* use fixed hardware for control and bulk */
  1573. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  1574. head = &musb->control;
  1575. hw_ep = musb->control_ep;
  1576. goto success;
  1577. }
  1578. /* else, periodic transfers get muxed to other endpoints */
  1579. /*
  1580. * We know this qh hasn't been scheduled, so all we need to do
  1581. * is choose which hardware endpoint to put it on ...
  1582. *
  1583. * REVISIT what we really want here is a regular schedule tree
  1584. * like e.g. OHCI uses.
  1585. */
  1586. best_diff = 4096;
  1587. best_end = -1;
  1588. for (epnum = 1, hw_ep = musb->endpoints + 1;
  1589. epnum < musb->nr_endpoints;
  1590. epnum++, hw_ep++) {
  1591. int diff;
  1592. if (musb_ep_get_qh(hw_ep, is_in) != NULL)
  1593. continue;
  1594. if (hw_ep == musb->bulk_ep)
  1595. continue;
  1596. if (is_in)
  1597. diff = hw_ep->max_packet_sz_rx;
  1598. else
  1599. diff = hw_ep->max_packet_sz_tx;
  1600. diff -= (qh->maxpacket * qh->hb_mult);
  1601. if (diff >= 0 && best_diff > diff) {
  1602. /*
  1603. * Mentor controller has a bug in that if we schedule
  1604. * a BULK Tx transfer on an endpoint that had earlier
  1605. * handled ISOC then the BULK transfer has to start on
  1606. * a zero toggle. If the BULK transfer starts on a 1
  1607. * toggle then this transfer will fail as the mentor
  1608. * controller starts the Bulk transfer on a 0 toggle
  1609. * irrespective of the programming of the toggle bits
  1610. * in the TXCSR register. Check for this condition
  1611. * while allocating the EP for a Tx Bulk transfer. If
  1612. * so skip this EP.
  1613. */
  1614. hw_ep = musb->endpoints + epnum;
  1615. toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
  1616. txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
  1617. >> 4) & 0x3;
  1618. if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
  1619. toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
  1620. continue;
  1621. best_diff = diff;
  1622. best_end = epnum;
  1623. }
  1624. }
  1625. /* use bulk reserved ep1 if no other ep is free */
  1626. if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
  1627. hw_ep = musb->bulk_ep;
  1628. if (is_in)
  1629. head = &musb->in_bulk;
  1630. else
  1631. head = &musb->out_bulk;
  1632. /* Enable bulk RX NAK timeout scheme when bulk requests are
  1633. * multiplexed. This scheme doen't work in high speed to full
  1634. * speed scenario as NAK interrupts are not coming from a
  1635. * full speed device connected to a high speed device.
  1636. * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
  1637. * 4 (8 frame or 8ms) for FS device.
  1638. */
  1639. if (is_in && qh->dev)
  1640. qh->intv_reg =
  1641. (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
  1642. goto success;
  1643. } else if (best_end < 0) {
  1644. return -ENOSPC;
  1645. }
  1646. idle = 1;
  1647. qh->mux = 0;
  1648. hw_ep = musb->endpoints + best_end;
  1649. dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
  1650. success:
  1651. if (head) {
  1652. idle = list_empty(head);
  1653. list_add_tail(&qh->ring, head);
  1654. qh->mux = 1;
  1655. }
  1656. qh->hw_ep = hw_ep;
  1657. qh->hep->hcpriv = qh;
  1658. if (idle)
  1659. musb_start_urb(musb, is_in, qh);
  1660. return 0;
  1661. }
  1662. #ifdef __UBOOT__
  1663. /* check if transaction translator is needed for device */
  1664. static int tt_needed(struct musb *musb, struct usb_device *dev)
  1665. {
  1666. if ((musb_readb(musb->mregs, MUSB_POWER) & MUSB_POWER_HSMODE) &&
  1667. (dev->speed < USB_SPEED_HIGH))
  1668. return 1;
  1669. return 0;
  1670. }
  1671. #endif
  1672. #ifndef __UBOOT__
  1673. static int musb_urb_enqueue(
  1674. #else
  1675. int musb_urb_enqueue(
  1676. #endif
  1677. struct usb_hcd *hcd,
  1678. struct urb *urb,
  1679. gfp_t mem_flags)
  1680. {
  1681. unsigned long flags;
  1682. struct musb *musb = hcd_to_musb(hcd);
  1683. struct usb_host_endpoint *hep = urb->ep;
  1684. struct musb_qh *qh;
  1685. struct usb_endpoint_descriptor *epd = &hep->desc;
  1686. int ret;
  1687. unsigned type_reg;
  1688. unsigned interval;
  1689. /* host role must be active */
  1690. if (!is_host_active(musb) || !musb->is_active)
  1691. return -ENODEV;
  1692. spin_lock_irqsave(&musb->lock, flags);
  1693. ret = usb_hcd_link_urb_to_ep(hcd, urb);
  1694. qh = ret ? NULL : hep->hcpriv;
  1695. if (qh)
  1696. urb->hcpriv = qh;
  1697. spin_unlock_irqrestore(&musb->lock, flags);
  1698. /* DMA mapping was already done, if needed, and this urb is on
  1699. * hep->urb_list now ... so we're done, unless hep wasn't yet
  1700. * scheduled onto a live qh.
  1701. *
  1702. * REVISIT best to keep hep->hcpriv valid until the endpoint gets
  1703. * disabled, testing for empty qh->ring and avoiding qh setup costs
  1704. * except for the first urb queued after a config change.
  1705. */
  1706. if (qh || ret)
  1707. return ret;
  1708. /* Allocate and initialize qh, minimizing the work done each time
  1709. * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
  1710. *
  1711. * REVISIT consider a dedicated qh kmem_cache, so it's harder
  1712. * for bugs in other kernel code to break this driver...
  1713. */
  1714. qh = kzalloc(sizeof *qh, mem_flags);
  1715. if (!qh) {
  1716. spin_lock_irqsave(&musb->lock, flags);
  1717. usb_hcd_unlink_urb_from_ep(hcd, urb);
  1718. spin_unlock_irqrestore(&musb->lock, flags);
  1719. return -ENOMEM;
  1720. }
  1721. qh->hep = hep;
  1722. qh->dev = urb->dev;
  1723. INIT_LIST_HEAD(&qh->ring);
  1724. qh->is_ready = 1;
  1725. qh->maxpacket = usb_endpoint_maxp(epd);
  1726. qh->type = usb_endpoint_type(epd);
  1727. /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
  1728. * Some musb cores don't support high bandwidth ISO transfers; and
  1729. * we don't (yet!) support high bandwidth interrupt transfers.
  1730. */
  1731. qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
  1732. if (qh->hb_mult > 1) {
  1733. int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
  1734. if (ok)
  1735. ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
  1736. || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
  1737. if (!ok) {
  1738. ret = -EMSGSIZE;
  1739. goto done;
  1740. }
  1741. qh->maxpacket &= 0x7ff;
  1742. }
  1743. qh->epnum = usb_endpoint_num(epd);
  1744. /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
  1745. qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
  1746. /* precompute rxtype/txtype/type0 register */
  1747. type_reg = (qh->type << 4) | qh->epnum;
  1748. switch (urb->dev->speed) {
  1749. case USB_SPEED_LOW:
  1750. type_reg |= 0xc0;
  1751. break;
  1752. case USB_SPEED_FULL:
  1753. type_reg |= 0x80;
  1754. break;
  1755. default:
  1756. type_reg |= 0x40;
  1757. }
  1758. qh->type_reg = type_reg;
  1759. /* Precompute RXINTERVAL/TXINTERVAL register */
  1760. switch (qh->type) {
  1761. case USB_ENDPOINT_XFER_INT:
  1762. /*
  1763. * Full/low speeds use the linear encoding,
  1764. * high speed uses the logarithmic encoding.
  1765. */
  1766. if (urb->dev->speed <= USB_SPEED_FULL) {
  1767. interval = max_t(u8, epd->bInterval, 1);
  1768. break;
  1769. }
  1770. /* FALLTHROUGH */
  1771. case USB_ENDPOINT_XFER_ISOC:
  1772. /* ISO always uses logarithmic encoding */
  1773. interval = min_t(u8, epd->bInterval, 16);
  1774. break;
  1775. default:
  1776. /* REVISIT we actually want to use NAK limits, hinting to the
  1777. * transfer scheduling logic to try some other qh, e.g. try
  1778. * for 2 msec first:
  1779. *
  1780. * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
  1781. *
  1782. * The downside of disabling this is that transfer scheduling
  1783. * gets VERY unfair for nonperiodic transfers; a misbehaving
  1784. * peripheral could make that hurt. That's perfectly normal
  1785. * for reads from network or serial adapters ... so we have
  1786. * partial NAKlimit support for bulk RX.
  1787. *
  1788. * The upside of disabling it is simpler transfer scheduling.
  1789. */
  1790. interval = 0;
  1791. }
  1792. qh->intv_reg = interval;
  1793. /* precompute addressing for external hub/tt ports */
  1794. if (musb->is_multipoint) {
  1795. #ifndef __UBOOT__
  1796. struct usb_device *parent = urb->dev->parent;
  1797. #else
  1798. struct usb_device *parent = usb_dev_get_parent(urb->dev);
  1799. #endif
  1800. #ifndef __UBOOT__
  1801. if (parent != hcd->self.root_hub) {
  1802. #else
  1803. if (parent) {
  1804. #endif
  1805. qh->h_addr_reg = (u8) parent->devnum;
  1806. #ifndef __UBOOT__
  1807. /* set up tt info if needed */
  1808. if (urb->dev->tt) {
  1809. qh->h_port_reg = (u8) urb->dev->ttport;
  1810. if (urb->dev->tt->hub)
  1811. qh->h_addr_reg =
  1812. (u8) urb->dev->tt->hub->devnum;
  1813. if (urb->dev->tt->multi)
  1814. qh->h_addr_reg |= 0x80;
  1815. }
  1816. #else
  1817. if (tt_needed(musb, urb->dev)) {
  1818. uint8_t portnr = 0;
  1819. uint8_t hubaddr = 0;
  1820. usb_find_usb2_hub_address_port(urb->dev,
  1821. &hubaddr,
  1822. &portnr);
  1823. qh->h_addr_reg = hubaddr;
  1824. qh->h_port_reg = portnr;
  1825. }
  1826. #endif
  1827. }
  1828. }
  1829. /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
  1830. * until we get real dma queues (with an entry for each urb/buffer),
  1831. * we only have work to do in the former case.
  1832. */
  1833. spin_lock_irqsave(&musb->lock, flags);
  1834. if (hep->hcpriv) {
  1835. /* some concurrent activity submitted another urb to hep...
  1836. * odd, rare, error prone, but legal.
  1837. */
  1838. kfree(qh);
  1839. qh = NULL;
  1840. ret = 0;
  1841. } else
  1842. ret = musb_schedule(musb, qh,
  1843. epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
  1844. if (ret == 0) {
  1845. urb->hcpriv = qh;
  1846. /* FIXME set urb->start_frame for iso/intr, it's tested in
  1847. * musb_start_urb(), but otherwise only konicawc cares ...
  1848. */
  1849. }
  1850. spin_unlock_irqrestore(&musb->lock, flags);
  1851. done:
  1852. if (ret != 0) {
  1853. spin_lock_irqsave(&musb->lock, flags);
  1854. usb_hcd_unlink_urb_from_ep(hcd, urb);
  1855. spin_unlock_irqrestore(&musb->lock, flags);
  1856. kfree(qh);
  1857. }
  1858. return ret;
  1859. }
  1860. /*
  1861. * abort a transfer that's at the head of a hardware queue.
  1862. * called with controller locked, irqs blocked
  1863. * that hardware queue advances to the next transfer, unless prevented
  1864. */
  1865. static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
  1866. {
  1867. struct musb_hw_ep *ep = qh->hw_ep;
  1868. struct musb *musb = ep->musb;
  1869. void __iomem *epio = ep->regs;
  1870. unsigned hw_end = ep->epnum;
  1871. void __iomem *regs = ep->musb->mregs;
  1872. int is_in = usb_pipein(urb->pipe);
  1873. int status = 0;
  1874. u16 csr;
  1875. musb_ep_select(regs, hw_end);
  1876. if (is_dma_capable()) {
  1877. struct dma_channel *dma;
  1878. dma = is_in ? ep->rx_channel : ep->tx_channel;
  1879. if (dma) {
  1880. status = ep->musb->dma_controller->channel_abort(dma);
  1881. dev_dbg(musb->controller,
  1882. "abort %cX%d DMA for urb %p --> %d\n",
  1883. is_in ? 'R' : 'T', ep->epnum,
  1884. urb, status);
  1885. urb->actual_length += dma->actual_len;
  1886. }
  1887. }
  1888. /* turn off DMA requests, discard state, stop polling ... */
  1889. if (ep->epnum && is_in) {
  1890. /* giveback saves bulk toggle */
  1891. csr = musb_h_flush_rxfifo(ep, 0);
  1892. /* REVISIT we still get an irq; should likely clear the
  1893. * endpoint's irq status here to avoid bogus irqs.
  1894. * clearing that status is platform-specific...
  1895. */
  1896. } else if (ep->epnum) {
  1897. musb_h_tx_flush_fifo(ep);
  1898. csr = musb_readw(epio, MUSB_TXCSR);
  1899. csr &= ~(MUSB_TXCSR_AUTOSET
  1900. | MUSB_TXCSR_DMAENAB
  1901. | MUSB_TXCSR_H_RXSTALL
  1902. | MUSB_TXCSR_H_NAKTIMEOUT
  1903. | MUSB_TXCSR_H_ERROR
  1904. | MUSB_TXCSR_TXPKTRDY);
  1905. musb_writew(epio, MUSB_TXCSR, csr);
  1906. /* REVISIT may need to clear FLUSHFIFO ... */
  1907. musb_writew(epio, MUSB_TXCSR, csr);
  1908. /* flush cpu writebuffer */
  1909. csr = musb_readw(epio, MUSB_TXCSR);
  1910. } else {
  1911. musb_h_ep0_flush_fifo(ep);
  1912. }
  1913. if (status == 0)
  1914. musb_advance_schedule(ep->musb, urb, ep, is_in);
  1915. return status;
  1916. }
  1917. #ifndef __UBOOT__
  1918. static int musb_urb_dequeue(
  1919. #else
  1920. int musb_urb_dequeue(
  1921. #endif
  1922. struct usb_hcd *hcd,
  1923. struct urb *urb,
  1924. int status)
  1925. {
  1926. struct musb *musb = hcd_to_musb(hcd);
  1927. struct musb_qh *qh;
  1928. unsigned long flags;
  1929. int is_in = usb_pipein(urb->pipe);
  1930. int ret;
  1931. dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
  1932. usb_pipedevice(urb->pipe),
  1933. usb_pipeendpoint(urb->pipe),
  1934. is_in ? "in" : "out");
  1935. spin_lock_irqsave(&musb->lock, flags);
  1936. ret = usb_hcd_check_unlink_urb(hcd, urb, status);
  1937. if (ret)
  1938. goto done;
  1939. qh = urb->hcpriv;
  1940. if (!qh)
  1941. goto done;
  1942. /*
  1943. * Any URB not actively programmed into endpoint hardware can be
  1944. * immediately given back; that's any URB not at the head of an
  1945. * endpoint queue, unless someday we get real DMA queues. And even
  1946. * if it's at the head, it might not be known to the hardware...
  1947. *
  1948. * Otherwise abort current transfer, pending DMA, etc.; urb->status
  1949. * has already been updated. This is a synchronous abort; it'd be
  1950. * OK to hold off until after some IRQ, though.
  1951. *
  1952. * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
  1953. */
  1954. if (!qh->is_ready
  1955. || urb->urb_list.prev != &qh->hep->urb_list
  1956. || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
  1957. int ready = qh->is_ready;
  1958. qh->is_ready = 0;
  1959. musb_giveback(musb, urb, 0);
  1960. qh->is_ready = ready;
  1961. /* If nothing else (usually musb_giveback) is using it
  1962. * and its URB list has emptied, recycle this qh.
  1963. */
  1964. if (ready && list_empty(&qh->hep->urb_list)) {
  1965. qh->hep->hcpriv = NULL;
  1966. list_del(&qh->ring);
  1967. kfree(qh);
  1968. }
  1969. } else
  1970. ret = musb_cleanup_urb(urb, qh);
  1971. done:
  1972. spin_unlock_irqrestore(&musb->lock, flags);
  1973. return ret;
  1974. }
  1975. #ifndef __UBOOT__
  1976. /* disable an endpoint */
  1977. static void
  1978. musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
  1979. {
  1980. u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
  1981. unsigned long flags;
  1982. struct musb *musb = hcd_to_musb(hcd);
  1983. struct musb_qh *qh;
  1984. struct urb *urb;
  1985. spin_lock_irqsave(&musb->lock, flags);
  1986. qh = hep->hcpriv;
  1987. if (qh == NULL)
  1988. goto exit;
  1989. /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
  1990. /* Kick the first URB off the hardware, if needed */
  1991. qh->is_ready = 0;
  1992. if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
  1993. urb = next_urb(qh);
  1994. /* make software (then hardware) stop ASAP */
  1995. if (!urb->unlinked)
  1996. urb->status = -ESHUTDOWN;
  1997. /* cleanup */
  1998. musb_cleanup_urb(urb, qh);
  1999. /* Then nuke all the others ... and advance the
  2000. * queue on hw_ep (e.g. bulk ring) when we're done.
  2001. */
  2002. while (!list_empty(&hep->urb_list)) {
  2003. urb = next_urb(qh);
  2004. urb->status = -ESHUTDOWN;
  2005. musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
  2006. }
  2007. } else {
  2008. /* Just empty the queue; the hardware is busy with
  2009. * other transfers, and since !qh->is_ready nothing
  2010. * will activate any of these as it advances.
  2011. */
  2012. while (!list_empty(&hep->urb_list))
  2013. musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
  2014. hep->hcpriv = NULL;
  2015. list_del(&qh->ring);
  2016. kfree(qh);
  2017. }
  2018. exit:
  2019. spin_unlock_irqrestore(&musb->lock, flags);
  2020. }
  2021. static int musb_h_get_frame_number(struct usb_hcd *hcd)
  2022. {
  2023. struct musb *musb = hcd_to_musb(hcd);
  2024. return musb_readw(musb->mregs, MUSB_FRAME);
  2025. }
  2026. static int musb_h_start(struct usb_hcd *hcd)
  2027. {
  2028. struct musb *musb = hcd_to_musb(hcd);
  2029. /* NOTE: musb_start() is called when the hub driver turns
  2030. * on port power, or when (OTG) peripheral starts.
  2031. */
  2032. hcd->state = HC_STATE_RUNNING;
  2033. musb->port1_status = 0;
  2034. return 0;
  2035. }
  2036. static void musb_h_stop(struct usb_hcd *hcd)
  2037. {
  2038. musb_stop(hcd_to_musb(hcd));
  2039. hcd->state = HC_STATE_HALT;
  2040. }
  2041. static int musb_bus_suspend(struct usb_hcd *hcd)
  2042. {
  2043. struct musb *musb = hcd_to_musb(hcd);
  2044. u8 devctl;
  2045. if (!is_host_active(musb))
  2046. return 0;
  2047. switch (musb->xceiv->state) {
  2048. case OTG_STATE_A_SUSPEND:
  2049. return 0;
  2050. case OTG_STATE_A_WAIT_VRISE:
  2051. /* ID could be grounded even if there's no device
  2052. * on the other end of the cable. NOTE that the
  2053. * A_WAIT_VRISE timers are messy with MUSB...
  2054. */
  2055. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  2056. if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
  2057. musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
  2058. break;
  2059. default:
  2060. break;
  2061. }
  2062. if (musb->is_active) {
  2063. WARNING("trying to suspend as %s while active\n",
  2064. otg_state_string(musb->xceiv->state));
  2065. return -EBUSY;
  2066. } else
  2067. return 0;
  2068. }
  2069. static int musb_bus_resume(struct usb_hcd *hcd)
  2070. {
  2071. /* resuming child port does the work */
  2072. return 0;
  2073. }
  2074. const struct hc_driver musb_hc_driver = {
  2075. .description = "musb-hcd",
  2076. .product_desc = "MUSB HDRC host driver",
  2077. .hcd_priv_size = sizeof(struct musb),
  2078. .flags = HCD_USB2 | HCD_MEMORY,
  2079. /* not using irq handler or reset hooks from usbcore, since
  2080. * those must be shared with peripheral code for OTG configs
  2081. */
  2082. .start = musb_h_start,
  2083. .stop = musb_h_stop,
  2084. .get_frame_number = musb_h_get_frame_number,
  2085. .urb_enqueue = musb_urb_enqueue,
  2086. .urb_dequeue = musb_urb_dequeue,
  2087. .endpoint_disable = musb_h_disable,
  2088. .hub_status_data = musb_hub_status_data,
  2089. .hub_control = musb_hub_control,
  2090. .bus_suspend = musb_bus_suspend,
  2091. .bus_resume = musb_bus_resume,
  2092. /* .start_port_reset = NULL, */
  2093. /* .hub_irq_enable = NULL, */
  2094. };
  2095. #endif