musb_gadget_ep0.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MUSB OTG peripheral driver ep0 handling
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
  9. */
  10. #ifndef __UBOOT__
  11. #include <log.h>
  12. #include <dm/device_compat.h>
  13. #include <linux/kernel.h>
  14. #include <linux/list.h>
  15. #include <linux/timer.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/device.h>
  18. #include <linux/interrupt.h>
  19. #else
  20. #include <common.h>
  21. #include <dm.h>
  22. #include <dm/device_compat.h>
  23. #include <asm/processor.h>
  24. #include "linux-compat.h"
  25. #endif
  26. #include "musb_core.h"
  27. /* ep0 is always musb->endpoints[0].ep_in */
  28. #define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
  29. /*
  30. * locking note: we use only the controller lock, for simpler correctness.
  31. * It's always held with IRQs blocked.
  32. *
  33. * It protects the ep0 request queue as well as ep0_state, not just the
  34. * controller and indexed registers. And that lock stays held unless it
  35. * needs to be dropped to allow reentering this driver ... like upcalls to
  36. * the gadget driver, or adjusting endpoint halt status.
  37. */
  38. static char *decode_ep0stage(u8 stage)
  39. {
  40. switch (stage) {
  41. case MUSB_EP0_STAGE_IDLE: return "idle";
  42. case MUSB_EP0_STAGE_SETUP: return "setup";
  43. case MUSB_EP0_STAGE_TX: return "in";
  44. case MUSB_EP0_STAGE_RX: return "out";
  45. case MUSB_EP0_STAGE_ACKWAIT: return "wait";
  46. case MUSB_EP0_STAGE_STATUSIN: return "in/status";
  47. case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
  48. default: return "?";
  49. }
  50. }
  51. /* handle a standard GET_STATUS request
  52. * Context: caller holds controller lock
  53. */
  54. static int service_tx_status_request(
  55. struct musb *musb,
  56. const struct usb_ctrlrequest *ctrlrequest)
  57. {
  58. void __iomem *mbase = musb->mregs;
  59. int handled = 1;
  60. u8 result[2], epnum = 0;
  61. const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  62. result[1] = 0;
  63. switch (recip) {
  64. case USB_RECIP_DEVICE:
  65. result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
  66. result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  67. if (musb->g.is_otg) {
  68. result[0] |= musb->g.b_hnp_enable
  69. << USB_DEVICE_B_HNP_ENABLE;
  70. result[0] |= musb->g.a_alt_hnp_support
  71. << USB_DEVICE_A_ALT_HNP_SUPPORT;
  72. result[0] |= musb->g.a_hnp_support
  73. << USB_DEVICE_A_HNP_SUPPORT;
  74. }
  75. break;
  76. case USB_RECIP_INTERFACE:
  77. result[0] = 0;
  78. break;
  79. case USB_RECIP_ENDPOINT: {
  80. int is_in;
  81. struct musb_ep *ep;
  82. u16 tmp;
  83. void __iomem *regs;
  84. epnum = (u8) ctrlrequest->wIndex;
  85. if (!epnum) {
  86. result[0] = 0;
  87. break;
  88. }
  89. is_in = epnum & USB_DIR_IN;
  90. if (is_in) {
  91. epnum &= 0x0f;
  92. ep = &musb->endpoints[epnum].ep_in;
  93. } else {
  94. ep = &musb->endpoints[epnum].ep_out;
  95. }
  96. regs = musb->endpoints[epnum].regs;
  97. if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
  98. handled = -EINVAL;
  99. break;
  100. }
  101. musb_ep_select(mbase, epnum);
  102. if (is_in)
  103. tmp = musb_readw(regs, MUSB_TXCSR)
  104. & MUSB_TXCSR_P_SENDSTALL;
  105. else
  106. tmp = musb_readw(regs, MUSB_RXCSR)
  107. & MUSB_RXCSR_P_SENDSTALL;
  108. musb_ep_select(mbase, 0);
  109. result[0] = tmp ? 1 : 0;
  110. } break;
  111. default:
  112. /* class, vendor, etc ... delegate */
  113. handled = 0;
  114. break;
  115. }
  116. /* fill up the fifo; caller updates csr0 */
  117. if (handled > 0) {
  118. u16 len = le16_to_cpu(ctrlrequest->wLength);
  119. if (len > 2)
  120. len = 2;
  121. musb_write_fifo(&musb->endpoints[0], len, result);
  122. }
  123. return handled;
  124. }
  125. /*
  126. * handle a control-IN request, the end0 buffer contains the current request
  127. * that is supposed to be a standard control request. Assumes the fifo to
  128. * be at least 2 bytes long.
  129. *
  130. * @return 0 if the request was NOT HANDLED,
  131. * < 0 when error
  132. * > 0 when the request is processed
  133. *
  134. * Context: caller holds controller lock
  135. */
  136. static int
  137. service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
  138. {
  139. int handled = 0; /* not handled */
  140. if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
  141. == USB_TYPE_STANDARD) {
  142. switch (ctrlrequest->bRequest) {
  143. case USB_REQ_GET_STATUS:
  144. handled = service_tx_status_request(musb,
  145. ctrlrequest);
  146. break;
  147. /* case USB_REQ_SYNC_FRAME: */
  148. default:
  149. break;
  150. }
  151. }
  152. return handled;
  153. }
  154. /*
  155. * Context: caller holds controller lock
  156. */
  157. static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
  158. {
  159. musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
  160. }
  161. /*
  162. * Tries to start B-device HNP negotiation if enabled via sysfs
  163. */
  164. static inline void musb_try_b_hnp_enable(struct musb *musb)
  165. {
  166. void __iomem *mbase = musb->mregs;
  167. u8 devctl;
  168. dev_dbg(musb->controller, "HNP: Setting HR\n");
  169. devctl = musb_readb(mbase, MUSB_DEVCTL);
  170. musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
  171. }
  172. /*
  173. * Handle all control requests with no DATA stage, including standard
  174. * requests such as:
  175. * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
  176. * always delegated to the gadget driver
  177. * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
  178. * always handled here, except for class/vendor/... features
  179. *
  180. * Context: caller holds controller lock
  181. */
  182. static int
  183. service_zero_data_request(struct musb *musb,
  184. struct usb_ctrlrequest *ctrlrequest)
  185. __releases(musb->lock)
  186. __acquires(musb->lock)
  187. {
  188. int handled = -EINVAL;
  189. void __iomem *mbase = musb->mregs;
  190. const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  191. /* the gadget driver handles everything except what we MUST handle */
  192. if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
  193. == USB_TYPE_STANDARD) {
  194. switch (ctrlrequest->bRequest) {
  195. case USB_REQ_SET_ADDRESS:
  196. /* change it after the status stage */
  197. musb->set_address = true;
  198. musb->address = (u8) (ctrlrequest->wValue & 0x7f);
  199. handled = 1;
  200. break;
  201. case USB_REQ_CLEAR_FEATURE:
  202. switch (recip) {
  203. case USB_RECIP_DEVICE:
  204. if (ctrlrequest->wValue
  205. != USB_DEVICE_REMOTE_WAKEUP)
  206. break;
  207. musb->may_wakeup = 0;
  208. handled = 1;
  209. break;
  210. case USB_RECIP_INTERFACE:
  211. break;
  212. case USB_RECIP_ENDPOINT:{
  213. const u8 epnum =
  214. ctrlrequest->wIndex & 0x0f;
  215. struct musb_ep *musb_ep;
  216. struct musb_hw_ep *ep;
  217. struct musb_request *request;
  218. void __iomem *regs;
  219. int is_in;
  220. u16 csr;
  221. if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
  222. ctrlrequest->wValue != USB_ENDPOINT_HALT)
  223. break;
  224. ep = musb->endpoints + epnum;
  225. regs = ep->regs;
  226. is_in = ctrlrequest->wIndex & USB_DIR_IN;
  227. if (is_in)
  228. musb_ep = &ep->ep_in;
  229. else
  230. musb_ep = &ep->ep_out;
  231. if (!musb_ep->desc)
  232. break;
  233. handled = 1;
  234. /* Ignore request if endpoint is wedged */
  235. if (musb_ep->wedged)
  236. break;
  237. musb_ep_select(mbase, epnum);
  238. if (is_in) {
  239. csr = musb_readw(regs, MUSB_TXCSR);
  240. csr |= MUSB_TXCSR_CLRDATATOG |
  241. MUSB_TXCSR_P_WZC_BITS;
  242. csr &= ~(MUSB_TXCSR_P_SENDSTALL |
  243. MUSB_TXCSR_P_SENTSTALL |
  244. MUSB_TXCSR_TXPKTRDY);
  245. musb_writew(regs, MUSB_TXCSR, csr);
  246. } else {
  247. csr = musb_readw(regs, MUSB_RXCSR);
  248. csr |= MUSB_RXCSR_CLRDATATOG |
  249. MUSB_RXCSR_P_WZC_BITS;
  250. csr &= ~(MUSB_RXCSR_P_SENDSTALL |
  251. MUSB_RXCSR_P_SENTSTALL);
  252. musb_writew(regs, MUSB_RXCSR, csr);
  253. }
  254. /* Maybe start the first request in the queue */
  255. request = next_request(musb_ep);
  256. if (!musb_ep->busy && request) {
  257. dev_dbg(musb->controller, "restarting the request\n");
  258. musb_ep_restart(musb, request);
  259. }
  260. /* select ep0 again */
  261. musb_ep_select(mbase, 0);
  262. } break;
  263. default:
  264. /* class, vendor, etc ... delegate */
  265. handled = 0;
  266. break;
  267. }
  268. break;
  269. case USB_REQ_SET_FEATURE:
  270. switch (recip) {
  271. case USB_RECIP_DEVICE:
  272. handled = 1;
  273. switch (ctrlrequest->wValue) {
  274. case USB_DEVICE_REMOTE_WAKEUP:
  275. musb->may_wakeup = 1;
  276. break;
  277. case USB_DEVICE_TEST_MODE:
  278. if (musb->g.speed != USB_SPEED_HIGH)
  279. goto stall;
  280. if (ctrlrequest->wIndex & 0xff)
  281. goto stall;
  282. switch (ctrlrequest->wIndex >> 8) {
  283. case 1:
  284. pr_debug("TEST_J\n");
  285. /* TEST_J */
  286. musb->test_mode_nr =
  287. MUSB_TEST_J;
  288. break;
  289. case 2:
  290. /* TEST_K */
  291. pr_debug("TEST_K\n");
  292. musb->test_mode_nr =
  293. MUSB_TEST_K;
  294. break;
  295. case 3:
  296. /* TEST_SE0_NAK */
  297. pr_debug("TEST_SE0_NAK\n");
  298. musb->test_mode_nr =
  299. MUSB_TEST_SE0_NAK;
  300. break;
  301. case 4:
  302. /* TEST_PACKET */
  303. pr_debug("TEST_PACKET\n");
  304. musb->test_mode_nr =
  305. MUSB_TEST_PACKET;
  306. break;
  307. case 0xc0:
  308. /* TEST_FORCE_HS */
  309. pr_debug("TEST_FORCE_HS\n");
  310. musb->test_mode_nr =
  311. MUSB_TEST_FORCE_HS;
  312. break;
  313. case 0xc1:
  314. /* TEST_FORCE_FS */
  315. pr_debug("TEST_FORCE_FS\n");
  316. musb->test_mode_nr =
  317. MUSB_TEST_FORCE_FS;
  318. break;
  319. case 0xc2:
  320. /* TEST_FIFO_ACCESS */
  321. pr_debug("TEST_FIFO_ACCESS\n");
  322. musb->test_mode_nr =
  323. MUSB_TEST_FIFO_ACCESS;
  324. break;
  325. case 0xc3:
  326. /* TEST_FORCE_HOST */
  327. pr_debug("TEST_FORCE_HOST\n");
  328. musb->test_mode_nr =
  329. MUSB_TEST_FORCE_HOST;
  330. break;
  331. default:
  332. goto stall;
  333. }
  334. /* enter test mode after irq */
  335. if (handled > 0)
  336. musb->test_mode = true;
  337. break;
  338. case USB_DEVICE_B_HNP_ENABLE:
  339. if (!musb->g.is_otg)
  340. goto stall;
  341. musb->g.b_hnp_enable = 1;
  342. musb_try_b_hnp_enable(musb);
  343. break;
  344. case USB_DEVICE_A_HNP_SUPPORT:
  345. if (!musb->g.is_otg)
  346. goto stall;
  347. musb->g.a_hnp_support = 1;
  348. break;
  349. case USB_DEVICE_A_ALT_HNP_SUPPORT:
  350. if (!musb->g.is_otg)
  351. goto stall;
  352. musb->g.a_alt_hnp_support = 1;
  353. break;
  354. case USB_DEVICE_DEBUG_MODE:
  355. handled = 0;
  356. break;
  357. stall:
  358. default:
  359. handled = -EINVAL;
  360. break;
  361. }
  362. break;
  363. case USB_RECIP_INTERFACE:
  364. break;
  365. case USB_RECIP_ENDPOINT:{
  366. const u8 epnum =
  367. ctrlrequest->wIndex & 0x0f;
  368. struct musb_ep *musb_ep;
  369. struct musb_hw_ep *ep;
  370. void __iomem *regs;
  371. int is_in;
  372. u16 csr;
  373. if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
  374. ctrlrequest->wValue != USB_ENDPOINT_HALT)
  375. break;
  376. ep = musb->endpoints + epnum;
  377. regs = ep->regs;
  378. is_in = ctrlrequest->wIndex & USB_DIR_IN;
  379. if (is_in)
  380. musb_ep = &ep->ep_in;
  381. else
  382. musb_ep = &ep->ep_out;
  383. if (!musb_ep->desc)
  384. break;
  385. musb_ep_select(mbase, epnum);
  386. if (is_in) {
  387. csr = musb_readw(regs, MUSB_TXCSR);
  388. if (csr & MUSB_TXCSR_FIFONOTEMPTY)
  389. csr |= MUSB_TXCSR_FLUSHFIFO;
  390. csr |= MUSB_TXCSR_P_SENDSTALL
  391. | MUSB_TXCSR_CLRDATATOG
  392. | MUSB_TXCSR_P_WZC_BITS;
  393. musb_writew(regs, MUSB_TXCSR, csr);
  394. } else {
  395. csr = musb_readw(regs, MUSB_RXCSR);
  396. csr |= MUSB_RXCSR_P_SENDSTALL
  397. | MUSB_RXCSR_FLUSHFIFO
  398. | MUSB_RXCSR_CLRDATATOG
  399. | MUSB_RXCSR_P_WZC_BITS;
  400. musb_writew(regs, MUSB_RXCSR, csr);
  401. }
  402. /* select ep0 again */
  403. musb_ep_select(mbase, 0);
  404. handled = 1;
  405. } break;
  406. default:
  407. /* class, vendor, etc ... delegate */
  408. handled = 0;
  409. break;
  410. }
  411. break;
  412. default:
  413. /* delegate SET_CONFIGURATION, etc */
  414. handled = 0;
  415. }
  416. } else
  417. handled = 0;
  418. return handled;
  419. }
  420. /* we have an ep0out data packet
  421. * Context: caller holds controller lock
  422. */
  423. static void ep0_rxstate(struct musb *musb)
  424. {
  425. void __iomem *regs = musb->control_ep->regs;
  426. struct musb_request *request;
  427. struct usb_request *req;
  428. u16 count, csr;
  429. request = next_ep0_request(musb);
  430. req = &request->request;
  431. /* read packet and ack; or stall because of gadget driver bug:
  432. * should have provided the rx buffer before setup() returned.
  433. */
  434. if (req) {
  435. void *buf = req->buf + req->actual;
  436. unsigned len = req->length - req->actual;
  437. /* read the buffer */
  438. count = musb_readb(regs, MUSB_COUNT0);
  439. if (count > len) {
  440. req->status = -EOVERFLOW;
  441. count = len;
  442. }
  443. musb_read_fifo(&musb->endpoints[0], count, buf);
  444. req->actual += count;
  445. csr = MUSB_CSR0_P_SVDRXPKTRDY;
  446. if (count < 64 || req->actual == req->length) {
  447. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  448. csr |= MUSB_CSR0_P_DATAEND;
  449. } else
  450. req = NULL;
  451. } else
  452. csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
  453. /* Completion handler may choose to stall, e.g. because the
  454. * message just received holds invalid data.
  455. */
  456. if (req) {
  457. musb->ackpend = csr;
  458. musb_g_ep0_giveback(musb, req);
  459. if (!musb->ackpend)
  460. return;
  461. musb->ackpend = 0;
  462. }
  463. musb_ep_select(musb->mregs, 0);
  464. musb_writew(regs, MUSB_CSR0, csr);
  465. }
  466. /*
  467. * transmitting to the host (IN), this code might be called from IRQ
  468. * and from kernel thread.
  469. *
  470. * Context: caller holds controller lock
  471. */
  472. static void ep0_txstate(struct musb *musb)
  473. {
  474. void __iomem *regs = musb->control_ep->regs;
  475. struct musb_request *req = next_ep0_request(musb);
  476. struct usb_request *request;
  477. u16 csr = MUSB_CSR0_TXPKTRDY;
  478. u8 *fifo_src;
  479. u8 fifo_count;
  480. if (!req) {
  481. /* WARN_ON(1); */
  482. dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
  483. return;
  484. }
  485. request = &req->request;
  486. /* load the data */
  487. fifo_src = (u8 *) request->buf + request->actual;
  488. fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
  489. request->length - request->actual);
  490. musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
  491. request->actual += fifo_count;
  492. /* update the flags */
  493. if (fifo_count < MUSB_MAX_END0_PACKET
  494. || (request->actual == request->length
  495. && !request->zero)) {
  496. musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
  497. csr |= MUSB_CSR0_P_DATAEND;
  498. } else
  499. request = NULL;
  500. /* send it out, triggering a "txpktrdy cleared" irq */
  501. musb_ep_select(musb->mregs, 0);
  502. musb_writew(regs, MUSB_CSR0, csr);
  503. /* report completions as soon as the fifo's loaded; there's no
  504. * win in waiting till this last packet gets acked. (other than
  505. * very precise fault reporting, needed by USB TMC; possible with
  506. * this hardware, but not usable from portable gadget drivers.)
  507. */
  508. if (request) {
  509. musb->ackpend = csr;
  510. musb_g_ep0_giveback(musb, request);
  511. if (!musb->ackpend)
  512. return;
  513. musb->ackpend = 0;
  514. }
  515. }
  516. /*
  517. * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
  518. * Fields are left in USB byte-order.
  519. *
  520. * Context: caller holds controller lock.
  521. */
  522. static void
  523. musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
  524. {
  525. struct musb_request *r;
  526. void __iomem *regs = musb->control_ep->regs;
  527. musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
  528. /* NOTE: earlier 2.6 versions changed setup packets to host
  529. * order, but now USB packets always stay in USB byte order.
  530. */
  531. dev_dbg(musb->controller, "SETUP req%02x.%02x v%04x i%04x l%d\n",
  532. req->bRequestType,
  533. req->bRequest,
  534. le16_to_cpu(req->wValue),
  535. le16_to_cpu(req->wIndex),
  536. le16_to_cpu(req->wLength));
  537. /* clean up any leftover transfers */
  538. r = next_ep0_request(musb);
  539. if (r)
  540. musb_g_ep0_giveback(musb, &r->request);
  541. /* For zero-data requests we want to delay the STATUS stage to
  542. * avoid SETUPEND errors. If we read data (OUT), delay accepting
  543. * packets until there's a buffer to store them in.
  544. *
  545. * If we write data, the controller acts happier if we enable
  546. * the TX FIFO right away, and give the controller a moment
  547. * to switch modes...
  548. */
  549. musb->set_address = false;
  550. musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
  551. if (req->wLength == 0) {
  552. if (req->bRequestType & USB_DIR_IN)
  553. musb->ackpend |= MUSB_CSR0_TXPKTRDY;
  554. musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
  555. } else if (req->bRequestType & USB_DIR_IN) {
  556. musb->ep0_state = MUSB_EP0_STAGE_TX;
  557. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
  558. while ((musb_readw(regs, MUSB_CSR0)
  559. & MUSB_CSR0_RXPKTRDY) != 0)
  560. cpu_relax();
  561. musb->ackpend = 0;
  562. } else
  563. musb->ep0_state = MUSB_EP0_STAGE_RX;
  564. }
  565. static int
  566. forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
  567. __releases(musb->lock)
  568. __acquires(musb->lock)
  569. {
  570. int retval;
  571. if (!musb->gadget_driver)
  572. return -EOPNOTSUPP;
  573. spin_unlock(&musb->lock);
  574. retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
  575. spin_lock(&musb->lock);
  576. return retval;
  577. }
  578. /*
  579. * Handle peripheral ep0 interrupt
  580. *
  581. * Context: irq handler; we won't re-enter the driver that way.
  582. */
  583. irqreturn_t musb_g_ep0_irq(struct musb *musb)
  584. {
  585. u16 csr;
  586. u16 len;
  587. void __iomem *mbase = musb->mregs;
  588. void __iomem *regs = musb->endpoints[0].regs;
  589. irqreturn_t retval = IRQ_NONE;
  590. musb_ep_select(mbase, 0); /* select ep0 */
  591. csr = musb_readw(regs, MUSB_CSR0);
  592. len = musb_readb(regs, MUSB_COUNT0);
  593. dev_dbg(musb->controller, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
  594. csr, len,
  595. musb_readb(mbase, MUSB_FADDR),
  596. decode_ep0stage(musb->ep0_state));
  597. if (csr & MUSB_CSR0_P_DATAEND) {
  598. /*
  599. * If DATAEND is set we should not call the callback,
  600. * hence the status stage is not complete.
  601. */
  602. return IRQ_HANDLED;
  603. }
  604. /* I sent a stall.. need to acknowledge it now.. */
  605. if (csr & MUSB_CSR0_P_SENTSTALL) {
  606. musb_writew(regs, MUSB_CSR0,
  607. csr & ~MUSB_CSR0_P_SENTSTALL);
  608. retval = IRQ_HANDLED;
  609. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  610. csr = musb_readw(regs, MUSB_CSR0);
  611. }
  612. /* request ended "early" */
  613. if (csr & MUSB_CSR0_P_SETUPEND) {
  614. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
  615. retval = IRQ_HANDLED;
  616. /* Transition into the early status phase */
  617. switch (musb->ep0_state) {
  618. case MUSB_EP0_STAGE_TX:
  619. musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
  620. break;
  621. case MUSB_EP0_STAGE_RX:
  622. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  623. break;
  624. default:
  625. ERR("SetupEnd came in a wrong ep0stage %s\n",
  626. decode_ep0stage(musb->ep0_state));
  627. }
  628. csr = musb_readw(regs, MUSB_CSR0);
  629. /* NOTE: request may need completion */
  630. }
  631. /* docs from Mentor only describe tx, rx, and idle/setup states.
  632. * we need to handle nuances around status stages, and also the
  633. * case where status and setup stages come back-to-back ...
  634. */
  635. switch (musb->ep0_state) {
  636. case MUSB_EP0_STAGE_TX:
  637. /* irq on clearing txpktrdy */
  638. if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
  639. ep0_txstate(musb);
  640. retval = IRQ_HANDLED;
  641. }
  642. break;
  643. case MUSB_EP0_STAGE_RX:
  644. /* irq on set rxpktrdy */
  645. if (csr & MUSB_CSR0_RXPKTRDY) {
  646. ep0_rxstate(musb);
  647. retval = IRQ_HANDLED;
  648. }
  649. break;
  650. case MUSB_EP0_STAGE_STATUSIN:
  651. /* end of sequence #2 (OUT/RX state) or #3 (no data) */
  652. /* update address (if needed) only @ the end of the
  653. * status phase per usb spec, which also guarantees
  654. * we get 10 msec to receive this irq... until this
  655. * is done we won't see the next packet.
  656. */
  657. if (musb->set_address) {
  658. musb->set_address = false;
  659. musb_writeb(mbase, MUSB_FADDR, musb->address);
  660. }
  661. /* enter test mode if needed (exit by reset) */
  662. else if (musb->test_mode) {
  663. dev_dbg(musb->controller, "entering TESTMODE\n");
  664. if (MUSB_TEST_PACKET == musb->test_mode_nr)
  665. musb_load_testpacket(musb);
  666. musb_writeb(mbase, MUSB_TESTMODE,
  667. musb->test_mode_nr);
  668. }
  669. /* FALLTHROUGH */
  670. case MUSB_EP0_STAGE_STATUSOUT:
  671. /* end of sequence #1: write to host (TX state) */
  672. {
  673. struct musb_request *req;
  674. req = next_ep0_request(musb);
  675. if (req)
  676. musb_g_ep0_giveback(musb, &req->request);
  677. }
  678. /*
  679. * In case when several interrupts can get coalesced,
  680. * check to see if we've already received a SETUP packet...
  681. */
  682. if (csr & MUSB_CSR0_RXPKTRDY)
  683. goto setup;
  684. retval = IRQ_HANDLED;
  685. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  686. break;
  687. case MUSB_EP0_STAGE_IDLE:
  688. /*
  689. * This state is typically (but not always) indiscernible
  690. * from the status states since the corresponding interrupts
  691. * tend to happen within too little period of time (with only
  692. * a zero-length packet in between) and so get coalesced...
  693. */
  694. retval = IRQ_HANDLED;
  695. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  696. /* FALLTHROUGH */
  697. case MUSB_EP0_STAGE_SETUP:
  698. setup:
  699. if (csr & MUSB_CSR0_RXPKTRDY) {
  700. struct usb_ctrlrequest setup;
  701. int handled = 0;
  702. if (len != 8) {
  703. ERR("SETUP packet len %d != 8 ?\n", len);
  704. break;
  705. }
  706. musb_read_setup(musb, &setup);
  707. retval = IRQ_HANDLED;
  708. /* sometimes the RESET won't be reported */
  709. if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
  710. u8 power;
  711. printk(KERN_NOTICE "%s: peripheral reset "
  712. "irq lost!\n",
  713. musb_driver_name);
  714. power = musb_readb(mbase, MUSB_POWER);
  715. musb->g.speed = (power & MUSB_POWER_HSMODE)
  716. ? USB_SPEED_HIGH : USB_SPEED_FULL;
  717. }
  718. switch (musb->ep0_state) {
  719. /* sequence #3 (no data stage), includes requests
  720. * we can't forward (notably SET_ADDRESS and the
  721. * device/endpoint feature set/clear operations)
  722. * plus SET_CONFIGURATION and others we must
  723. */
  724. case MUSB_EP0_STAGE_ACKWAIT:
  725. handled = service_zero_data_request(
  726. musb, &setup);
  727. /*
  728. * We're expecting no data in any case, so
  729. * always set the DATAEND bit -- doing this
  730. * here helps avoid SetupEnd interrupt coming
  731. * in the idle stage when we're stalling...
  732. */
  733. musb->ackpend |= MUSB_CSR0_P_DATAEND;
  734. /* status stage might be immediate */
  735. if (handled > 0)
  736. musb->ep0_state =
  737. MUSB_EP0_STAGE_STATUSIN;
  738. break;
  739. /* sequence #1 (IN to host), includes GET_STATUS
  740. * requests that we can't forward, GET_DESCRIPTOR
  741. * and others that we must
  742. */
  743. case MUSB_EP0_STAGE_TX:
  744. handled = service_in_request(musb, &setup);
  745. if (handled > 0) {
  746. musb->ackpend = MUSB_CSR0_TXPKTRDY
  747. | MUSB_CSR0_P_DATAEND;
  748. musb->ep0_state =
  749. MUSB_EP0_STAGE_STATUSOUT;
  750. }
  751. break;
  752. /* sequence #2 (OUT from host), always forward */
  753. default: /* MUSB_EP0_STAGE_RX */
  754. break;
  755. }
  756. dev_dbg(musb->controller, "handled %d, csr %04x, ep0stage %s\n",
  757. handled, csr,
  758. decode_ep0stage(musb->ep0_state));
  759. /* unless we need to delegate this to the gadget
  760. * driver, we know how to wrap this up: csr0 has
  761. * not yet been written.
  762. */
  763. if (handled < 0)
  764. goto stall;
  765. else if (handled > 0)
  766. goto finish;
  767. handled = forward_to_driver(musb, &setup);
  768. if (handled < 0) {
  769. musb_ep_select(mbase, 0);
  770. stall:
  771. dev_dbg(musb->controller, "stall (%d)\n", handled);
  772. musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
  773. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  774. finish:
  775. musb_writew(regs, MUSB_CSR0,
  776. musb->ackpend);
  777. musb->ackpend = 0;
  778. }
  779. }
  780. break;
  781. case MUSB_EP0_STAGE_ACKWAIT:
  782. /* This should not happen. But happens with tusb6010 with
  783. * g_file_storage and high speed. Do nothing.
  784. */
  785. retval = IRQ_HANDLED;
  786. break;
  787. default:
  788. /* "can't happen" */
  789. assert_noisy(false);
  790. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
  791. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  792. break;
  793. }
  794. return retval;
  795. }
  796. static int
  797. musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
  798. {
  799. /* always enabled */
  800. return -EINVAL;
  801. }
  802. static int musb_g_ep0_disable(struct usb_ep *e)
  803. {
  804. /* always enabled */
  805. return -EINVAL;
  806. }
  807. static int
  808. musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
  809. {
  810. struct musb_ep *ep;
  811. struct musb_request *req;
  812. struct musb *musb;
  813. int status;
  814. unsigned long lockflags;
  815. void __iomem *regs;
  816. if (!e || !r)
  817. return -EINVAL;
  818. ep = to_musb_ep(e);
  819. musb = ep->musb;
  820. regs = musb->control_ep->regs;
  821. req = to_musb_request(r);
  822. req->musb = musb;
  823. req->request.actual = 0;
  824. req->request.status = -EINPROGRESS;
  825. req->tx = ep->is_in;
  826. spin_lock_irqsave(&musb->lock, lockflags);
  827. if (!list_empty(&ep->req_list)) {
  828. status = -EBUSY;
  829. goto cleanup;
  830. }
  831. switch (musb->ep0_state) {
  832. case MUSB_EP0_STAGE_RX: /* control-OUT data */
  833. case MUSB_EP0_STAGE_TX: /* control-IN data */
  834. case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
  835. status = 0;
  836. break;
  837. default:
  838. dev_dbg(musb->controller, "ep0 request queued in state %d\n",
  839. musb->ep0_state);
  840. status = -EINVAL;
  841. goto cleanup;
  842. }
  843. /* add request to the list */
  844. list_add_tail(&req->list, &ep->req_list);
  845. dev_dbg(musb->controller, "queue to %s (%s), length=%d\n",
  846. ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
  847. req->request.length);
  848. musb_ep_select(musb->mregs, 0);
  849. /* sequence #1, IN ... start writing the data */
  850. if (musb->ep0_state == MUSB_EP0_STAGE_TX)
  851. ep0_txstate(musb);
  852. /* sequence #3, no-data ... issue IN status */
  853. else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
  854. if (req->request.length)
  855. status = -EINVAL;
  856. else {
  857. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  858. musb_writew(regs, MUSB_CSR0,
  859. musb->ackpend | MUSB_CSR0_P_DATAEND);
  860. musb->ackpend = 0;
  861. musb_g_ep0_giveback(ep->musb, r);
  862. }
  863. /* else for sequence #2 (OUT), caller provides a buffer
  864. * before the next packet arrives. deferred responses
  865. * (after SETUP is acked) are racey.
  866. */
  867. } else if (musb->ackpend) {
  868. musb_writew(regs, MUSB_CSR0, musb->ackpend);
  869. musb->ackpend = 0;
  870. }
  871. cleanup:
  872. spin_unlock_irqrestore(&musb->lock, lockflags);
  873. return status;
  874. }
  875. static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
  876. {
  877. /* we just won't support this */
  878. return -EINVAL;
  879. }
  880. static int musb_g_ep0_halt(struct usb_ep *e, int value)
  881. {
  882. struct musb_ep *ep;
  883. struct musb *musb;
  884. void __iomem *base, *regs;
  885. unsigned long flags;
  886. int status;
  887. u16 csr;
  888. if (!e || !value)
  889. return -EINVAL;
  890. ep = to_musb_ep(e);
  891. musb = ep->musb;
  892. base = musb->mregs;
  893. regs = musb->control_ep->regs;
  894. status = 0;
  895. spin_lock_irqsave(&musb->lock, flags);
  896. if (!list_empty(&ep->req_list)) {
  897. status = -EBUSY;
  898. goto cleanup;
  899. }
  900. musb_ep_select(base, 0);
  901. csr = musb->ackpend;
  902. switch (musb->ep0_state) {
  903. /* Stalls are usually issued after parsing SETUP packet, either
  904. * directly in irq context from setup() or else later.
  905. */
  906. case MUSB_EP0_STAGE_TX: /* control-IN data */
  907. case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
  908. case MUSB_EP0_STAGE_RX: /* control-OUT data */
  909. csr = musb_readw(regs, MUSB_CSR0);
  910. /* FALLTHROUGH */
  911. /* It's also OK to issue stalls during callbacks when a non-empty
  912. * DATA stage buffer has been read (or even written).
  913. */
  914. case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
  915. case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
  916. csr |= MUSB_CSR0_P_SENDSTALL;
  917. musb_writew(regs, MUSB_CSR0, csr);
  918. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  919. musb->ackpend = 0;
  920. break;
  921. default:
  922. dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);
  923. status = -EINVAL;
  924. }
  925. cleanup:
  926. spin_unlock_irqrestore(&musb->lock, flags);
  927. return status;
  928. }
  929. const struct usb_ep_ops musb_g_ep0_ops = {
  930. .enable = musb_g_ep0_enable,
  931. .disable = musb_g_ep0_disable,
  932. .alloc_request = musb_alloc_request,
  933. .free_request = musb_free_request,
  934. .queue = musb_g_ep0_queue,
  935. .dequeue = musb_g_ep0_dequeue,
  936. .set_halt = musb_g_ep0_halt,
  937. };