musb_gadget.c 59 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MUSB OTG driver peripheral support
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
  9. */
  10. #ifndef __UBOOT__
  11. #include <log.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/devres.h>
  14. #include <linux/kernel.h>
  15. #include <linux/list.h>
  16. #include <linux/timer.h>
  17. #include <linux/module.h>
  18. #include <linux/smp.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/delay.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/slab.h>
  23. #else
  24. #include <common.h>
  25. #include <dm.h>
  26. #include <dm/device_compat.h>
  27. #include <linux/bug.h>
  28. #include <linux/usb/ch9.h>
  29. #include "linux-compat.h"
  30. #endif
  31. #include "musb_core.h"
  32. /* MUSB PERIPHERAL status 3-mar-2006:
  33. *
  34. * - EP0 seems solid. It passes both USBCV and usbtest control cases.
  35. * Minor glitches:
  36. *
  37. * + remote wakeup to Linux hosts work, but saw USBCV failures;
  38. * in one test run (operator error?)
  39. * + endpoint halt tests -- in both usbtest and usbcv -- seem
  40. * to break when dma is enabled ... is something wrongly
  41. * clearing SENDSTALL?
  42. *
  43. * - Mass storage behaved ok when last tested. Network traffic patterns
  44. * (with lots of short transfers etc) need retesting; they turn up the
  45. * worst cases of the DMA, since short packets are typical but are not
  46. * required.
  47. *
  48. * - TX/IN
  49. * + both pio and dma behave in with network and g_zero tests
  50. * + no cppi throughput issues other than no-hw-queueing
  51. * + failed with FLAT_REG (DaVinci)
  52. * + seems to behave with double buffering, PIO -and- CPPI
  53. * + with gadgetfs + AIO, requests got lost?
  54. *
  55. * - RX/OUT
  56. * + both pio and dma behave in with network and g_zero tests
  57. * + dma is slow in typical case (short_not_ok is clear)
  58. * + double buffering ok with PIO
  59. * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
  60. * + request lossage observed with gadgetfs
  61. *
  62. * - ISO not tested ... might work, but only weakly isochronous
  63. *
  64. * - Gadget driver disabling of softconnect during bind() is ignored; so
  65. * drivers can't hold off host requests until userspace is ready.
  66. * (Workaround: they can turn it off later.)
  67. *
  68. * - PORTABILITY (assumes PIO works):
  69. * + DaVinci, basically works with cppi dma
  70. * + OMAP 2430, ditto with mentor dma
  71. * + TUSB 6010, platform-specific dma in the works
  72. */
  73. /* ----------------------------------------------------------------------- */
  74. #define is_buffer_mapped(req) (is_dma_capable() && \
  75. (req->map_state != UN_MAPPED))
  76. #ifndef CONFIG_USB_MUSB_PIO_ONLY
  77. /* Maps the buffer to dma */
  78. static inline void map_dma_buffer(struct musb_request *request,
  79. struct musb *musb, struct musb_ep *musb_ep)
  80. {
  81. int compatible = true;
  82. struct dma_controller *dma = musb->dma_controller;
  83. request->map_state = UN_MAPPED;
  84. if (!is_dma_capable() || !musb_ep->dma)
  85. return;
  86. /* Check if DMA engine can handle this request.
  87. * DMA code must reject the USB request explicitly.
  88. * Default behaviour is to map the request.
  89. */
  90. if (dma->is_compatible)
  91. compatible = dma->is_compatible(musb_ep->dma,
  92. musb_ep->packet_sz, request->request.buf,
  93. request->request.length);
  94. if (!compatible)
  95. return;
  96. if (request->request.dma == DMA_ADDR_INVALID) {
  97. request->request.dma = dma_map_single(
  98. musb->controller,
  99. request->request.buf,
  100. request->request.length,
  101. request->tx
  102. ? DMA_TO_DEVICE
  103. : DMA_FROM_DEVICE);
  104. request->map_state = MUSB_MAPPED;
  105. } else {
  106. dma_sync_single_for_device(musb->controller,
  107. request->request.dma,
  108. request->request.length,
  109. request->tx
  110. ? DMA_TO_DEVICE
  111. : DMA_FROM_DEVICE);
  112. request->map_state = PRE_MAPPED;
  113. }
  114. }
  115. /* Unmap the buffer from dma and maps it back to cpu */
  116. static inline void unmap_dma_buffer(struct musb_request *request,
  117. struct musb *musb)
  118. {
  119. if (!is_buffer_mapped(request))
  120. return;
  121. if (request->request.dma == DMA_ADDR_INVALID) {
  122. dev_vdbg(musb->controller,
  123. "not unmapping a never mapped buffer\n");
  124. return;
  125. }
  126. if (request->map_state == MUSB_MAPPED) {
  127. dma_unmap_single(musb->controller,
  128. request->request.dma,
  129. request->request.length,
  130. request->tx
  131. ? DMA_TO_DEVICE
  132. : DMA_FROM_DEVICE);
  133. request->request.dma = DMA_ADDR_INVALID;
  134. } else { /* PRE_MAPPED */
  135. dma_sync_single_for_cpu(musb->controller,
  136. request->request.dma,
  137. request->request.length,
  138. request->tx
  139. ? DMA_TO_DEVICE
  140. : DMA_FROM_DEVICE);
  141. }
  142. request->map_state = UN_MAPPED;
  143. }
  144. #else
  145. static inline void map_dma_buffer(struct musb_request *request,
  146. struct musb *musb, struct musb_ep *musb_ep)
  147. {
  148. }
  149. static inline void unmap_dma_buffer(struct musb_request *request,
  150. struct musb *musb)
  151. {
  152. }
  153. #endif
  154. /*
  155. * Immediately complete a request.
  156. *
  157. * @param request the request to complete
  158. * @param status the status to complete the request with
  159. * Context: controller locked, IRQs blocked.
  160. */
  161. void musb_g_giveback(
  162. struct musb_ep *ep,
  163. struct usb_request *request,
  164. int status)
  165. __releases(ep->musb->lock)
  166. __acquires(ep->musb->lock)
  167. {
  168. struct musb_request *req;
  169. struct musb *musb;
  170. int busy = ep->busy;
  171. req = to_musb_request(request);
  172. list_del(&req->list);
  173. if (req->request.status == -EINPROGRESS)
  174. req->request.status = status;
  175. musb = req->musb;
  176. ep->busy = 1;
  177. spin_unlock(&musb->lock);
  178. unmap_dma_buffer(req, musb);
  179. if (request->status == 0)
  180. dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
  181. ep->end_point.name, request,
  182. req->request.actual, req->request.length);
  183. else
  184. dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
  185. ep->end_point.name, request,
  186. req->request.actual, req->request.length,
  187. request->status);
  188. req->request.complete(&req->ep->end_point, &req->request);
  189. spin_lock(&musb->lock);
  190. ep->busy = busy;
  191. }
  192. /* ----------------------------------------------------------------------- */
  193. /*
  194. * Abort requests queued to an endpoint using the status. Synchronous.
  195. * caller locked controller and blocked irqs, and selected this ep.
  196. */
  197. static void nuke(struct musb_ep *ep, const int status)
  198. {
  199. struct musb *musb = ep->musb;
  200. struct musb_request *req = NULL;
  201. void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
  202. ep->busy = 1;
  203. if (is_dma_capable() && ep->dma) {
  204. struct dma_controller *c = ep->musb->dma_controller;
  205. int value;
  206. if (ep->is_in) {
  207. /*
  208. * The programming guide says that we must not clear
  209. * the DMAMODE bit before DMAENAB, so we only
  210. * clear it in the second write...
  211. */
  212. musb_writew(epio, MUSB_TXCSR,
  213. MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
  214. musb_writew(epio, MUSB_TXCSR,
  215. 0 | MUSB_TXCSR_FLUSHFIFO);
  216. } else {
  217. musb_writew(epio, MUSB_RXCSR,
  218. 0 | MUSB_RXCSR_FLUSHFIFO);
  219. musb_writew(epio, MUSB_RXCSR,
  220. 0 | MUSB_RXCSR_FLUSHFIFO);
  221. }
  222. value = c->channel_abort(ep->dma);
  223. dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
  224. ep->name, value);
  225. c->channel_release(ep->dma);
  226. ep->dma = NULL;
  227. }
  228. while (!list_empty(&ep->req_list)) {
  229. req = list_first_entry(&ep->req_list, struct musb_request, list);
  230. musb_g_giveback(ep, &req->request, status);
  231. }
  232. }
  233. /* ----------------------------------------------------------------------- */
  234. /* Data transfers - pure PIO, pure DMA, or mixed mode */
  235. /*
  236. * This assumes the separate CPPI engine is responding to DMA requests
  237. * from the usb core ... sequenced a bit differently from mentor dma.
  238. */
  239. static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
  240. {
  241. if (can_bulk_split(musb, ep->type))
  242. return ep->hw_ep->max_packet_sz_tx;
  243. else
  244. return ep->packet_sz;
  245. }
  246. #ifdef CONFIG_USB_INVENTRA_DMA
  247. /* Peripheral tx (IN) using Mentor DMA works as follows:
  248. Only mode 0 is used for transfers <= wPktSize,
  249. mode 1 is used for larger transfers,
  250. One of the following happens:
  251. - Host sends IN token which causes an endpoint interrupt
  252. -> TxAvail
  253. -> if DMA is currently busy, exit.
  254. -> if queue is non-empty, txstate().
  255. - Request is queued by the gadget driver.
  256. -> if queue was previously empty, txstate()
  257. txstate()
  258. -> start
  259. /\ -> setup DMA
  260. | (data is transferred to the FIFO, then sent out when
  261. | IN token(s) are recd from Host.
  262. | -> DMA interrupt on completion
  263. | calls TxAvail.
  264. | -> stop DMA, ~DMAENAB,
  265. | -> set TxPktRdy for last short pkt or zlp
  266. | -> Complete Request
  267. | -> Continue next request (call txstate)
  268. |___________________________________|
  269. * Non-Mentor DMA engines can of course work differently, such as by
  270. * upleveling from irq-per-packet to irq-per-buffer.
  271. */
  272. #endif
  273. /*
  274. * An endpoint is transmitting data. This can be called either from
  275. * the IRQ routine or from ep.queue() to kickstart a request on an
  276. * endpoint.
  277. *
  278. * Context: controller locked, IRQs blocked, endpoint selected
  279. */
  280. static void txstate(struct musb *musb, struct musb_request *req)
  281. {
  282. u8 epnum = req->epnum;
  283. struct musb_ep *musb_ep;
  284. void __iomem *epio = musb->endpoints[epnum].regs;
  285. struct usb_request *request;
  286. u16 fifo_count = 0, csr;
  287. int use_dma = 0;
  288. musb_ep = req->ep;
  289. /* Check if EP is disabled */
  290. if (!musb_ep->desc) {
  291. dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
  292. musb_ep->end_point.name);
  293. return;
  294. }
  295. /* we shouldn't get here while DMA is active ... but we do ... */
  296. if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
  297. dev_dbg(musb->controller, "dma pending...\n");
  298. return;
  299. }
  300. /* read TXCSR before */
  301. csr = musb_readw(epio, MUSB_TXCSR);
  302. request = &req->request;
  303. fifo_count = min(max_ep_writesize(musb, musb_ep),
  304. (int)(request->length - request->actual));
  305. if (csr & MUSB_TXCSR_TXPKTRDY) {
  306. dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
  307. musb_ep->end_point.name, csr);
  308. return;
  309. }
  310. if (csr & MUSB_TXCSR_P_SENDSTALL) {
  311. dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
  312. musb_ep->end_point.name, csr);
  313. return;
  314. }
  315. dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
  316. epnum, musb_ep->packet_sz, fifo_count,
  317. csr);
  318. #ifndef CONFIG_USB_MUSB_PIO_ONLY
  319. if (is_buffer_mapped(req)) {
  320. struct dma_controller *c = musb->dma_controller;
  321. size_t request_size;
  322. /* setup DMA, then program endpoint CSR */
  323. request_size = min_t(size_t, request->length - request->actual,
  324. musb_ep->dma->max_len);
  325. use_dma = (request->dma != DMA_ADDR_INVALID);
  326. /* MUSB_TXCSR_P_ISO is still set correctly */
  327. #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
  328. {
  329. if (request_size < musb_ep->packet_sz)
  330. musb_ep->dma->desired_mode = 0;
  331. else
  332. musb_ep->dma->desired_mode = 1;
  333. use_dma = use_dma && c->channel_program(
  334. musb_ep->dma, musb_ep->packet_sz,
  335. musb_ep->dma->desired_mode,
  336. request->dma + request->actual, request_size);
  337. if (use_dma) {
  338. if (musb_ep->dma->desired_mode == 0) {
  339. /*
  340. * We must not clear the DMAMODE bit
  341. * before the DMAENAB bit -- and the
  342. * latter doesn't always get cleared
  343. * before we get here...
  344. */
  345. csr &= ~(MUSB_TXCSR_AUTOSET
  346. | MUSB_TXCSR_DMAENAB);
  347. musb_writew(epio, MUSB_TXCSR, csr
  348. | MUSB_TXCSR_P_WZC_BITS);
  349. csr &= ~MUSB_TXCSR_DMAMODE;
  350. csr |= (MUSB_TXCSR_DMAENAB |
  351. MUSB_TXCSR_MODE);
  352. /* against programming guide */
  353. } else {
  354. csr |= (MUSB_TXCSR_DMAENAB
  355. | MUSB_TXCSR_DMAMODE
  356. | MUSB_TXCSR_MODE);
  357. if (!musb_ep->hb_mult)
  358. csr |= MUSB_TXCSR_AUTOSET;
  359. }
  360. csr &= ~MUSB_TXCSR_P_UNDERRUN;
  361. musb_writew(epio, MUSB_TXCSR, csr);
  362. }
  363. }
  364. #elif defined(CONFIG_USB_TI_CPPI_DMA)
  365. /* program endpoint CSR first, then setup DMA */
  366. csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
  367. csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
  368. MUSB_TXCSR_MODE;
  369. musb_writew(epio, MUSB_TXCSR,
  370. (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
  371. | csr);
  372. /* ensure writebuffer is empty */
  373. csr = musb_readw(epio, MUSB_TXCSR);
  374. /* NOTE host side sets DMAENAB later than this; both are
  375. * OK since the transfer dma glue (between CPPI and Mentor
  376. * fifos) just tells CPPI it could start. Data only moves
  377. * to the USB TX fifo when both fifos are ready.
  378. */
  379. /* "mode" is irrelevant here; handle terminating ZLPs like
  380. * PIO does, since the hardware RNDIS mode seems unreliable
  381. * except for the last-packet-is-already-short case.
  382. */
  383. use_dma = use_dma && c->channel_program(
  384. musb_ep->dma, musb_ep->packet_sz,
  385. 0,
  386. request->dma + request->actual,
  387. request_size);
  388. if (!use_dma) {
  389. c->channel_release(musb_ep->dma);
  390. musb_ep->dma = NULL;
  391. csr &= ~MUSB_TXCSR_DMAENAB;
  392. musb_writew(epio, MUSB_TXCSR, csr);
  393. /* invariant: prequest->buf is non-null */
  394. }
  395. #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
  396. use_dma = use_dma && c->channel_program(
  397. musb_ep->dma, musb_ep->packet_sz,
  398. request->zero,
  399. request->dma + request->actual,
  400. request_size);
  401. #endif
  402. }
  403. #endif
  404. if (!use_dma) {
  405. /*
  406. * Unmap the dma buffer back to cpu if dma channel
  407. * programming fails
  408. */
  409. unmap_dma_buffer(req, musb);
  410. musb_write_fifo(musb_ep->hw_ep, fifo_count,
  411. (u8 *) (request->buf + request->actual));
  412. request->actual += fifo_count;
  413. csr |= MUSB_TXCSR_TXPKTRDY;
  414. csr &= ~MUSB_TXCSR_P_UNDERRUN;
  415. musb_writew(epio, MUSB_TXCSR, csr);
  416. }
  417. /* host may already have the data when this message shows... */
  418. dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
  419. musb_ep->end_point.name, use_dma ? "dma" : "pio",
  420. request->actual, request->length,
  421. musb_readw(epio, MUSB_TXCSR),
  422. fifo_count,
  423. musb_readw(epio, MUSB_TXMAXP));
  424. }
  425. /*
  426. * FIFO state update (e.g. data ready).
  427. * Called from IRQ, with controller locked.
  428. */
  429. void musb_g_tx(struct musb *musb, u8 epnum)
  430. {
  431. u16 csr;
  432. struct musb_request *req;
  433. struct usb_request *request;
  434. u8 __iomem *mbase = musb->mregs;
  435. struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
  436. void __iomem *epio = musb->endpoints[epnum].regs;
  437. struct dma_channel *dma;
  438. musb_ep_select(mbase, epnum);
  439. req = next_request(musb_ep);
  440. request = &req->request;
  441. csr = musb_readw(epio, MUSB_TXCSR);
  442. dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
  443. dma = is_dma_capable() ? musb_ep->dma : NULL;
  444. /*
  445. * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
  446. * probably rates reporting as a host error.
  447. */
  448. if (csr & MUSB_TXCSR_P_SENTSTALL) {
  449. csr |= MUSB_TXCSR_P_WZC_BITS;
  450. csr &= ~MUSB_TXCSR_P_SENTSTALL;
  451. musb_writew(epio, MUSB_TXCSR, csr);
  452. return;
  453. }
  454. if (csr & MUSB_TXCSR_P_UNDERRUN) {
  455. /* We NAKed, no big deal... little reason to care. */
  456. csr |= MUSB_TXCSR_P_WZC_BITS;
  457. csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
  458. musb_writew(epio, MUSB_TXCSR, csr);
  459. dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
  460. epnum, request);
  461. }
  462. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  463. /*
  464. * SHOULD NOT HAPPEN... has with CPPI though, after
  465. * changing SENDSTALL (and other cases); harmless?
  466. */
  467. dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
  468. return;
  469. }
  470. if (request) {
  471. u8 is_dma = 0;
  472. if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
  473. is_dma = 1;
  474. csr |= MUSB_TXCSR_P_WZC_BITS;
  475. csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
  476. MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
  477. musb_writew(epio, MUSB_TXCSR, csr);
  478. /* Ensure writebuffer is empty. */
  479. csr = musb_readw(epio, MUSB_TXCSR);
  480. request->actual += musb_ep->dma->actual_len;
  481. dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
  482. epnum, csr, musb_ep->dma->actual_len, request);
  483. }
  484. /*
  485. * First, maybe a terminating short packet. Some DMA
  486. * engines might handle this by themselves.
  487. */
  488. if ((request->zero && request->length
  489. && (request->length % musb_ep->packet_sz == 0)
  490. && (request->actual == request->length))
  491. #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
  492. || (is_dma && (!dma->desired_mode ||
  493. (request->actual &
  494. (musb_ep->packet_sz - 1))))
  495. #endif
  496. ) {
  497. /*
  498. * On DMA completion, FIFO may not be
  499. * available yet...
  500. */
  501. if (csr & MUSB_TXCSR_TXPKTRDY)
  502. return;
  503. dev_dbg(musb->controller, "sending zero pkt\n");
  504. musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
  505. | MUSB_TXCSR_TXPKTRDY);
  506. request->zero = 0;
  507. }
  508. if (request->actual == request->length) {
  509. musb_g_giveback(musb_ep, request, 0);
  510. /*
  511. * In the giveback function the MUSB lock is
  512. * released and acquired after sometime. During
  513. * this time period the INDEX register could get
  514. * changed by the gadget_queue function especially
  515. * on SMP systems. Reselect the INDEX to be sure
  516. * we are reading/modifying the right registers
  517. */
  518. musb_ep_select(mbase, epnum);
  519. req = musb_ep->desc ? next_request(musb_ep) : NULL;
  520. if (!req) {
  521. dev_dbg(musb->controller, "%s idle now\n",
  522. musb_ep->end_point.name);
  523. return;
  524. }
  525. }
  526. txstate(musb, req);
  527. }
  528. }
  529. /* ------------------------------------------------------------ */
  530. #ifdef CONFIG_USB_INVENTRA_DMA
  531. /* Peripheral rx (OUT) using Mentor DMA works as follows:
  532. - Only mode 0 is used.
  533. - Request is queued by the gadget class driver.
  534. -> if queue was previously empty, rxstate()
  535. - Host sends OUT token which causes an endpoint interrupt
  536. /\ -> RxReady
  537. | -> if request queued, call rxstate
  538. | /\ -> setup DMA
  539. | | -> DMA interrupt on completion
  540. | | -> RxReady
  541. | | -> stop DMA
  542. | | -> ack the read
  543. | | -> if data recd = max expected
  544. | | by the request, or host
  545. | | sent a short packet,
  546. | | complete the request,
  547. | | and start the next one.
  548. | |_____________________________________|
  549. | else just wait for the host
  550. | to send the next OUT token.
  551. |__________________________________________________|
  552. * Non-Mentor DMA engines can of course work differently.
  553. */
  554. #endif
  555. /*
  556. * Context: controller locked, IRQs blocked, endpoint selected
  557. */
  558. static void rxstate(struct musb *musb, struct musb_request *req)
  559. {
  560. const u8 epnum = req->epnum;
  561. struct usb_request *request = &req->request;
  562. struct musb_ep *musb_ep;
  563. void __iomem *epio = musb->endpoints[epnum].regs;
  564. unsigned fifo_count = 0;
  565. u16 len;
  566. u16 csr = musb_readw(epio, MUSB_RXCSR);
  567. struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
  568. u8 use_mode_1;
  569. if (hw_ep->is_shared_fifo)
  570. musb_ep = &hw_ep->ep_in;
  571. else
  572. musb_ep = &hw_ep->ep_out;
  573. len = musb_ep->packet_sz;
  574. /* Check if EP is disabled */
  575. if (!musb_ep->desc) {
  576. dev_dbg(musb->controller, "ep:%s disabled - ignore request\n",
  577. musb_ep->end_point.name);
  578. return;
  579. }
  580. /* We shouldn't get here while DMA is active, but we do... */
  581. if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
  582. dev_dbg(musb->controller, "DMA pending...\n");
  583. return;
  584. }
  585. if (csr & MUSB_RXCSR_P_SENDSTALL) {
  586. dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
  587. musb_ep->end_point.name, csr);
  588. return;
  589. }
  590. if (is_cppi_enabled() && is_buffer_mapped(req)) {
  591. struct dma_controller *c = musb->dma_controller;
  592. struct dma_channel *channel = musb_ep->dma;
  593. /* NOTE: CPPI won't actually stop advancing the DMA
  594. * queue after short packet transfers, so this is almost
  595. * always going to run as IRQ-per-packet DMA so that
  596. * faults will be handled correctly.
  597. */
  598. if (c->channel_program(channel,
  599. musb_ep->packet_sz,
  600. !request->short_not_ok,
  601. request->dma + request->actual,
  602. request->length - request->actual)) {
  603. /* make sure that if an rxpkt arrived after the irq,
  604. * the cppi engine will be ready to take it as soon
  605. * as DMA is enabled
  606. */
  607. csr &= ~(MUSB_RXCSR_AUTOCLEAR
  608. | MUSB_RXCSR_DMAMODE);
  609. csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
  610. musb_writew(epio, MUSB_RXCSR, csr);
  611. return;
  612. }
  613. }
  614. if (csr & MUSB_RXCSR_RXPKTRDY) {
  615. len = musb_readw(epio, MUSB_RXCOUNT);
  616. /*
  617. * Enable Mode 1 on RX transfers only when short_not_ok flag
  618. * is set. Currently short_not_ok flag is set only from
  619. * file_storage and f_mass_storage drivers
  620. */
  621. if (request->short_not_ok && len == musb_ep->packet_sz)
  622. use_mode_1 = 1;
  623. else
  624. use_mode_1 = 0;
  625. if (request->actual < request->length) {
  626. #ifdef CONFIG_USB_INVENTRA_DMA
  627. if (is_buffer_mapped(req)) {
  628. struct dma_controller *c;
  629. struct dma_channel *channel;
  630. int use_dma = 0;
  631. c = musb->dma_controller;
  632. channel = musb_ep->dma;
  633. /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
  634. * mode 0 only. So we do not get endpoint interrupts due to DMA
  635. * completion. We only get interrupts from DMA controller.
  636. *
  637. * We could operate in DMA mode 1 if we knew the size of the tranfer
  638. * in advance. For mass storage class, request->length = what the host
  639. * sends, so that'd work. But for pretty much everything else,
  640. * request->length is routinely more than what the host sends. For
  641. * most these gadgets, end of is signified either by a short packet,
  642. * or filling the last byte of the buffer. (Sending extra data in
  643. * that last pckate should trigger an overflow fault.) But in mode 1,
  644. * we don't get DMA completion interrupt for short packets.
  645. *
  646. * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
  647. * to get endpoint interrupt on every DMA req, but that didn't seem
  648. * to work reliably.
  649. *
  650. * REVISIT an updated g_file_storage can set req->short_not_ok, which
  651. * then becomes usable as a runtime "use mode 1" hint...
  652. */
  653. /* Experimental: Mode1 works with mass storage use cases */
  654. if (use_mode_1) {
  655. csr |= MUSB_RXCSR_AUTOCLEAR;
  656. musb_writew(epio, MUSB_RXCSR, csr);
  657. csr |= MUSB_RXCSR_DMAENAB;
  658. musb_writew(epio, MUSB_RXCSR, csr);
  659. /*
  660. * this special sequence (enabling and then
  661. * disabling MUSB_RXCSR_DMAMODE) is required
  662. * to get DMAReq to activate
  663. */
  664. musb_writew(epio, MUSB_RXCSR,
  665. csr | MUSB_RXCSR_DMAMODE);
  666. musb_writew(epio, MUSB_RXCSR, csr);
  667. } else {
  668. if (!musb_ep->hb_mult &&
  669. musb_ep->hw_ep->rx_double_buffered)
  670. csr |= MUSB_RXCSR_AUTOCLEAR;
  671. csr |= MUSB_RXCSR_DMAENAB;
  672. musb_writew(epio, MUSB_RXCSR, csr);
  673. }
  674. if (request->actual < request->length) {
  675. int transfer_size = 0;
  676. if (use_mode_1) {
  677. transfer_size = min(request->length - request->actual,
  678. channel->max_len);
  679. musb_ep->dma->desired_mode = 1;
  680. } else {
  681. transfer_size = min(request->length - request->actual,
  682. (unsigned)len);
  683. musb_ep->dma->desired_mode = 0;
  684. }
  685. use_dma = c->channel_program(
  686. channel,
  687. musb_ep->packet_sz,
  688. channel->desired_mode,
  689. request->dma
  690. + request->actual,
  691. transfer_size);
  692. }
  693. if (use_dma)
  694. return;
  695. }
  696. #elif defined(CONFIG_USB_UX500_DMA)
  697. if ((is_buffer_mapped(req)) &&
  698. (request->actual < request->length)) {
  699. struct dma_controller *c;
  700. struct dma_channel *channel;
  701. int transfer_size = 0;
  702. c = musb->dma_controller;
  703. channel = musb_ep->dma;
  704. /* In case first packet is short */
  705. if (len < musb_ep->packet_sz)
  706. transfer_size = len;
  707. else if (request->short_not_ok)
  708. transfer_size = min(request->length -
  709. request->actual,
  710. channel->max_len);
  711. else
  712. transfer_size = min(request->length -
  713. request->actual,
  714. (unsigned)len);
  715. csr &= ~MUSB_RXCSR_DMAMODE;
  716. csr |= (MUSB_RXCSR_DMAENAB |
  717. MUSB_RXCSR_AUTOCLEAR);
  718. musb_writew(epio, MUSB_RXCSR, csr);
  719. if (transfer_size <= musb_ep->packet_sz) {
  720. musb_ep->dma->desired_mode = 0;
  721. } else {
  722. musb_ep->dma->desired_mode = 1;
  723. /* Mode must be set after DMAENAB */
  724. csr |= MUSB_RXCSR_DMAMODE;
  725. musb_writew(epio, MUSB_RXCSR, csr);
  726. }
  727. if (c->channel_program(channel,
  728. musb_ep->packet_sz,
  729. channel->desired_mode,
  730. request->dma
  731. + request->actual,
  732. transfer_size))
  733. return;
  734. }
  735. #endif /* Mentor's DMA */
  736. fifo_count = request->length - request->actual;
  737. dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
  738. musb_ep->end_point.name,
  739. len, fifo_count,
  740. musb_ep->packet_sz);
  741. fifo_count = min_t(unsigned, len, fifo_count);
  742. #ifdef CONFIG_USB_TUSB_OMAP_DMA
  743. if (tusb_dma_omap() && is_buffer_mapped(req)) {
  744. struct dma_controller *c = musb->dma_controller;
  745. struct dma_channel *channel = musb_ep->dma;
  746. u32 dma_addr = request->dma + request->actual;
  747. int ret;
  748. ret = c->channel_program(channel,
  749. musb_ep->packet_sz,
  750. channel->desired_mode,
  751. dma_addr,
  752. fifo_count);
  753. if (ret)
  754. return;
  755. }
  756. #endif
  757. /*
  758. * Unmap the dma buffer back to cpu if dma channel
  759. * programming fails. This buffer is mapped if the
  760. * channel allocation is successful
  761. */
  762. if (is_buffer_mapped(req)) {
  763. unmap_dma_buffer(req, musb);
  764. /*
  765. * Clear DMAENAB and AUTOCLEAR for the
  766. * PIO mode transfer
  767. */
  768. csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
  769. musb_writew(epio, MUSB_RXCSR, csr);
  770. }
  771. musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
  772. (request->buf + request->actual));
  773. request->actual += fifo_count;
  774. /* REVISIT if we left anything in the fifo, flush
  775. * it and report -EOVERFLOW
  776. */
  777. /* ack the read! */
  778. csr |= MUSB_RXCSR_P_WZC_BITS;
  779. csr &= ~MUSB_RXCSR_RXPKTRDY;
  780. musb_writew(epio, MUSB_RXCSR, csr);
  781. }
  782. }
  783. /* reach the end or short packet detected */
  784. if (request->actual == request->length || len < musb_ep->packet_sz)
  785. musb_g_giveback(musb_ep, request, 0);
  786. }
  787. /*
  788. * Data ready for a request; called from IRQ
  789. */
  790. void musb_g_rx(struct musb *musb, u8 epnum)
  791. {
  792. u16 csr;
  793. struct musb_request *req;
  794. struct usb_request *request;
  795. void __iomem *mbase = musb->mregs;
  796. struct musb_ep *musb_ep;
  797. void __iomem *epio = musb->endpoints[epnum].regs;
  798. struct dma_channel *dma;
  799. struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
  800. if (hw_ep->is_shared_fifo)
  801. musb_ep = &hw_ep->ep_in;
  802. else
  803. musb_ep = &hw_ep->ep_out;
  804. musb_ep_select(mbase, epnum);
  805. req = next_request(musb_ep);
  806. if (!req)
  807. return;
  808. request = &req->request;
  809. csr = musb_readw(epio, MUSB_RXCSR);
  810. dma = is_dma_capable() ? musb_ep->dma : NULL;
  811. dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
  812. csr, dma ? " (dma)" : "", request);
  813. if (csr & MUSB_RXCSR_P_SENTSTALL) {
  814. csr |= MUSB_RXCSR_P_WZC_BITS;
  815. csr &= ~MUSB_RXCSR_P_SENTSTALL;
  816. musb_writew(epio, MUSB_RXCSR, csr);
  817. return;
  818. }
  819. if (csr & MUSB_RXCSR_P_OVERRUN) {
  820. /* csr |= MUSB_RXCSR_P_WZC_BITS; */
  821. csr &= ~MUSB_RXCSR_P_OVERRUN;
  822. musb_writew(epio, MUSB_RXCSR, csr);
  823. dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
  824. if (request->status == -EINPROGRESS)
  825. request->status = -EOVERFLOW;
  826. }
  827. if (csr & MUSB_RXCSR_INCOMPRX) {
  828. /* REVISIT not necessarily an error */
  829. dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
  830. }
  831. if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
  832. /* "should not happen"; likely RXPKTRDY pending for DMA */
  833. dev_dbg(musb->controller, "%s busy, csr %04x\n",
  834. musb_ep->end_point.name, csr);
  835. return;
  836. }
  837. if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
  838. csr &= ~(MUSB_RXCSR_AUTOCLEAR
  839. | MUSB_RXCSR_DMAENAB
  840. | MUSB_RXCSR_DMAMODE);
  841. musb_writew(epio, MUSB_RXCSR,
  842. MUSB_RXCSR_P_WZC_BITS | csr);
  843. request->actual += musb_ep->dma->actual_len;
  844. dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
  845. epnum, csr,
  846. musb_readw(epio, MUSB_RXCSR),
  847. musb_ep->dma->actual_len, request);
  848. #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
  849. defined(CONFIG_USB_UX500_DMA)
  850. /* Autoclear doesn't clear RxPktRdy for short packets */
  851. if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
  852. || (dma->actual_len
  853. & (musb_ep->packet_sz - 1))) {
  854. /* ack the read! */
  855. csr &= ~MUSB_RXCSR_RXPKTRDY;
  856. musb_writew(epio, MUSB_RXCSR, csr);
  857. }
  858. /* incomplete, and not short? wait for next IN packet */
  859. if ((request->actual < request->length)
  860. && (musb_ep->dma->actual_len
  861. == musb_ep->packet_sz)) {
  862. /* In double buffer case, continue to unload fifo if
  863. * there is Rx packet in FIFO.
  864. **/
  865. csr = musb_readw(epio, MUSB_RXCSR);
  866. if ((csr & MUSB_RXCSR_RXPKTRDY) &&
  867. hw_ep->rx_double_buffered)
  868. goto exit;
  869. return;
  870. }
  871. #endif
  872. musb_g_giveback(musb_ep, request, 0);
  873. /*
  874. * In the giveback function the MUSB lock is
  875. * released and acquired after sometime. During
  876. * this time period the INDEX register could get
  877. * changed by the gadget_queue function especially
  878. * on SMP systems. Reselect the INDEX to be sure
  879. * we are reading/modifying the right registers
  880. */
  881. musb_ep_select(mbase, epnum);
  882. req = next_request(musb_ep);
  883. if (!req)
  884. return;
  885. }
  886. #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
  887. defined(CONFIG_USB_UX500_DMA)
  888. exit:
  889. #endif
  890. /* Analyze request */
  891. rxstate(musb, req);
  892. }
  893. /* ------------------------------------------------------------ */
  894. static int musb_gadget_enable(struct usb_ep *ep,
  895. const struct usb_endpoint_descriptor *desc)
  896. {
  897. unsigned long flags;
  898. struct musb_ep *musb_ep;
  899. struct musb_hw_ep *hw_ep;
  900. void __iomem *regs;
  901. struct musb *musb;
  902. void __iomem *mbase;
  903. u8 epnum;
  904. u16 csr;
  905. unsigned tmp;
  906. int status = -EINVAL;
  907. if (!ep || !desc)
  908. return -EINVAL;
  909. musb_ep = to_musb_ep(ep);
  910. hw_ep = musb_ep->hw_ep;
  911. regs = hw_ep->regs;
  912. musb = musb_ep->musb;
  913. mbase = musb->mregs;
  914. epnum = musb_ep->current_epnum;
  915. spin_lock_irqsave(&musb->lock, flags);
  916. if (musb_ep->desc) {
  917. status = -EBUSY;
  918. goto fail;
  919. }
  920. musb_ep->type = usb_endpoint_type(desc);
  921. /* check direction and (later) maxpacket size against endpoint */
  922. if (usb_endpoint_num(desc) != epnum)
  923. goto fail;
  924. /* REVISIT this rules out high bandwidth periodic transfers */
  925. tmp = usb_endpoint_maxp(desc);
  926. if (tmp & ~0x07ff) {
  927. int ok;
  928. if (usb_endpoint_dir_in(desc))
  929. ok = musb->hb_iso_tx;
  930. else
  931. ok = musb->hb_iso_rx;
  932. if (!ok) {
  933. dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
  934. goto fail;
  935. }
  936. musb_ep->hb_mult = (tmp >> 11) & 3;
  937. } else {
  938. musb_ep->hb_mult = 0;
  939. }
  940. musb_ep->packet_sz = tmp & 0x7ff;
  941. tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
  942. /* enable the interrupts for the endpoint, set the endpoint
  943. * packet size (or fail), set the mode, clear the fifo
  944. */
  945. musb_ep_select(mbase, epnum);
  946. if (usb_endpoint_dir_in(desc)) {
  947. u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
  948. if (hw_ep->is_shared_fifo)
  949. musb_ep->is_in = 1;
  950. if (!musb_ep->is_in)
  951. goto fail;
  952. if (tmp > hw_ep->max_packet_sz_tx) {
  953. dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
  954. goto fail;
  955. }
  956. int_txe |= (1 << epnum);
  957. musb_writew(mbase, MUSB_INTRTXE, int_txe);
  958. /* REVISIT if can_bulk_split(), use by updating "tmp";
  959. * likewise high bandwidth periodic tx
  960. */
  961. /* Set TXMAXP with the FIFO size of the endpoint
  962. * to disable double buffering mode.
  963. */
  964. if (musb->double_buffer_not_ok)
  965. musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
  966. else
  967. musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
  968. | (musb_ep->hb_mult << 11));
  969. csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
  970. if (musb_readw(regs, MUSB_TXCSR)
  971. & MUSB_TXCSR_FIFONOTEMPTY)
  972. csr |= MUSB_TXCSR_FLUSHFIFO;
  973. if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
  974. csr |= MUSB_TXCSR_P_ISO;
  975. /* set twice in case of double buffering */
  976. musb_writew(regs, MUSB_TXCSR, csr);
  977. /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
  978. musb_writew(regs, MUSB_TXCSR, csr);
  979. } else {
  980. u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
  981. if (hw_ep->is_shared_fifo)
  982. musb_ep->is_in = 0;
  983. if (musb_ep->is_in)
  984. goto fail;
  985. if (tmp > hw_ep->max_packet_sz_rx) {
  986. dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
  987. goto fail;
  988. }
  989. int_rxe |= (1 << epnum);
  990. musb_writew(mbase, MUSB_INTRRXE, int_rxe);
  991. /* REVISIT if can_bulk_combine() use by updating "tmp"
  992. * likewise high bandwidth periodic rx
  993. */
  994. /* Set RXMAXP with the FIFO size of the endpoint
  995. * to disable double buffering mode.
  996. */
  997. if (musb->double_buffer_not_ok)
  998. musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
  999. else
  1000. musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
  1001. | (musb_ep->hb_mult << 11));
  1002. /* force shared fifo to OUT-only mode */
  1003. if (hw_ep->is_shared_fifo) {
  1004. csr = musb_readw(regs, MUSB_TXCSR);
  1005. csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
  1006. musb_writew(regs, MUSB_TXCSR, csr);
  1007. }
  1008. csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
  1009. if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
  1010. csr |= MUSB_RXCSR_P_ISO;
  1011. else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
  1012. csr |= MUSB_RXCSR_DISNYET;
  1013. /* set twice in case of double buffering */
  1014. musb_writew(regs, MUSB_RXCSR, csr);
  1015. musb_writew(regs, MUSB_RXCSR, csr);
  1016. }
  1017. /* NOTE: all the I/O code _should_ work fine without DMA, in case
  1018. * for some reason you run out of channels here.
  1019. */
  1020. if (is_dma_capable() && musb->dma_controller) {
  1021. struct dma_controller *c = musb->dma_controller;
  1022. musb_ep->dma = c->channel_alloc(c, hw_ep,
  1023. (desc->bEndpointAddress & USB_DIR_IN));
  1024. } else
  1025. musb_ep->dma = NULL;
  1026. musb_ep->desc = desc;
  1027. musb_ep->busy = 0;
  1028. musb_ep->wedged = 0;
  1029. status = 0;
  1030. pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
  1031. musb_driver_name, musb_ep->end_point.name,
  1032. ({ char *s; switch (musb_ep->type) {
  1033. case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
  1034. case USB_ENDPOINT_XFER_INT: s = "int"; break;
  1035. default: s = "iso"; break;
  1036. }; s; }),
  1037. musb_ep->is_in ? "IN" : "OUT",
  1038. musb_ep->dma ? "dma, " : "",
  1039. musb_ep->packet_sz);
  1040. schedule_work(&musb->irq_work);
  1041. fail:
  1042. spin_unlock_irqrestore(&musb->lock, flags);
  1043. return status;
  1044. }
  1045. /*
  1046. * Disable an endpoint flushing all requests queued.
  1047. */
  1048. static int musb_gadget_disable(struct usb_ep *ep)
  1049. {
  1050. unsigned long flags;
  1051. struct musb *musb;
  1052. u8 epnum;
  1053. struct musb_ep *musb_ep;
  1054. void __iomem *epio;
  1055. int status = 0;
  1056. musb_ep = to_musb_ep(ep);
  1057. musb = musb_ep->musb;
  1058. epnum = musb_ep->current_epnum;
  1059. epio = musb->endpoints[epnum].regs;
  1060. spin_lock_irqsave(&musb->lock, flags);
  1061. musb_ep_select(musb->mregs, epnum);
  1062. /* zero the endpoint sizes */
  1063. if (musb_ep->is_in) {
  1064. u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
  1065. int_txe &= ~(1 << epnum);
  1066. musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
  1067. musb_writew(epio, MUSB_TXMAXP, 0);
  1068. } else {
  1069. u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
  1070. int_rxe &= ~(1 << epnum);
  1071. musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
  1072. musb_writew(epio, MUSB_RXMAXP, 0);
  1073. }
  1074. musb_ep->desc = NULL;
  1075. #ifndef __UBOOT__
  1076. musb_ep->end_point.desc = NULL;
  1077. #endif
  1078. /* abort all pending DMA and requests */
  1079. nuke(musb_ep, -ESHUTDOWN);
  1080. schedule_work(&musb->irq_work);
  1081. spin_unlock_irqrestore(&(musb->lock), flags);
  1082. dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
  1083. return status;
  1084. }
  1085. /*
  1086. * Allocate a request for an endpoint.
  1087. * Reused by ep0 code.
  1088. */
  1089. struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1090. {
  1091. struct musb_ep *musb_ep = to_musb_ep(ep);
  1092. struct musb *musb = musb_ep->musb;
  1093. struct musb_request *request = NULL;
  1094. request = kzalloc(sizeof *request, gfp_flags);
  1095. if (!request) {
  1096. dev_dbg(musb->controller, "not enough memory\n");
  1097. return NULL;
  1098. }
  1099. request->request.dma = DMA_ADDR_INVALID;
  1100. request->epnum = musb_ep->current_epnum;
  1101. request->ep = musb_ep;
  1102. return &request->request;
  1103. }
  1104. /*
  1105. * Free a request
  1106. * Reused by ep0 code.
  1107. */
  1108. void musb_free_request(struct usb_ep *ep, struct usb_request *req)
  1109. {
  1110. kfree(to_musb_request(req));
  1111. }
  1112. static LIST_HEAD(buffers);
  1113. struct free_record {
  1114. struct list_head list;
  1115. struct device *dev;
  1116. unsigned bytes;
  1117. dma_addr_t dma;
  1118. };
  1119. /*
  1120. * Context: controller locked, IRQs blocked.
  1121. */
  1122. void musb_ep_restart(struct musb *musb, struct musb_request *req)
  1123. {
  1124. dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
  1125. req->tx ? "TX/IN" : "RX/OUT",
  1126. &req->request, req->request.length, req->epnum);
  1127. musb_ep_select(musb->mregs, req->epnum);
  1128. if (req->tx)
  1129. txstate(musb, req);
  1130. else
  1131. rxstate(musb, req);
  1132. }
  1133. static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
  1134. gfp_t gfp_flags)
  1135. {
  1136. struct musb_ep *musb_ep;
  1137. struct musb_request *request;
  1138. struct musb *musb;
  1139. int status = 0;
  1140. unsigned long lockflags;
  1141. if (!ep || !req)
  1142. return -EINVAL;
  1143. if (!req->buf)
  1144. return -ENODATA;
  1145. musb_ep = to_musb_ep(ep);
  1146. musb = musb_ep->musb;
  1147. request = to_musb_request(req);
  1148. request->musb = musb;
  1149. if (request->ep != musb_ep)
  1150. return -EINVAL;
  1151. dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
  1152. /* request is mine now... */
  1153. request->request.actual = 0;
  1154. request->request.status = -EINPROGRESS;
  1155. request->epnum = musb_ep->current_epnum;
  1156. request->tx = musb_ep->is_in;
  1157. map_dma_buffer(request, musb, musb_ep);
  1158. spin_lock_irqsave(&musb->lock, lockflags);
  1159. /* don't queue if the ep is down */
  1160. if (!musb_ep->desc) {
  1161. dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
  1162. req, ep->name, "disabled");
  1163. status = -ESHUTDOWN;
  1164. goto cleanup;
  1165. }
  1166. /* add request to the list */
  1167. list_add_tail(&request->list, &musb_ep->req_list);
  1168. /* it this is the head of the queue, start i/o ... */
  1169. if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
  1170. musb_ep_restart(musb, request);
  1171. cleanup:
  1172. spin_unlock_irqrestore(&musb->lock, lockflags);
  1173. return status;
  1174. }
  1175. static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
  1176. {
  1177. struct musb_ep *musb_ep = to_musb_ep(ep);
  1178. struct musb_request *req = to_musb_request(request);
  1179. struct musb_request *r;
  1180. unsigned long flags;
  1181. int status = 0;
  1182. struct musb *musb = musb_ep->musb;
  1183. if (!ep || !request || to_musb_request(request)->ep != musb_ep)
  1184. return -EINVAL;
  1185. spin_lock_irqsave(&musb->lock, flags);
  1186. list_for_each_entry(r, &musb_ep->req_list, list) {
  1187. if (r == req)
  1188. break;
  1189. }
  1190. if (r != req) {
  1191. dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
  1192. status = -EINVAL;
  1193. goto done;
  1194. }
  1195. /* if the hardware doesn't have the request, easy ... */
  1196. if (musb_ep->req_list.next != &req->list || musb_ep->busy)
  1197. musb_g_giveback(musb_ep, request, -ECONNRESET);
  1198. /* ... else abort the dma transfer ... */
  1199. else if (is_dma_capable() && musb_ep->dma) {
  1200. struct dma_controller *c = musb->dma_controller;
  1201. musb_ep_select(musb->mregs, musb_ep->current_epnum);
  1202. if (c->channel_abort)
  1203. status = c->channel_abort(musb_ep->dma);
  1204. else
  1205. status = -EBUSY;
  1206. if (status == 0)
  1207. musb_g_giveback(musb_ep, request, -ECONNRESET);
  1208. } else {
  1209. /* NOTE: by sticking to easily tested hardware/driver states,
  1210. * we leave counting of in-flight packets imprecise.
  1211. */
  1212. musb_g_giveback(musb_ep, request, -ECONNRESET);
  1213. }
  1214. done:
  1215. spin_unlock_irqrestore(&musb->lock, flags);
  1216. return status;
  1217. }
  1218. /*
  1219. * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
  1220. * data but will queue requests.
  1221. *
  1222. * exported to ep0 code
  1223. */
  1224. static int musb_gadget_set_halt(struct usb_ep *ep, int value)
  1225. {
  1226. struct musb_ep *musb_ep = to_musb_ep(ep);
  1227. u8 epnum = musb_ep->current_epnum;
  1228. struct musb *musb = musb_ep->musb;
  1229. void __iomem *epio = musb->endpoints[epnum].regs;
  1230. void __iomem *mbase;
  1231. unsigned long flags;
  1232. u16 csr;
  1233. struct musb_request *request;
  1234. int status = 0;
  1235. if (!ep)
  1236. return -EINVAL;
  1237. mbase = musb->mregs;
  1238. spin_lock_irqsave(&musb->lock, flags);
  1239. if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
  1240. status = -EINVAL;
  1241. goto done;
  1242. }
  1243. musb_ep_select(mbase, epnum);
  1244. request = next_request(musb_ep);
  1245. if (value) {
  1246. if (request) {
  1247. dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
  1248. ep->name);
  1249. status = -EAGAIN;
  1250. goto done;
  1251. }
  1252. /* Cannot portably stall with non-empty FIFO */
  1253. if (musb_ep->is_in) {
  1254. csr = musb_readw(epio, MUSB_TXCSR);
  1255. if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
  1256. dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
  1257. status = -EAGAIN;
  1258. goto done;
  1259. }
  1260. }
  1261. } else
  1262. musb_ep->wedged = 0;
  1263. /* set/clear the stall and toggle bits */
  1264. dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
  1265. if (musb_ep->is_in) {
  1266. csr = musb_readw(epio, MUSB_TXCSR);
  1267. csr |= MUSB_TXCSR_P_WZC_BITS
  1268. | MUSB_TXCSR_CLRDATATOG;
  1269. if (value)
  1270. csr |= MUSB_TXCSR_P_SENDSTALL;
  1271. else
  1272. csr &= ~(MUSB_TXCSR_P_SENDSTALL
  1273. | MUSB_TXCSR_P_SENTSTALL);
  1274. csr &= ~MUSB_TXCSR_TXPKTRDY;
  1275. musb_writew(epio, MUSB_TXCSR, csr);
  1276. } else {
  1277. csr = musb_readw(epio, MUSB_RXCSR);
  1278. csr |= MUSB_RXCSR_P_WZC_BITS
  1279. | MUSB_RXCSR_FLUSHFIFO
  1280. | MUSB_RXCSR_CLRDATATOG;
  1281. if (value)
  1282. csr |= MUSB_RXCSR_P_SENDSTALL;
  1283. else
  1284. csr &= ~(MUSB_RXCSR_P_SENDSTALL
  1285. | MUSB_RXCSR_P_SENTSTALL);
  1286. musb_writew(epio, MUSB_RXCSR, csr);
  1287. }
  1288. /* maybe start the first request in the queue */
  1289. if (!musb_ep->busy && !value && request) {
  1290. dev_dbg(musb->controller, "restarting the request\n");
  1291. musb_ep_restart(musb, request);
  1292. }
  1293. done:
  1294. spin_unlock_irqrestore(&musb->lock, flags);
  1295. return status;
  1296. }
  1297. #ifndef __UBOOT__
  1298. /*
  1299. * Sets the halt feature with the clear requests ignored
  1300. */
  1301. static int musb_gadget_set_wedge(struct usb_ep *ep)
  1302. {
  1303. struct musb_ep *musb_ep = to_musb_ep(ep);
  1304. if (!ep)
  1305. return -EINVAL;
  1306. musb_ep->wedged = 1;
  1307. return usb_ep_set_halt(ep);
  1308. }
  1309. #endif
  1310. static int musb_gadget_fifo_status(struct usb_ep *ep)
  1311. {
  1312. struct musb_ep *musb_ep = to_musb_ep(ep);
  1313. void __iomem *epio = musb_ep->hw_ep->regs;
  1314. int retval = -EINVAL;
  1315. if (musb_ep->desc && !musb_ep->is_in) {
  1316. struct musb *musb = musb_ep->musb;
  1317. int epnum = musb_ep->current_epnum;
  1318. void __iomem *mbase = musb->mregs;
  1319. unsigned long flags;
  1320. spin_lock_irqsave(&musb->lock, flags);
  1321. musb_ep_select(mbase, epnum);
  1322. /* FIXME return zero unless RXPKTRDY is set */
  1323. retval = musb_readw(epio, MUSB_RXCOUNT);
  1324. spin_unlock_irqrestore(&musb->lock, flags);
  1325. }
  1326. return retval;
  1327. }
  1328. static void musb_gadget_fifo_flush(struct usb_ep *ep)
  1329. {
  1330. struct musb_ep *musb_ep = to_musb_ep(ep);
  1331. struct musb *musb = musb_ep->musb;
  1332. u8 epnum = musb_ep->current_epnum;
  1333. void __iomem *epio = musb->endpoints[epnum].regs;
  1334. void __iomem *mbase;
  1335. unsigned long flags;
  1336. u16 csr, int_txe;
  1337. mbase = musb->mregs;
  1338. spin_lock_irqsave(&musb->lock, flags);
  1339. musb_ep_select(mbase, (u8) epnum);
  1340. /* disable interrupts */
  1341. int_txe = musb_readw(mbase, MUSB_INTRTXE);
  1342. musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
  1343. if (musb_ep->is_in) {
  1344. csr = musb_readw(epio, MUSB_TXCSR);
  1345. if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
  1346. csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
  1347. /*
  1348. * Setting both TXPKTRDY and FLUSHFIFO makes controller
  1349. * to interrupt current FIFO loading, but not flushing
  1350. * the already loaded ones.
  1351. */
  1352. csr &= ~MUSB_TXCSR_TXPKTRDY;
  1353. musb_writew(epio, MUSB_TXCSR, csr);
  1354. /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
  1355. musb_writew(epio, MUSB_TXCSR, csr);
  1356. }
  1357. } else {
  1358. csr = musb_readw(epio, MUSB_RXCSR);
  1359. csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
  1360. musb_writew(epio, MUSB_RXCSR, csr);
  1361. musb_writew(epio, MUSB_RXCSR, csr);
  1362. }
  1363. /* re-enable interrupt */
  1364. musb_writew(mbase, MUSB_INTRTXE, int_txe);
  1365. spin_unlock_irqrestore(&musb->lock, flags);
  1366. }
  1367. static const struct usb_ep_ops musb_ep_ops = {
  1368. .enable = musb_gadget_enable,
  1369. .disable = musb_gadget_disable,
  1370. .alloc_request = musb_alloc_request,
  1371. .free_request = musb_free_request,
  1372. .queue = musb_gadget_queue,
  1373. .dequeue = musb_gadget_dequeue,
  1374. .set_halt = musb_gadget_set_halt,
  1375. #ifndef __UBOOT__
  1376. .set_wedge = musb_gadget_set_wedge,
  1377. #endif
  1378. .fifo_status = musb_gadget_fifo_status,
  1379. .fifo_flush = musb_gadget_fifo_flush
  1380. };
  1381. /* ----------------------------------------------------------------------- */
  1382. static int musb_gadget_get_frame(struct usb_gadget *gadget)
  1383. {
  1384. struct musb *musb = gadget_to_musb(gadget);
  1385. return (int)musb_readw(musb->mregs, MUSB_FRAME);
  1386. }
  1387. static int musb_gadget_wakeup(struct usb_gadget *gadget)
  1388. {
  1389. #ifndef __UBOOT__
  1390. struct musb *musb = gadget_to_musb(gadget);
  1391. void __iomem *mregs = musb->mregs;
  1392. unsigned long flags;
  1393. int status = -EINVAL;
  1394. u8 power, devctl;
  1395. int retries;
  1396. spin_lock_irqsave(&musb->lock, flags);
  1397. switch (musb->xceiv->state) {
  1398. case OTG_STATE_B_PERIPHERAL:
  1399. /* NOTE: OTG state machine doesn't include B_SUSPENDED;
  1400. * that's part of the standard usb 1.1 state machine, and
  1401. * doesn't affect OTG transitions.
  1402. */
  1403. if (musb->may_wakeup && musb->is_suspended)
  1404. break;
  1405. goto done;
  1406. case OTG_STATE_B_IDLE:
  1407. /* Start SRP ... OTG not required. */
  1408. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1409. dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
  1410. devctl |= MUSB_DEVCTL_SESSION;
  1411. musb_writeb(mregs, MUSB_DEVCTL, devctl);
  1412. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1413. retries = 100;
  1414. while (!(devctl & MUSB_DEVCTL_SESSION)) {
  1415. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1416. if (retries-- < 1)
  1417. break;
  1418. }
  1419. retries = 10000;
  1420. while (devctl & MUSB_DEVCTL_SESSION) {
  1421. devctl = musb_readb(mregs, MUSB_DEVCTL);
  1422. if (retries-- < 1)
  1423. break;
  1424. }
  1425. spin_unlock_irqrestore(&musb->lock, flags);
  1426. otg_start_srp(musb->xceiv->otg);
  1427. spin_lock_irqsave(&musb->lock, flags);
  1428. /* Block idling for at least 1s */
  1429. musb_platform_try_idle(musb,
  1430. jiffies + msecs_to_jiffies(1 * HZ));
  1431. status = 0;
  1432. goto done;
  1433. default:
  1434. dev_dbg(musb->controller, "Unhandled wake: %s\n",
  1435. otg_state_string(musb->xceiv->state));
  1436. goto done;
  1437. }
  1438. status = 0;
  1439. power = musb_readb(mregs, MUSB_POWER);
  1440. power |= MUSB_POWER_RESUME;
  1441. musb_writeb(mregs, MUSB_POWER, power);
  1442. dev_dbg(musb->controller, "issue wakeup\n");
  1443. /* FIXME do this next chunk in a timer callback, no udelay */
  1444. mdelay(2);
  1445. power = musb_readb(mregs, MUSB_POWER);
  1446. power &= ~MUSB_POWER_RESUME;
  1447. musb_writeb(mregs, MUSB_POWER, power);
  1448. done:
  1449. spin_unlock_irqrestore(&musb->lock, flags);
  1450. return status;
  1451. #else
  1452. return 0;
  1453. #endif
  1454. }
  1455. static int
  1456. musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
  1457. {
  1458. struct musb *musb = gadget_to_musb(gadget);
  1459. musb->is_self_powered = !!is_selfpowered;
  1460. return 0;
  1461. }
  1462. static void musb_pullup(struct musb *musb, int is_on)
  1463. {
  1464. u8 power;
  1465. power = musb_readb(musb->mregs, MUSB_POWER);
  1466. if (is_on)
  1467. power |= MUSB_POWER_SOFTCONN;
  1468. else
  1469. power &= ~MUSB_POWER_SOFTCONN;
  1470. /* FIXME if on, HdrcStart; if off, HdrcStop */
  1471. dev_dbg(musb->controller, "gadget D+ pullup %s\n",
  1472. is_on ? "on" : "off");
  1473. musb_writeb(musb->mregs, MUSB_POWER, power);
  1474. }
  1475. #if 0
  1476. static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
  1477. {
  1478. dev_dbg(musb->controller, "<= %s =>\n", __func__);
  1479. /*
  1480. * FIXME iff driver's softconnect flag is set (as it is during probe,
  1481. * though that can clear it), just musb_pullup().
  1482. */
  1483. return -EINVAL;
  1484. }
  1485. #endif
  1486. static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
  1487. {
  1488. #ifndef __UBOOT__
  1489. struct musb *musb = gadget_to_musb(gadget);
  1490. if (!musb->xceiv->set_power)
  1491. return -EOPNOTSUPP;
  1492. return usb_phy_set_power(musb->xceiv, mA);
  1493. #else
  1494. return 0;
  1495. #endif
  1496. }
  1497. static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
  1498. {
  1499. struct musb *musb = gadget_to_musb(gadget);
  1500. unsigned long flags;
  1501. is_on = !!is_on;
  1502. pm_runtime_get_sync(musb->controller);
  1503. /* NOTE: this assumes we are sensing vbus; we'd rather
  1504. * not pullup unless the B-session is active.
  1505. */
  1506. spin_lock_irqsave(&musb->lock, flags);
  1507. if (is_on != musb->softconnect) {
  1508. musb->softconnect = is_on;
  1509. musb_pullup(musb, is_on);
  1510. }
  1511. spin_unlock_irqrestore(&musb->lock, flags);
  1512. pm_runtime_put(musb->controller);
  1513. return 0;
  1514. }
  1515. #ifndef __UBOOT__
  1516. static int musb_gadget_start(struct usb_gadget *g,
  1517. struct usb_gadget_driver *driver);
  1518. static int musb_gadget_stop(struct usb_gadget *g,
  1519. struct usb_gadget_driver *driver);
  1520. #else
  1521. static int musb_gadget_stop(struct usb_gadget *g)
  1522. {
  1523. struct musb *musb = gadget_to_musb(g);
  1524. musb_stop(musb);
  1525. return 0;
  1526. }
  1527. #endif
  1528. static const struct usb_gadget_ops musb_gadget_operations = {
  1529. .get_frame = musb_gadget_get_frame,
  1530. .wakeup = musb_gadget_wakeup,
  1531. .set_selfpowered = musb_gadget_set_self_powered,
  1532. /* .vbus_session = musb_gadget_vbus_session, */
  1533. .vbus_draw = musb_gadget_vbus_draw,
  1534. .pullup = musb_gadget_pullup,
  1535. #ifndef __UBOOT__
  1536. .udc_start = musb_gadget_start,
  1537. .udc_stop = musb_gadget_stop,
  1538. #else
  1539. .udc_start = musb_gadget_start,
  1540. .udc_stop = musb_gadget_stop,
  1541. #endif
  1542. };
  1543. /* ----------------------------------------------------------------------- */
  1544. /* Registration */
  1545. /* Only this registration code "knows" the rule (from USB standards)
  1546. * about there being only one external upstream port. It assumes
  1547. * all peripheral ports are external...
  1548. */
  1549. #ifndef __UBOOT__
  1550. static void musb_gadget_release(struct device *dev)
  1551. {
  1552. /* kref_put(WHAT) */
  1553. dev_dbg(dev, "%s\n", __func__);
  1554. }
  1555. #endif
  1556. static void __devinit
  1557. init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
  1558. {
  1559. struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
  1560. memset(ep, 0, sizeof *ep);
  1561. ep->current_epnum = epnum;
  1562. ep->musb = musb;
  1563. ep->hw_ep = hw_ep;
  1564. ep->is_in = is_in;
  1565. INIT_LIST_HEAD(&ep->req_list);
  1566. sprintf(ep->name, "ep%d%s", epnum,
  1567. (!epnum || hw_ep->is_shared_fifo) ? "" : (
  1568. is_in ? "in" : "out"));
  1569. ep->end_point.name = ep->name;
  1570. INIT_LIST_HEAD(&ep->end_point.ep_list);
  1571. if (!epnum) {
  1572. ep->end_point.maxpacket = 64;
  1573. ep->end_point.ops = &musb_g_ep0_ops;
  1574. musb->g.ep0 = &ep->end_point;
  1575. } else {
  1576. if (is_in)
  1577. ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
  1578. else
  1579. ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
  1580. ep->end_point.ops = &musb_ep_ops;
  1581. list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
  1582. }
  1583. }
  1584. /*
  1585. * Initialize the endpoints exposed to peripheral drivers, with backlinks
  1586. * to the rest of the driver state.
  1587. */
  1588. static inline void __devinit musb_g_init_endpoints(struct musb *musb)
  1589. {
  1590. u8 epnum;
  1591. struct musb_hw_ep *hw_ep;
  1592. unsigned count = 0;
  1593. /* initialize endpoint list just once */
  1594. INIT_LIST_HEAD(&(musb->g.ep_list));
  1595. for (epnum = 0, hw_ep = musb->endpoints;
  1596. epnum < musb->nr_endpoints;
  1597. epnum++, hw_ep++) {
  1598. if (hw_ep->is_shared_fifo /* || !epnum */) {
  1599. init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
  1600. count++;
  1601. } else {
  1602. if (hw_ep->max_packet_sz_tx) {
  1603. init_peripheral_ep(musb, &hw_ep->ep_in,
  1604. epnum, 1);
  1605. count++;
  1606. }
  1607. if (hw_ep->max_packet_sz_rx) {
  1608. init_peripheral_ep(musb, &hw_ep->ep_out,
  1609. epnum, 0);
  1610. count++;
  1611. }
  1612. }
  1613. }
  1614. }
  1615. /* called once during driver setup to initialize and link into
  1616. * the driver model; memory is zeroed.
  1617. */
  1618. int __devinit musb_gadget_setup(struct musb *musb)
  1619. {
  1620. int status;
  1621. /* REVISIT minor race: if (erroneously) setting up two
  1622. * musb peripherals at the same time, only the bus lock
  1623. * is probably held.
  1624. */
  1625. musb->g.ops = &musb_gadget_operations;
  1626. #ifndef __UBOOT__
  1627. musb->g.max_speed = USB_SPEED_HIGH;
  1628. #endif
  1629. musb->g.speed = USB_SPEED_UNKNOWN;
  1630. #ifndef __UBOOT__
  1631. /* this "gadget" abstracts/virtualizes the controller */
  1632. dev_set_name(&musb->g.dev, "gadget");
  1633. musb->g.dev.parent = musb->controller;
  1634. musb->g.dev.dma_mask = musb->controller->dma_mask;
  1635. musb->g.dev.release = musb_gadget_release;
  1636. #endif
  1637. musb->g.name = musb_driver_name;
  1638. #ifndef __UBOOT__
  1639. if (is_otg_enabled(musb))
  1640. musb->g.is_otg = 1;
  1641. #endif
  1642. musb_g_init_endpoints(musb);
  1643. musb->is_active = 0;
  1644. musb_platform_try_idle(musb, 0);
  1645. #ifndef __UBOOT__
  1646. status = device_register(&musb->g.dev);
  1647. if (status != 0) {
  1648. put_device(&musb->g.dev);
  1649. return status;
  1650. }
  1651. status = usb_add_gadget_udc(musb->controller, &musb->g);
  1652. if (status)
  1653. goto err;
  1654. #endif
  1655. return 0;
  1656. #ifndef __UBOOT__
  1657. err:
  1658. musb->g.dev.parent = NULL;
  1659. device_unregister(&musb->g.dev);
  1660. return status;
  1661. #endif
  1662. }
  1663. void musb_gadget_cleanup(struct musb *musb)
  1664. {
  1665. #ifndef __UBOOT__
  1666. usb_del_gadget_udc(&musb->g);
  1667. if (musb->g.dev.parent)
  1668. device_unregister(&musb->g.dev);
  1669. #endif
  1670. }
  1671. /*
  1672. * Register the gadget driver. Used by gadget drivers when
  1673. * registering themselves with the controller.
  1674. *
  1675. * -EINVAL something went wrong (not driver)
  1676. * -EBUSY another gadget is already using the controller
  1677. * -ENOMEM no memory to perform the operation
  1678. *
  1679. * @param driver the gadget driver
  1680. * @return <0 if error, 0 if everything is fine
  1681. */
  1682. #ifndef __UBOOT__
  1683. static int musb_gadget_start(struct usb_gadget *g,
  1684. struct usb_gadget_driver *driver)
  1685. #else
  1686. int musb_gadget_start(struct usb_gadget *g,
  1687. struct usb_gadget_driver *driver)
  1688. #endif
  1689. {
  1690. struct musb *musb = gadget_to_musb(g);
  1691. #ifndef __UBOOT__
  1692. struct usb_otg *otg = musb->xceiv->otg;
  1693. #endif
  1694. unsigned long flags;
  1695. int retval = -EINVAL;
  1696. #ifndef __UBOOT__
  1697. if (driver->max_speed < USB_SPEED_HIGH)
  1698. goto err0;
  1699. #endif
  1700. pm_runtime_get_sync(musb->controller);
  1701. #ifndef __UBOOT__
  1702. dev_dbg(musb->controller, "registering driver %s\n", driver->function);
  1703. #endif
  1704. musb->softconnect = 0;
  1705. musb->gadget_driver = driver;
  1706. spin_lock_irqsave(&musb->lock, flags);
  1707. musb->is_active = 1;
  1708. #ifndef __UBOOT__
  1709. otg_set_peripheral(otg, &musb->g);
  1710. musb->xceiv->state = OTG_STATE_B_IDLE;
  1711. /*
  1712. * FIXME this ignores the softconnect flag. Drivers are
  1713. * allowed hold the peripheral inactive until for example
  1714. * userspace hooks up printer hardware or DSP codecs, so
  1715. * hosts only see fully functional devices.
  1716. */
  1717. if (!is_otg_enabled(musb))
  1718. #endif
  1719. musb_start(musb);
  1720. spin_unlock_irqrestore(&musb->lock, flags);
  1721. #ifndef __UBOOT__
  1722. if (is_otg_enabled(musb)) {
  1723. struct usb_hcd *hcd = musb_to_hcd(musb);
  1724. dev_dbg(musb->controller, "OTG startup...\n");
  1725. /* REVISIT: funcall to other code, which also
  1726. * handles power budgeting ... this way also
  1727. * ensures HdrcStart is indirectly called.
  1728. */
  1729. retval = usb_add_hcd(musb_to_hcd(musb), 0, 0);
  1730. if (retval < 0) {
  1731. dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
  1732. goto err2;
  1733. }
  1734. if ((musb->xceiv->last_event == USB_EVENT_ID)
  1735. && otg->set_vbus)
  1736. otg_set_vbus(otg, 1);
  1737. hcd->self.uses_pio_for_control = 1;
  1738. }
  1739. if (musb->xceiv->last_event == USB_EVENT_NONE)
  1740. pm_runtime_put(musb->controller);
  1741. #endif
  1742. return 0;
  1743. #ifndef __UBOOT__
  1744. err2:
  1745. if (!is_otg_enabled(musb))
  1746. musb_stop(musb);
  1747. err0:
  1748. return retval;
  1749. #endif
  1750. }
  1751. #ifndef __UBOOT__
  1752. static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
  1753. {
  1754. int i;
  1755. struct musb_hw_ep *hw_ep;
  1756. /* don't disconnect if it's not connected */
  1757. if (musb->g.speed == USB_SPEED_UNKNOWN)
  1758. driver = NULL;
  1759. else
  1760. musb->g.speed = USB_SPEED_UNKNOWN;
  1761. /* deactivate the hardware */
  1762. if (musb->softconnect) {
  1763. musb->softconnect = 0;
  1764. musb_pullup(musb, 0);
  1765. }
  1766. musb_stop(musb);
  1767. /* killing any outstanding requests will quiesce the driver;
  1768. * then report disconnect
  1769. */
  1770. if (driver) {
  1771. for (i = 0, hw_ep = musb->endpoints;
  1772. i < musb->nr_endpoints;
  1773. i++, hw_ep++) {
  1774. musb_ep_select(musb->mregs, i);
  1775. if (hw_ep->is_shared_fifo /* || !epnum */) {
  1776. nuke(&hw_ep->ep_in, -ESHUTDOWN);
  1777. } else {
  1778. if (hw_ep->max_packet_sz_tx)
  1779. nuke(&hw_ep->ep_in, -ESHUTDOWN);
  1780. if (hw_ep->max_packet_sz_rx)
  1781. nuke(&hw_ep->ep_out, -ESHUTDOWN);
  1782. }
  1783. }
  1784. }
  1785. }
  1786. /*
  1787. * Unregister the gadget driver. Used by gadget drivers when
  1788. * unregistering themselves from the controller.
  1789. *
  1790. * @param driver the gadget driver to unregister
  1791. */
  1792. static int musb_gadget_stop(struct usb_gadget *g,
  1793. struct usb_gadget_driver *driver)
  1794. {
  1795. struct musb *musb = gadget_to_musb(g);
  1796. unsigned long flags;
  1797. if (musb->xceiv->last_event == USB_EVENT_NONE)
  1798. pm_runtime_get_sync(musb->controller);
  1799. /*
  1800. * REVISIT always use otg_set_peripheral() here too;
  1801. * this needs to shut down the OTG engine.
  1802. */
  1803. spin_lock_irqsave(&musb->lock, flags);
  1804. musb_hnp_stop(musb);
  1805. (void) musb_gadget_vbus_draw(&musb->g, 0);
  1806. musb->xceiv->state = OTG_STATE_UNDEFINED;
  1807. stop_activity(musb, driver);
  1808. otg_set_peripheral(musb->xceiv->otg, NULL);
  1809. dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
  1810. musb->is_active = 0;
  1811. musb_platform_try_idle(musb, 0);
  1812. spin_unlock_irqrestore(&musb->lock, flags);
  1813. if (is_otg_enabled(musb)) {
  1814. usb_remove_hcd(musb_to_hcd(musb));
  1815. /* FIXME we need to be able to register another
  1816. * gadget driver here and have everything work;
  1817. * that currently misbehaves.
  1818. */
  1819. }
  1820. if (!is_otg_enabled(musb))
  1821. musb_stop(musb);
  1822. pm_runtime_put(musb->controller);
  1823. return 0;
  1824. }
  1825. #endif
  1826. /* ----------------------------------------------------------------------- */
  1827. /* lifecycle operations called through plat_uds.c */
  1828. void musb_g_resume(struct musb *musb)
  1829. {
  1830. #ifndef __UBOOT__
  1831. musb->is_suspended = 0;
  1832. switch (musb->xceiv->state) {
  1833. case OTG_STATE_B_IDLE:
  1834. break;
  1835. case OTG_STATE_B_WAIT_ACON:
  1836. case OTG_STATE_B_PERIPHERAL:
  1837. musb->is_active = 1;
  1838. if (musb->gadget_driver && musb->gadget_driver->resume) {
  1839. spin_unlock(&musb->lock);
  1840. musb->gadget_driver->resume(&musb->g);
  1841. spin_lock(&musb->lock);
  1842. }
  1843. break;
  1844. default:
  1845. WARNING("unhandled RESUME transition (%s)\n",
  1846. otg_state_string(musb->xceiv->state));
  1847. }
  1848. #endif
  1849. }
  1850. /* called when SOF packets stop for 3+ msec */
  1851. void musb_g_suspend(struct musb *musb)
  1852. {
  1853. #ifndef __UBOOT__
  1854. u8 devctl;
  1855. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1856. dev_dbg(musb->controller, "devctl %02x\n", devctl);
  1857. switch (musb->xceiv->state) {
  1858. case OTG_STATE_B_IDLE:
  1859. if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
  1860. musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
  1861. break;
  1862. case OTG_STATE_B_PERIPHERAL:
  1863. musb->is_suspended = 1;
  1864. if (musb->gadget_driver && musb->gadget_driver->suspend) {
  1865. spin_unlock(&musb->lock);
  1866. musb->gadget_driver->suspend(&musb->g);
  1867. spin_lock(&musb->lock);
  1868. }
  1869. break;
  1870. default:
  1871. /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
  1872. * A_PERIPHERAL may need care too
  1873. */
  1874. WARNING("unhandled SUSPEND transition (%s)\n",
  1875. otg_state_string(musb->xceiv->state));
  1876. }
  1877. #endif
  1878. }
  1879. /* Called during SRP */
  1880. void musb_g_wakeup(struct musb *musb)
  1881. {
  1882. musb_gadget_wakeup(&musb->g);
  1883. }
  1884. /* called when VBUS drops below session threshold, and in other cases */
  1885. void musb_g_disconnect(struct musb *musb)
  1886. {
  1887. void __iomem *mregs = musb->mregs;
  1888. u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
  1889. dev_dbg(musb->controller, "devctl %02x\n", devctl);
  1890. /* clear HR */
  1891. musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
  1892. /* don't draw vbus until new b-default session */
  1893. (void) musb_gadget_vbus_draw(&musb->g, 0);
  1894. musb->g.speed = USB_SPEED_UNKNOWN;
  1895. if (musb->gadget_driver && musb->gadget_driver->disconnect) {
  1896. spin_unlock(&musb->lock);
  1897. musb->gadget_driver->disconnect(&musb->g);
  1898. spin_lock(&musb->lock);
  1899. }
  1900. #ifndef __UBOOT__
  1901. switch (musb->xceiv->state) {
  1902. default:
  1903. dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
  1904. otg_state_string(musb->xceiv->state));
  1905. musb->xceiv->state = OTG_STATE_A_IDLE;
  1906. MUSB_HST_MODE(musb);
  1907. break;
  1908. case OTG_STATE_A_PERIPHERAL:
  1909. musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
  1910. MUSB_HST_MODE(musb);
  1911. break;
  1912. case OTG_STATE_B_WAIT_ACON:
  1913. case OTG_STATE_B_HOST:
  1914. case OTG_STATE_B_PERIPHERAL:
  1915. case OTG_STATE_B_IDLE:
  1916. musb->xceiv->state = OTG_STATE_B_IDLE;
  1917. break;
  1918. case OTG_STATE_B_SRP_INIT:
  1919. break;
  1920. }
  1921. #endif
  1922. musb->is_active = 0;
  1923. }
  1924. void musb_g_reset(struct musb *musb)
  1925. __releases(musb->lock)
  1926. __acquires(musb->lock)
  1927. {
  1928. void __iomem *mbase = musb->mregs;
  1929. u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
  1930. u8 power;
  1931. #ifndef __UBOOT__
  1932. dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
  1933. (devctl & MUSB_DEVCTL_BDEVICE)
  1934. ? "B-Device" : "A-Device",
  1935. musb_readb(mbase, MUSB_FADDR),
  1936. musb->gadget_driver
  1937. ? musb->gadget_driver->driver.name
  1938. : NULL
  1939. );
  1940. #endif
  1941. /* report disconnect, if we didn't already (flushing EP state) */
  1942. if (musb->g.speed != USB_SPEED_UNKNOWN)
  1943. musb_g_disconnect(musb);
  1944. /* clear HR */
  1945. else if (devctl & MUSB_DEVCTL_HR)
  1946. musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
  1947. /* what speed did we negotiate? */
  1948. power = musb_readb(mbase, MUSB_POWER);
  1949. musb->g.speed = (power & MUSB_POWER_HSMODE)
  1950. ? USB_SPEED_HIGH : USB_SPEED_FULL;
  1951. /* start in USB_STATE_DEFAULT */
  1952. musb->is_active = 1;
  1953. musb->is_suspended = 0;
  1954. MUSB_DEV_MODE(musb);
  1955. musb->address = 0;
  1956. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  1957. musb->may_wakeup = 0;
  1958. musb->g.b_hnp_enable = 0;
  1959. musb->g.a_alt_hnp_support = 0;
  1960. musb->g.a_hnp_support = 0;
  1961. #ifndef __UBOOT__
  1962. /* Normal reset, as B-Device;
  1963. * or else after HNP, as A-Device
  1964. */
  1965. if (devctl & MUSB_DEVCTL_BDEVICE) {
  1966. musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
  1967. musb->g.is_a_peripheral = 0;
  1968. } else if (is_otg_enabled(musb)) {
  1969. musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
  1970. musb->g.is_a_peripheral = 1;
  1971. } else
  1972. WARN_ON(1);
  1973. /* start with default limits on VBUS power draw */
  1974. (void) musb_gadget_vbus_draw(&musb->g,
  1975. is_otg_enabled(musb) ? 8 : 100);
  1976. #endif
  1977. }