mt85xx.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Mediatek "glue layer"
  4. *
  5. * Copyright (C) 2019-2021 by Mediatek
  6. * Based on the AllWinner SUNXI "glue layer" code.
  7. * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
  8. * Copyright (C) 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
  9. *
  10. * This file is part of the Inventra Controller Driver for Linux.
  11. */
  12. #include <common.h>
  13. #include <clk.h>
  14. #include <dm.h>
  15. #include <dm/device_compat.h>
  16. #include <dm/lists.h>
  17. #include <dm/root.h>
  18. #include <linux/delay.h>
  19. #include <linux/usb/musb.h>
  20. #include <usb.h>
  21. #include "linux-compat.h"
  22. #include "musb_core.h"
  23. #include "musb_uboot.h"
  24. #define DBG_I(fmt, ...) \
  25. pr_info(fmt, ##__VA_ARGS__)
  26. struct mtk_musb_config {
  27. struct musb_hdrc_config *config;
  28. };
  29. struct mtk_musb_glue {
  30. struct musb_host_data mdata;
  31. struct clk usbpllclk;
  32. struct clk usbmcuclk;
  33. struct clk usbclk;
  34. struct mtk_musb_config *cfg;
  35. struct device dev;
  36. };
  37. #define to_mtk_musb_glue(d) container_of(d, struct mtk_musb_glue, dev)
  38. /******************************************************************************
  39. * phy settings
  40. ******************************************************************************/
  41. #define USB20_PHY_BASE 0x11110800
  42. #define USBPHY_READ8(offset) \
  43. readb((void *)(USB20_PHY_BASE + (offset)))
  44. #define USBPHY_WRITE8(offset, value) \
  45. writeb(value, (void *)(USB20_PHY_BASE + (offset)))
  46. #define USBPHY_SET8(offset, mask) \
  47. USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) | (mask))
  48. #define USBPHY_CLR8(offset, mask) \
  49. USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) & (~(mask)))
  50. static void mt_usb_phy_poweron(void)
  51. {
  52. /*
  53. * switch to USB function.
  54. * (system register, force ip into usb mode).
  55. */
  56. USBPHY_CLR8(0x6b, 0x04);
  57. USBPHY_CLR8(0x6e, 0x01);
  58. USBPHY_CLR8(0x21, 0x03);
  59. /* RG_USB20_BC11_SW_EN = 1'b0 */
  60. USBPHY_SET8(0x22, 0x04);
  61. USBPHY_CLR8(0x1a, 0x80);
  62. /* RG_USB20_DP_100K_EN = 1'b0 */
  63. /* RG_USB20_DP_100K_EN = 1'b0 */
  64. USBPHY_CLR8(0x22, 0x03);
  65. /*OTG enable*/
  66. USBPHY_SET8(0x20, 0x10);
  67. /* release force suspendm */
  68. USBPHY_CLR8(0x6a, 0x04);
  69. mdelay(800);
  70. /* force enter device mode */
  71. USBPHY_CLR8(0x6c, 0x10);
  72. USBPHY_SET8(0x6c, 0x2E);
  73. USBPHY_SET8(0x6d, 0x3E);
  74. }
  75. static void mt_usb_phy_savecurrent(void)
  76. {
  77. /*
  78. * switch to USB function.
  79. * (system register, force ip into usb mode).
  80. */
  81. USBPHY_CLR8(0x6b, 0x04);
  82. USBPHY_CLR8(0x6e, 0x01);
  83. USBPHY_CLR8(0x21, 0x03);
  84. /* release force suspendm */
  85. USBPHY_CLR8(0x6a, 0x04);
  86. USBPHY_SET8(0x68, 0x04);
  87. /* RG_DPPULLDOWN./RG_DMPULLDOWN. */
  88. USBPHY_SET8(0x68, 0xc0);
  89. /* RG_XCVRSEL[1:0] = 2'b01 */
  90. USBPHY_CLR8(0x68, 0x30);
  91. USBPHY_SET8(0x68, 0x10);
  92. /* RG_TERMSEL = 1'b1 */
  93. USBPHY_SET8(0x68, 0x04);
  94. /* RG_DATAIN[3:0] = 4'b0000 */
  95. USBPHY_CLR8(0x69, 0x3c);
  96. /*
  97. * force_dp_pulldown, force_dm_pulldown,
  98. * force_xcversel, force_termsel.
  99. */
  100. USBPHY_SET8(0x6a, 0xba);
  101. /* RG_USB20_BC11_SW_EN = 1'b0 */
  102. USBPHY_CLR8(0x1a, 0x80);
  103. /* RG_USB20_OTG_VBUSSCMP_EN = 1'b0 */
  104. USBPHY_CLR8(0x1a, 0x10);
  105. mdelay(800);
  106. USBPHY_CLR8(0x6a, 0x04);
  107. /* rg_usb20_pll_stable = 1 */
  108. //USBPHY_SET8(0x63, 0x02);
  109. mdelay(1);
  110. /* force suspendm = 1 */
  111. //USBPHY_SET8(0x6a, 0x04);
  112. }
  113. static void mt_usb_phy_recover(void)
  114. {
  115. /* clean PUPD_BIST_EN */
  116. /* PUPD_BIST_EN = 1'b0 */
  117. /* PMIC will use it to detect charger type */
  118. USBPHY_CLR8(0x1d, 0x10);
  119. /* force_uart_en = 1'b0 */
  120. USBPHY_CLR8(0x6b, 0x04);
  121. /* RG_UART_EN = 1'b0 */
  122. USBPHY_CLR8(0x6e, 0x01);
  123. /* force_uart_en = 1'b0 */
  124. USBPHY_CLR8(0x6a, 0x04);
  125. USBPHY_CLR8(0x21, 0x03);
  126. USBPHY_CLR8(0x68, 0xf4);
  127. /* RG_DATAIN[3:0] = 4'b0000 */
  128. USBPHY_CLR8(0x69, 0x3c);
  129. USBPHY_CLR8(0x6a, 0xba);
  130. /* RG_USB20_BC11_SW_EN = 1'b0 */
  131. USBPHY_CLR8(0x1a, 0x80);
  132. /* RG_USB20_OTG_VBUSSCMP_EN = 1'b1 */
  133. USBPHY_SET8(0x1a, 0x10);
  134. //HQA adjustment
  135. USBPHY_CLR8(0x18, 0x08);
  136. USBPHY_SET8(0x18, 0x06);
  137. mdelay(800);
  138. /* force enter device mode */
  139. //USBPHY_CLR8(0x6c, 0x10);
  140. //USBPHY_SET8(0x6c, 0x2E);
  141. //USBPHY_SET8(0x6d, 0x3E);
  142. /* enable VRT internal R architecture */
  143. /* RG_USB20_INTR_EN = 1'b1 */
  144. USBPHY_SET8(0x00, 0x20);
  145. }
  146. /******************************************************************************
  147. * MUSB Glue code
  148. ******************************************************************************/
  149. static irqreturn_t mtk_musb_interrupt(int irq, void *__hci)
  150. {
  151. struct musb *musb = __hci;
  152. irqreturn_t retval = IRQ_NONE;
  153. /* read and flush interrupts */
  154. musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
  155. // last_int_usb = musb->int_usb;
  156. if (musb->int_usb)
  157. musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
  158. musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
  159. if (musb->int_tx)
  160. musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
  161. musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
  162. if (musb->int_rx)
  163. musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
  164. if (musb->int_usb || musb->int_tx || musb->int_rx)
  165. retval |= musb_interrupt(musb);
  166. return retval;
  167. }
  168. /* musb_core does not call enable / disable in a balanced manner <sigh> */
  169. static bool enabled;
  170. static int mtk_musb_enable(struct musb *musb)
  171. {
  172. struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller);
  173. DBG_I("%s():\n", __func__);
  174. musb_ep_select(musb->mregs, 0);
  175. musb_writeb(musb->mregs, MUSB_FADDR, 0);
  176. if (enabled)
  177. return 0;
  178. mt_usb_phy_recover();
  179. enabled = true;
  180. return 0;
  181. }
  182. static void mtk_musb_disable(struct musb *musb)
  183. {
  184. struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller);
  185. int ret;
  186. DBG_I("%s():\n", __func__);
  187. if (!enabled)
  188. return;
  189. mt_usb_phy_savecurrent();
  190. enabled = false;
  191. }
  192. static int mtk_musb_init(struct musb *musb)
  193. {
  194. struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller);
  195. int ret;
  196. DBG_I("%s():\n", __func__);
  197. ret = clk_enable(&glue->usbpllclk);
  198. if (ret) {
  199. dev_err(musb->controller, "failed to enable usbpll clock\n");
  200. return ret;
  201. }
  202. ret = clk_enable(&glue->usbmcuclk);
  203. if (ret) {
  204. dev_err(musb->controller, "failed to enable usbmcu clock\n");
  205. return ret;
  206. }
  207. ret = clk_enable(&glue->usbclk);
  208. if (ret) {
  209. dev_err(musb->controller, "failed to enable usb clock\n");
  210. return ret;
  211. }
  212. musb->isr = mtk_musb_interrupt;
  213. return 0;
  214. }
  215. static int mtk_musb_exit(struct musb *musb)
  216. {
  217. struct mtk_musb_glue *glue = to_mtk_musb_glue(musb->controller);
  218. clk_disable(&glue->usbclk);
  219. clk_disable(&glue->usbmcuclk);
  220. clk_disable(&glue->usbpllclk);
  221. return 0;
  222. }
  223. static const struct musb_platform_ops mtk_musb_ops = {
  224. .init = mtk_musb_init,
  225. .exit = mtk_musb_exit,
  226. .enable = mtk_musb_enable,
  227. .disable = mtk_musb_disable,
  228. };
  229. /* MTK OTG supports up to 7 endpoints */
  230. #define MTK_MUSB_MAX_EP_NUM 8
  231. #define MTK_MUSB_RAM_BITS 16
  232. static struct musb_fifo_cfg mtk_musb_mode_cfg[] = {
  233. MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
  234. MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
  235. MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
  236. MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
  237. MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
  238. MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
  239. MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
  240. MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
  241. MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
  242. MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
  243. MUSB_EP_FIFO_SINGLE(6, FIFO_TX, 512),
  244. MUSB_EP_FIFO_SINGLE(6, FIFO_RX, 512),
  245. MUSB_EP_FIFO_SINGLE(7, FIFO_TX, 512),
  246. MUSB_EP_FIFO_SINGLE(7, FIFO_RX, 512),
  247. };
  248. static struct musb_hdrc_config musb_config = {
  249. .fifo_cfg = mtk_musb_mode_cfg,
  250. .fifo_cfg_size = ARRAY_SIZE(mtk_musb_mode_cfg),
  251. .multipoint = true,
  252. .dyn_fifo = true,
  253. .num_eps = MTK_MUSB_MAX_EP_NUM,
  254. .ram_bits = MTK_MUSB_RAM_BITS,
  255. };
  256. static int musb_usb_probe(struct udevice *dev)
  257. {
  258. struct mtk_musb_glue *glue = dev_get_priv(dev);
  259. struct musb_host_data *host = &glue->mdata;
  260. struct musb_hdrc_platform_data pdata;
  261. void *base = dev_read_addr_ptr(dev);
  262. int ret;
  263. DBG_I("%s():\n", __func__);
  264. #ifdef CONFIG_USB_MUSB_HOST
  265. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  266. #endif
  267. if (!base)
  268. return -EINVAL;
  269. glue->cfg = (struct mtk_musb_config *)dev_get_driver_data(dev);
  270. if (!glue->cfg)
  271. return -EINVAL;
  272. ret = clk_get_by_name(dev, "usbpll", &glue->usbpllclk);
  273. if (ret) {
  274. dev_err(dev, "failed to get usbpll clock\n");
  275. return ret;
  276. }
  277. ret = clk_get_by_name(dev, "usbmcu", &glue->usbmcuclk);
  278. if (ret) {
  279. dev_err(dev, "failed to get usbmcu clock\n");
  280. return ret;
  281. }
  282. ret = clk_get_by_name(dev, "usb", &glue->usbclk);
  283. if (ret) {
  284. dev_err(dev, "failed to get usb clock\n");
  285. return ret;
  286. }
  287. memset(&pdata, 0, sizeof(pdata));
  288. pdata.power = (u8)400;
  289. pdata.platform_ops = &mtk_musb_ops;
  290. pdata.config = glue->cfg->config;
  291. #ifdef CONFIG_USB_MUSB_HOST
  292. priv->desc_before_addr = true;
  293. pdata.mode = MUSB_HOST;
  294. host->host = musb_init_controller(&pdata, &glue->dev, base);
  295. if (!host->host)
  296. return -EIO;
  297. ret = musb_lowlevel_init(host);
  298. if (!ret)
  299. printf("MTK MUSB OTG (Host)\n");
  300. #else
  301. pdata.mode = MUSB_PERIPHERAL;
  302. host->host = musb_register(&pdata, &glue->dev, base);
  303. if (!host->host)
  304. return -EIO;
  305. printf("MTK MUSB OTG (Peripheral)\n");
  306. #endif
  307. mt_usb_phy_poweron();
  308. return ret;
  309. }
  310. static int musb_usb_remove(struct udevice *dev)
  311. {
  312. struct mtk_musb_glue *glue = dev_get_priv(dev);
  313. struct musb_host_data *host = &glue->mdata;
  314. musb_stop(host->host);
  315. free(host->host);
  316. host->host = NULL;
  317. return 0;
  318. }
  319. static const struct mtk_musb_config mt8518_cfg = {
  320. .config = &musb_config,
  321. };
  322. static const struct udevice_id mtk_musb_ids[] = {
  323. { .compatible = "mediatek,mt8518-musb",
  324. .data = (ulong)&mt8518_cfg },
  325. { }
  326. };
  327. U_BOOT_DRIVER(mtk_musb) = {
  328. .name = "mtk_musb",
  329. #ifdef CONFIG_USB_MUSB_HOST
  330. .id = UCLASS_USB,
  331. #else
  332. .id = UCLASS_USB_GADGET_GENERIC,
  333. #endif
  334. .of_match = mtk_musb_ids,
  335. .probe = musb_usb_probe,
  336. .remove = musb_usb_remove,
  337. #ifdef CONFIG_USB_MUSB_HOST
  338. .ops = &musb_usb_ops,
  339. #endif
  340. .platdata_auto_alloc_size = sizeof(struct usb_platdata),
  341. .priv_auto_alloc_size = sizeof(struct mtk_musb_glue),
  342. };