da8xx.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments da8xx "glue layer"
  4. *
  5. * Copyright (c) 2019, by Texas Instruments
  6. *
  7. * Based on the DA8xx "glue layer" code.
  8. * Copyright (c) 2008-2019, MontaVista Software, Inc. <source@mvista.com>
  9. *
  10. * DT support
  11. * Copyright (c) 2016 Petr Kulhavy <petr@barix.com>
  12. * This file is part of the Inventra Controller Driver for Linux.
  13. *
  14. */
  15. #include <common.h>
  16. #include <dm.h>
  17. #include <log.h>
  18. #include <dm/device-internal.h>
  19. #include <dm/device_compat.h>
  20. #include <dm/lists.h>
  21. #include <asm/arch/hardware.h>
  22. #include <asm/arch/da8xx-usb.h>
  23. #include <linux/delay.h>
  24. #include <linux/usb/otg.h>
  25. #include <asm/omap_musb.h>
  26. #include <generic-phy.h>
  27. #include "linux-compat.h"
  28. #include "musb_core.h"
  29. #include "musb_uboot.h"
  30. /* USB 2.0 OTG module registers */
  31. #define DA8XX_USB_REVISION_REG 0x00
  32. #define DA8XX_USB_CTRL_REG 0x04
  33. #define DA8XX_USB_STAT_REG 0x08
  34. #define DA8XX_USB_EMULATION_REG 0x0c
  35. #define DA8XX_USB_SRP_FIX_TIME_REG 0x18
  36. #define DA8XX_USB_INTR_SRC_REG 0x20
  37. #define DA8XX_USB_INTR_SRC_SET_REG 0x24
  38. #define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
  39. #define DA8XX_USB_INTR_MASK_REG 0x2c
  40. #define DA8XX_USB_INTR_MASK_SET_REG 0x30
  41. #define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
  42. #define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
  43. #define DA8XX_USB_END_OF_INTR_REG 0x3c
  44. #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
  45. /* Control register bits */
  46. #define DA8XX_SOFT_RESET_MASK 1
  47. #define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
  48. #define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
  49. /* USB interrupt register bits */
  50. #define DA8XX_INTR_USB_SHIFT 16
  51. #define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
  52. /* interrupts and DRVVBUS interrupt */
  53. #define DA8XX_INTR_DRVVBUS 0x100
  54. #define DA8XX_INTR_RX_SHIFT 8
  55. #define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
  56. #define DA8XX_INTR_TX_SHIFT 0
  57. #define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
  58. #define DA8XX_MENTOR_CORE_OFFSET 0x400
  59. static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
  60. {
  61. struct musb *musb = hci;
  62. void __iomem *reg_base = musb->ctrl_base;
  63. unsigned long flags;
  64. irqreturn_t ret = IRQ_NONE;
  65. u32 status;
  66. spin_lock_irqsave(&musb->lock, flags);
  67. /*
  68. * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
  69. * the Mentor registers (except for setup), use the TI ones and EOI.
  70. */
  71. /* Acknowledge and handle non-CPPI interrupts */
  72. status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
  73. if (!status)
  74. goto eoi;
  75. musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
  76. dev_dbg(musb->controller, "USB IRQ %08x\n", status);
  77. musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
  78. musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
  79. musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
  80. /*
  81. * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
  82. * DA8xx's missing ID change IRQ. We need an ID change IRQ to
  83. * switch appropriately between halves of the OTG state machine.
  84. * Managing DEVCTL.Session per Mentor docs requires that we know its
  85. * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
  86. * Also, DRVVBUS pulses for SRP (but not at 5 V)...
  87. */
  88. if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
  89. int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
  90. void __iomem *mregs = musb->mregs;
  91. u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
  92. int err;
  93. err = musb->int_usb & MUSB_INTR_VBUSERROR;
  94. if (err) {
  95. /*
  96. * The Mentor core doesn't debounce VBUS as needed
  97. * to cope with device connect current spikes. This
  98. * means it's not uncommon for bus-powered devices
  99. * to get VBUS errors during enumeration.
  100. *
  101. * This is a workaround, but newer RTL from Mentor
  102. * seems to allow a better one: "re"-starting sessions
  103. * without waiting for VBUS to stop registering in
  104. * devctl.
  105. */
  106. musb->int_usb &= ~MUSB_INTR_VBUSERROR;
  107. WARNING("VBUS error workaround (delay coming)\n");
  108. } else if (drvvbus) {
  109. MUSB_HST_MODE(musb);
  110. musb->port1_status |= USB_PORT_STAT_POWER;
  111. } else if (!(musb->int_usb & MUSB_INTR_BABBLE)) {
  112. /*
  113. * When babble condition happens, drvvbus interrupt
  114. * is also generated. Ignore this drvvbus interrupt
  115. * and let babble interrupt handler recovers the
  116. * controller; otherwise, the host-mode flag is lost
  117. * due to the MUSB_DEV_MODE() call below and babble
  118. * recovery logic will not be called.
  119. */
  120. musb->is_active = 0;
  121. MUSB_DEV_MODE(musb);
  122. musb->port1_status &= ~USB_PORT_STAT_POWER;
  123. }
  124. ret = IRQ_HANDLED;
  125. }
  126. if (musb->int_tx || musb->int_rx || musb->int_usb)
  127. ret |= musb_interrupt(musb);
  128. eoi:
  129. /* EOI needs to be written for the IRQ to be re-asserted. */
  130. if (ret == IRQ_HANDLED || status)
  131. musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
  132. spin_unlock_irqrestore(&musb->lock, flags);
  133. return ret;
  134. }
  135. static int da8xx_musb_init(struct musb *musb)
  136. {
  137. u32 revision;
  138. void __iomem *reg_base = musb->ctrl_base;
  139. int ret;
  140. /* reset the controller */
  141. writel(0x1, &da8xx_usb_regs->control);
  142. udelay(50);
  143. /* Returns zero if e.g. not clocked */
  144. revision = readl(&da8xx_usb_regs->revision);
  145. if (revision == 0)
  146. return -ENODEV;
  147. /* Disable all interrupts */
  148. writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
  149. DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_set);
  150. musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
  151. /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
  152. debug("DA8xx OTG revision %08x, control %02x\n", revision,
  153. musb_readb(reg_base, DA8XX_USB_CTRL_REG));
  154. musb->isr = da8xx_musb_interrupt;
  155. return 0;
  156. }
  157. static int da8xx_musb_exit(struct musb *musb)
  158. {
  159. /* flush any interrupts */
  160. writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
  161. DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr);
  162. writel(0, &da8xx_usb_regs->eoi);
  163. return 0;
  164. }
  165. /**
  166. * da8xx_musb_enable - enable interrupts
  167. */
  168. static int da8xx_musb_enable(struct musb *musb)
  169. {
  170. void __iomem *reg_base = musb->ctrl_base;
  171. u32 mask;
  172. /* Workaround: setup IRQs through both register sets. */
  173. mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
  174. ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
  175. DA8XX_INTR_USB_MASK;
  176. musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
  177. /* Force the DRVVBUS IRQ so we can start polling for ID change. */
  178. musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
  179. DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
  180. return 0;
  181. }
  182. /**
  183. * da8xx_musb_disable - disable HDRC and flush interrupts
  184. */
  185. static void da8xx_musb_disable(struct musb *musb)
  186. {
  187. void __iomem *reg_base = musb->ctrl_base;
  188. musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
  189. DA8XX_INTR_USB_MASK |
  190. DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
  191. musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
  192. }
  193. void da8xx_musb_reset(struct udevice *dev)
  194. {
  195. void *reg_base = dev_read_addr_ptr(dev);
  196. /* Reset the controller */
  197. musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
  198. }
  199. void da8xx_musb_clear_irq(struct udevice *dev)
  200. {
  201. /* flush any interrupts */
  202. writel((DA8XX_USB_USBINT_MASK | DA8XX_USB_TXINT_MASK |
  203. DA8XX_USB_RXINT_MASK), &da8xx_usb_regs->intmsk_clr);
  204. writel(0, &da8xx_usb_regs->eoi);
  205. }
  206. const struct musb_platform_ops da8xx_ops = {
  207. .init = da8xx_musb_init,
  208. .exit = da8xx_musb_exit,
  209. .enable = da8xx_musb_enable,
  210. .disable = da8xx_musb_disable,
  211. };
  212. struct da8xx_musb_platdata {
  213. void *base;
  214. void *ctrl_mod_base;
  215. struct musb_hdrc_platform_data plat;
  216. struct musb_hdrc_config musb_config;
  217. struct omap_musb_board_data otg_board_data;
  218. struct phy phy;
  219. };
  220. static int da8xx_musb_ofdata_to_platdata(struct udevice *dev)
  221. {
  222. struct da8xx_musb_platdata *platdata = dev_get_platdata(dev);
  223. const void *fdt = gd->fdt_blob;
  224. int node = dev_of_offset(dev);
  225. platdata->base = (void *)dev_read_addr_ptr(dev);
  226. platdata->musb_config.multipoint = 1;
  227. platdata->musb_config.dyn_fifo = 1;
  228. platdata->musb_config.num_eps = 5;
  229. platdata->musb_config.ram_bits = 10;
  230. platdata->plat.power = fdtdec_get_int(fdt, node, "power", 50);
  231. platdata->otg_board_data.interface_type = MUSB_INTERFACE_UTMI;
  232. platdata->plat.mode = MUSB_HOST;
  233. platdata->otg_board_data.dev = dev;
  234. platdata->plat.config = &platdata->musb_config;
  235. platdata->plat.platform_ops = &da8xx_ops;
  236. platdata->plat.board_data = &platdata->otg_board_data;
  237. platdata->otg_board_data.clear_irq = da8xx_musb_clear_irq;
  238. platdata->otg_board_data.reset = da8xx_musb_reset;
  239. return 0;
  240. }
  241. static int da8xx_musb_probe(struct udevice *dev)
  242. {
  243. struct musb_host_data *host = dev_get_priv(dev);
  244. struct da8xx_musb_platdata *platdata = dev_get_platdata(dev);
  245. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  246. struct omap_musb_board_data *otg_board_data;
  247. int ret;
  248. void *base = dev_read_addr_ptr(dev);
  249. /* Get the phy info from the device tree */
  250. ret = generic_phy_get_by_name(dev, "usb-phy", &platdata->phy);
  251. if (ret)
  252. return ret;
  253. /* Initialize the phy */
  254. ret = generic_phy_init(&platdata->phy);
  255. if (ret)
  256. return ret;
  257. /* enable psc for usb2.0 */
  258. lpsc_on(33);
  259. /* Enable phy */
  260. generic_phy_power_on(&platdata->phy);
  261. priv->desc_before_addr = true;
  262. otg_board_data = &platdata->otg_board_data;
  263. host->host = musb_init_controller(&platdata->plat,
  264. (struct device *)otg_board_data,
  265. platdata->base);
  266. if (!host->host) {
  267. ret = -ENODEV;
  268. goto shutdown; /* Shutdown what we started */
  269. }
  270. ret = musb_lowlevel_init(host);
  271. if (ret == 0)
  272. return 0;
  273. shutdown:
  274. /* Turn off the phy if we fail */
  275. generic_phy_power_off(&platdata->phy);
  276. lpsc_disable(33);
  277. return ret;
  278. }
  279. static int da8xx_musb_remove(struct udevice *dev)
  280. {
  281. struct musb_host_data *host = dev_get_priv(dev);
  282. musb_stop(host->host);
  283. return 0;
  284. }
  285. static const struct udevice_id da8xx_musb_ids[] = {
  286. { .compatible = "ti,da830-musb" },
  287. { }
  288. };
  289. U_BOOT_DRIVER(da8xx_musb) = {
  290. .name = "da8xx-musb",
  291. .id = UCLASS_USB,
  292. .of_match = da8xx_musb_ids,
  293. .ofdata_to_platdata = da8xx_musb_ofdata_to_platdata,
  294. .probe = da8xx_musb_probe,
  295. .remove = da8xx_musb_remove,
  296. .ops = &musb_usb_ops,
  297. .platdata_auto_alloc_size = sizeof(struct da8xx_musb_platdata),
  298. .priv_auto_alloc_size = sizeof(struct musb_host_data),
  299. };