am35x.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments AM35x "glue layer"
  4. *
  5. * Copyright (c) 2010, by Texas Instruments
  6. *
  7. * Based on the DA8xx "glue layer" code.
  8. * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
  9. *
  10. * This file is part of the Inventra Controller Driver for Linux.
  11. *
  12. */
  13. #ifndef __UBOOT__
  14. #include <dm/device_compat.h>
  15. #include <dm/devres.h>
  16. #include <linux/init.h>
  17. #include <linux/module.h>
  18. #include <linux/clk.h>
  19. #include <linux/err.h>
  20. #include <linux/io.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/dma-mapping.h>
  23. #include <plat/usb.h>
  24. #else
  25. #include <common.h>
  26. #include <asm/omap_musb.h>
  27. #include <linux/bug.h>
  28. #include <linux/delay.h>
  29. #include "linux-compat.h"
  30. #endif
  31. #include "musb_core.h"
  32. /*
  33. * AM35x specific definitions
  34. */
  35. /* USB 2.0 OTG module registers */
  36. #define USB_REVISION_REG 0x00
  37. #define USB_CTRL_REG 0x04
  38. #define USB_STAT_REG 0x08
  39. #define USB_EMULATION_REG 0x0c
  40. /* 0x10 Reserved */
  41. #define USB_AUTOREQ_REG 0x14
  42. #define USB_SRP_FIX_TIME_REG 0x18
  43. #define USB_TEARDOWN_REG 0x1c
  44. #define EP_INTR_SRC_REG 0x20
  45. #define EP_INTR_SRC_SET_REG 0x24
  46. #define EP_INTR_SRC_CLEAR_REG 0x28
  47. #define EP_INTR_MASK_REG 0x2c
  48. #define EP_INTR_MASK_SET_REG 0x30
  49. #define EP_INTR_MASK_CLEAR_REG 0x34
  50. #define EP_INTR_SRC_MASKED_REG 0x38
  51. #define CORE_INTR_SRC_REG 0x40
  52. #define CORE_INTR_SRC_SET_REG 0x44
  53. #define CORE_INTR_SRC_CLEAR_REG 0x48
  54. #define CORE_INTR_MASK_REG 0x4c
  55. #define CORE_INTR_MASK_SET_REG 0x50
  56. #define CORE_INTR_MASK_CLEAR_REG 0x54
  57. #define CORE_INTR_SRC_MASKED_REG 0x58
  58. /* 0x5c Reserved */
  59. #define USB_END_OF_INTR_REG 0x60
  60. /* Control register bits */
  61. #define AM35X_SOFT_RESET_MASK 1
  62. /* USB interrupt register bits */
  63. #define AM35X_INTR_USB_SHIFT 16
  64. #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
  65. #define AM35X_INTR_DRVVBUS 0x100
  66. #define AM35X_INTR_RX_SHIFT 16
  67. #define AM35X_INTR_TX_SHIFT 0
  68. #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
  69. #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
  70. #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
  71. #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
  72. #define USB_MENTOR_CORE_OFFSET 0x400
  73. struct am35x_glue {
  74. struct device *dev;
  75. struct platform_device *musb;
  76. struct clk *phy_clk;
  77. struct clk *clk;
  78. };
  79. #define glue_to_musb(g) platform_get_drvdata(g->musb)
  80. /*
  81. * am35x_musb_enable - enable interrupts
  82. */
  83. #ifndef __UBOOT__
  84. static void am35x_musb_enable(struct musb *musb)
  85. #else
  86. static int am35x_musb_enable(struct musb *musb)
  87. #endif
  88. {
  89. void __iomem *reg_base = musb->ctrl_base;
  90. u32 epmask;
  91. /* Workaround: setup IRQs through both register sets. */
  92. epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
  93. ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
  94. musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
  95. musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
  96. /* Force the DRVVBUS IRQ so we can start polling for ID change. */
  97. if (is_otg_enabled(musb))
  98. musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
  99. AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
  100. #ifdef __UBOOT__
  101. return 0;
  102. #endif
  103. }
  104. /*
  105. * am35x_musb_disable - disable HDRC and flush interrupts
  106. */
  107. static void am35x_musb_disable(struct musb *musb)
  108. {
  109. void __iomem *reg_base = musb->ctrl_base;
  110. musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
  111. musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
  112. AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
  113. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  114. musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
  115. }
  116. #ifndef __UBOOT__
  117. #define portstate(stmt) stmt
  118. static void am35x_musb_set_vbus(struct musb *musb, int is_on)
  119. {
  120. WARN_ON(is_on && is_peripheral_active(musb));
  121. }
  122. #define POLL_SECONDS 2
  123. static struct timer_list otg_workaround;
  124. static void otg_timer(unsigned long _musb)
  125. {
  126. struct musb *musb = (void *)_musb;
  127. void __iomem *mregs = musb->mregs;
  128. u8 devctl;
  129. unsigned long flags;
  130. /*
  131. * We poll because AM35x's won't expose several OTG-critical
  132. * status change events (from the transceiver) otherwise.
  133. */
  134. devctl = musb_readb(mregs, MUSB_DEVCTL);
  135. dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
  136. otg_state_string(musb->xceiv->state));
  137. spin_lock_irqsave(&musb->lock, flags);
  138. switch (musb->xceiv->state) {
  139. case OTG_STATE_A_WAIT_BCON:
  140. devctl &= ~MUSB_DEVCTL_SESSION;
  141. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  142. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  143. if (devctl & MUSB_DEVCTL_BDEVICE) {
  144. musb->xceiv->state = OTG_STATE_B_IDLE;
  145. MUSB_DEV_MODE(musb);
  146. } else {
  147. musb->xceiv->state = OTG_STATE_A_IDLE;
  148. MUSB_HST_MODE(musb);
  149. }
  150. break;
  151. case OTG_STATE_A_WAIT_VFALL:
  152. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  153. musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
  154. MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
  155. break;
  156. case OTG_STATE_B_IDLE:
  157. if (!is_peripheral_enabled(musb))
  158. break;
  159. devctl = musb_readb(mregs, MUSB_DEVCTL);
  160. if (devctl & MUSB_DEVCTL_BDEVICE)
  161. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  162. else
  163. musb->xceiv->state = OTG_STATE_A_IDLE;
  164. break;
  165. default:
  166. break;
  167. }
  168. spin_unlock_irqrestore(&musb->lock, flags);
  169. }
  170. static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
  171. {
  172. static unsigned long last_timer;
  173. if (!is_otg_enabled(musb))
  174. return;
  175. if (timeout == 0)
  176. timeout = jiffies + msecs_to_jiffies(3);
  177. /* Never idle if active, or when VBUS timeout is not set as host */
  178. if (musb->is_active || (musb->a_wait_bcon == 0 &&
  179. musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
  180. dev_dbg(musb->controller, "%s active, deleting timer\n",
  181. otg_state_string(musb->xceiv->state));
  182. del_timer(&otg_workaround);
  183. last_timer = jiffies;
  184. return;
  185. }
  186. if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
  187. dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
  188. return;
  189. }
  190. last_timer = timeout;
  191. dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
  192. otg_state_string(musb->xceiv->state),
  193. jiffies_to_msecs(timeout - jiffies));
  194. mod_timer(&otg_workaround, timeout);
  195. }
  196. #endif
  197. static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
  198. {
  199. struct musb *musb = hci;
  200. void __iomem *reg_base = musb->ctrl_base;
  201. #ifndef __UBOOT__
  202. struct device *dev = musb->controller;
  203. struct musb_hdrc_platform_data *plat = dev->platform_data;
  204. struct omap_musb_board_data *data = plat->board_data;
  205. struct usb_otg *otg = musb->xceiv->otg;
  206. #else
  207. struct omap_musb_board_data *data =
  208. (struct omap_musb_board_data *)musb->controller;
  209. #endif
  210. unsigned long flags;
  211. irqreturn_t ret = IRQ_NONE;
  212. u32 epintr, usbintr;
  213. #ifdef __UBOOT__
  214. /*
  215. * It seems that on AM35X interrupt registers can be updated
  216. * before core registers. This confuses the code.
  217. * As a workaround add a small delay here.
  218. */
  219. udelay(10);
  220. #endif
  221. spin_lock_irqsave(&musb->lock, flags);
  222. /* Get endpoint interrupts */
  223. epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
  224. if (epintr) {
  225. musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
  226. musb->int_rx =
  227. (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
  228. musb->int_tx =
  229. (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
  230. }
  231. /* Get usb core interrupts */
  232. usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
  233. if (!usbintr && !epintr)
  234. goto eoi;
  235. if (usbintr) {
  236. musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
  237. musb->int_usb =
  238. (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
  239. }
  240. #ifndef __UBOOT__
  241. /*
  242. * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
  243. * AM35x's missing ID change IRQ. We need an ID change IRQ to
  244. * switch appropriately between halves of the OTG state machine.
  245. * Managing DEVCTL.SESSION per Mentor docs requires that we know its
  246. * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
  247. * Also, DRVVBUS pulses for SRP (but not at 5V) ...
  248. */
  249. if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
  250. int drvvbus = musb_readl(reg_base, USB_STAT_REG);
  251. void __iomem *mregs = musb->mregs;
  252. u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
  253. int err;
  254. err = is_host_enabled(musb) && (musb->int_usb &
  255. MUSB_INTR_VBUSERROR);
  256. if (err) {
  257. /*
  258. * The Mentor core doesn't debounce VBUS as needed
  259. * to cope with device connect current spikes. This
  260. * means it's not uncommon for bus-powered devices
  261. * to get VBUS errors during enumeration.
  262. *
  263. * This is a workaround, but newer RTL from Mentor
  264. * seems to allow a better one: "re"-starting sessions
  265. * without waiting for VBUS to stop registering in
  266. * devctl.
  267. */
  268. musb->int_usb &= ~MUSB_INTR_VBUSERROR;
  269. musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
  270. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  271. WARNING("VBUS error workaround (delay coming)\n");
  272. } else if (is_host_enabled(musb) && drvvbus) {
  273. MUSB_HST_MODE(musb);
  274. otg->default_a = 1;
  275. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  276. portstate(musb->port1_status |= USB_PORT_STAT_POWER);
  277. del_timer(&otg_workaround);
  278. } else {
  279. musb->is_active = 0;
  280. MUSB_DEV_MODE(musb);
  281. otg->default_a = 0;
  282. musb->xceiv->state = OTG_STATE_B_IDLE;
  283. portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
  284. }
  285. /* NOTE: this must complete power-on within 100 ms. */
  286. dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
  287. drvvbus ? "on" : "off",
  288. otg_state_string(musb->xceiv->state),
  289. err ? " ERROR" : "",
  290. devctl);
  291. ret = IRQ_HANDLED;
  292. }
  293. #endif
  294. if (musb->int_tx || musb->int_rx || musb->int_usb)
  295. ret |= musb_interrupt(musb);
  296. eoi:
  297. /* EOI needs to be written for the IRQ to be re-asserted. */
  298. if (ret == IRQ_HANDLED || epintr || usbintr) {
  299. /* clear level interrupt */
  300. if (data->clear_irq)
  301. data->clear_irq(data->dev);
  302. /* write EOI */
  303. musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
  304. }
  305. #ifndef __UBOOT__
  306. /* Poll for ID change */
  307. if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
  308. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  309. #endif
  310. spin_unlock_irqrestore(&musb->lock, flags);
  311. return ret;
  312. }
  313. #ifndef __UBOOT__
  314. static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
  315. {
  316. struct device *dev = musb->controller;
  317. struct musb_hdrc_platform_data *plat = dev->platform_data;
  318. struct omap_musb_board_data *data = plat->board_data;
  319. int retval = 0;
  320. if (data->set_mode)
  321. data->set_mode(musb_mode);
  322. else
  323. retval = -EIO;
  324. return retval;
  325. }
  326. #endif
  327. static int am35x_musb_init(struct musb *musb)
  328. {
  329. #ifndef __UBOOT__
  330. struct device *dev = musb->controller;
  331. struct musb_hdrc_platform_data *plat = dev->platform_data;
  332. struct omap_musb_board_data *data = plat->board_data;
  333. #else
  334. struct omap_musb_board_data *data =
  335. (struct omap_musb_board_data *)musb->controller;
  336. #endif
  337. void __iomem *reg_base = musb->ctrl_base;
  338. u32 rev;
  339. musb->mregs += USB_MENTOR_CORE_OFFSET;
  340. /* Returns zero if e.g. not clocked */
  341. rev = musb_readl(reg_base, USB_REVISION_REG);
  342. if (!rev)
  343. return -ENODEV;
  344. #ifndef __UBOOT__
  345. usb_nop_xceiv_register();
  346. musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  347. if (IS_ERR_OR_NULL(musb->xceiv))
  348. return -ENODEV;
  349. if (is_host_enabled(musb))
  350. setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
  351. #endif
  352. /* Reset the musb */
  353. if (data->reset)
  354. data->reset(data->dev);
  355. /* Reset the controller */
  356. musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
  357. /* Start the on-chip PHY and its PLL. */
  358. if (data && data->set_phy_power)
  359. data->set_phy_power(data->dev, 1);
  360. msleep(5);
  361. musb->isr = am35x_musb_interrupt;
  362. /* clear level interrupt */
  363. if (data->clear_irq)
  364. data->clear_irq(data->dev);
  365. return 0;
  366. }
  367. static int am35x_musb_exit(struct musb *musb)
  368. {
  369. #ifndef __UBOOT__
  370. struct device *dev = musb->controller;
  371. struct musb_hdrc_platform_data *plat = dev->platform_data;
  372. struct omap_musb_board_data *data = plat->board_data;
  373. #else
  374. struct omap_musb_board_data *data =
  375. (struct omap_musb_board_data *)musb->controller;
  376. #endif
  377. #ifndef __UBOOT__
  378. if (is_host_enabled(musb))
  379. del_timer_sync(&otg_workaround);
  380. #endif
  381. /* Shutdown the on-chip PHY and its PLL. */
  382. if (data && data->set_phy_power)
  383. data->set_phy_power(data->dev, 0);
  384. #ifndef __UBOOT__
  385. usb_put_phy(musb->xceiv);
  386. usb_nop_xceiv_unregister();
  387. #endif
  388. return 0;
  389. }
  390. /* AM35x supports only 32bit read operation */
  391. void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  392. {
  393. void __iomem *fifo = hw_ep->fifo;
  394. u32 val;
  395. int i;
  396. /* Read for 32bit-aligned destination address */
  397. if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
  398. readsl(fifo, dst, len >> 2);
  399. dst += len & ~0x03;
  400. len &= 0x03;
  401. }
  402. /*
  403. * Now read the remaining 1 to 3 byte or complete length if
  404. * unaligned address.
  405. */
  406. if (len > 4) {
  407. for (i = 0; i < (len >> 2); i++) {
  408. *(u32 *) dst = musb_readl(fifo, 0);
  409. dst += 4;
  410. }
  411. len &= 0x03;
  412. }
  413. if (len > 0) {
  414. val = musb_readl(fifo, 0);
  415. memcpy(dst, &val, len);
  416. }
  417. }
  418. #ifndef __UBOOT__
  419. static const struct musb_platform_ops am35x_ops = {
  420. #else
  421. const struct musb_platform_ops am35x_ops = {
  422. #endif
  423. .init = am35x_musb_init,
  424. .exit = am35x_musb_exit,
  425. .enable = am35x_musb_enable,
  426. .disable = am35x_musb_disable,
  427. #ifndef __UBOOT__
  428. .set_mode = am35x_musb_set_mode,
  429. .try_idle = am35x_musb_try_idle,
  430. .set_vbus = am35x_musb_set_vbus,
  431. #endif
  432. };
  433. #ifndef __UBOOT__
  434. static u64 am35x_dmamask = DMA_BIT_MASK(32);
  435. static int __devinit am35x_probe(struct platform_device *pdev)
  436. {
  437. struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
  438. struct platform_device *musb;
  439. struct am35x_glue *glue;
  440. struct clk *phy_clk;
  441. struct clk *clk;
  442. int ret = -ENOMEM;
  443. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  444. if (!glue) {
  445. dev_err(&pdev->dev, "failed to allocate glue context\n");
  446. goto err0;
  447. }
  448. musb = platform_device_alloc("musb-hdrc", -1);
  449. if (!musb) {
  450. dev_err(&pdev->dev, "failed to allocate musb device\n");
  451. goto err1;
  452. }
  453. phy_clk = clk_get(&pdev->dev, "fck");
  454. if (IS_ERR(phy_clk)) {
  455. dev_err(&pdev->dev, "failed to get PHY clock\n");
  456. ret = PTR_ERR(phy_clk);
  457. goto err2;
  458. }
  459. clk = clk_get(&pdev->dev, "ick");
  460. if (IS_ERR(clk)) {
  461. dev_err(&pdev->dev, "failed to get clock\n");
  462. ret = PTR_ERR(clk);
  463. goto err3;
  464. }
  465. ret = clk_enable(phy_clk);
  466. if (ret) {
  467. dev_err(&pdev->dev, "failed to enable PHY clock\n");
  468. goto err4;
  469. }
  470. ret = clk_enable(clk);
  471. if (ret) {
  472. dev_err(&pdev->dev, "failed to enable clock\n");
  473. goto err5;
  474. }
  475. musb->dev.parent = &pdev->dev;
  476. musb->dev.dma_mask = &am35x_dmamask;
  477. musb->dev.coherent_dma_mask = am35x_dmamask;
  478. glue->dev = &pdev->dev;
  479. glue->musb = musb;
  480. glue->phy_clk = phy_clk;
  481. glue->clk = clk;
  482. pdata->platform_ops = &am35x_ops;
  483. platform_set_drvdata(pdev, glue);
  484. ret = platform_device_add_resources(musb, pdev->resource,
  485. pdev->num_resources);
  486. if (ret) {
  487. dev_err(&pdev->dev, "failed to add resources\n");
  488. goto err6;
  489. }
  490. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  491. if (ret) {
  492. dev_err(&pdev->dev, "failed to add platform_data\n");
  493. goto err6;
  494. }
  495. ret = platform_device_add(musb);
  496. if (ret) {
  497. dev_err(&pdev->dev, "failed to register musb device\n");
  498. goto err6;
  499. }
  500. return 0;
  501. err6:
  502. clk_disable(clk);
  503. err5:
  504. clk_disable(phy_clk);
  505. err4:
  506. clk_put(clk);
  507. err3:
  508. clk_put(phy_clk);
  509. err2:
  510. platform_device_put(musb);
  511. err1:
  512. kfree(glue);
  513. err0:
  514. return ret;
  515. }
  516. static int __devexit am35x_remove(struct platform_device *pdev)
  517. {
  518. struct am35x_glue *glue = platform_get_drvdata(pdev);
  519. platform_device_del(glue->musb);
  520. platform_device_put(glue->musb);
  521. clk_disable(glue->clk);
  522. clk_disable(glue->phy_clk);
  523. clk_put(glue->clk);
  524. clk_put(glue->phy_clk);
  525. kfree(glue);
  526. return 0;
  527. }
  528. #ifdef CONFIG_PM
  529. static int am35x_suspend(struct device *dev)
  530. {
  531. struct am35x_glue *glue = dev_get_drvdata(dev);
  532. struct musb_hdrc_platform_data *plat = dev->platform_data;
  533. struct omap_musb_board_data *data = plat->board_data;
  534. /* Shutdown the on-chip PHY and its PLL. */
  535. if (data && data->set_phy_power)
  536. data->set_phy_power(data->dev, 0);
  537. clk_disable(glue->phy_clk);
  538. clk_disable(glue->clk);
  539. return 0;
  540. }
  541. static int am35x_resume(struct device *dev)
  542. {
  543. struct am35x_glue *glue = dev_get_drvdata(dev);
  544. struct musb_hdrc_platform_data *plat = dev->platform_data;
  545. struct omap_musb_board_data *data = plat->board_data;
  546. int ret;
  547. /* Start the on-chip PHY and its PLL. */
  548. if (data && data->set_phy_power)
  549. data->set_phy_power(data->dev, 1);
  550. ret = clk_enable(glue->phy_clk);
  551. if (ret) {
  552. dev_err(dev, "failed to enable PHY clock\n");
  553. return ret;
  554. }
  555. ret = clk_enable(glue->clk);
  556. if (ret) {
  557. dev_err(dev, "failed to enable clock\n");
  558. return ret;
  559. }
  560. return 0;
  561. }
  562. static struct dev_pm_ops am35x_pm_ops = {
  563. .suspend = am35x_suspend,
  564. .resume = am35x_resume,
  565. };
  566. #define DEV_PM_OPS &am35x_pm_ops
  567. #else
  568. #define DEV_PM_OPS NULL
  569. #endif
  570. static struct platform_driver am35x_driver = {
  571. .probe = am35x_probe,
  572. .remove = __devexit_p(am35x_remove),
  573. .driver = {
  574. .name = "musb-am35x",
  575. .pm = DEV_PM_OPS,
  576. },
  577. };
  578. MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
  579. MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
  580. MODULE_LICENSE("GPL v2");
  581. static int __init am35x_init(void)
  582. {
  583. return platform_driver_register(&am35x_driver);
  584. }
  585. module_init(am35x_init);
  586. static void __exit am35x_exit(void)
  587. {
  588. platform_driver_unregister(&am35x_driver);
  589. }
  590. module_exit(am35x_exit);
  591. #endif