mtu3.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * mtu3.h - MediaTek USB3 DRD header
  4. *
  5. * Copyright (C) 2016 MediaTek Inc.
  6. *
  7. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  8. */
  9. #ifndef __MTU3_H__
  10. #define __MTU3_H__
  11. #include <asm/io.h>
  12. #include <clk.h>
  13. #include <dm.h>
  14. #include <dm/device_compat.h>
  15. #include <dm/devres.h>
  16. #include <generic-phy.h>
  17. #include <linux/bug.h>
  18. #include <linux/delay.h>
  19. #include <linux/usb/ch9.h>
  20. #include <linux/usb/gadget.h>
  21. #include <linux/usb/otg.h>
  22. #include <power/regulator.h>
  23. #include <usb/xhci.h>
  24. struct mtu3;
  25. struct mtu3_ep;
  26. struct mtu3_request;
  27. struct mtu3_host;
  28. #include "mtu3_hw_regs.h"
  29. #include "mtu3_qmu.h"
  30. #define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
  31. #define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
  32. #define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
  33. #define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
  34. #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
  35. #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
  36. #define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
  37. #define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
  38. #define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
  39. #define USB_QMU_TQCSR(epnum) (U3D_TXQCSR1 + (((epnum) - 1) * 0x10))
  40. #define USB_QMU_TQSAR(epnum) (U3D_TXQSAR1 + (((epnum) - 1) * 0x10))
  41. #define USB_QMU_TQCPR(epnum) (U3D_TXQCPR1 + (((epnum) - 1) * 0x10))
  42. #define SSUSB_U3_CTRL(p) (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08))
  43. #define SSUSB_U2_CTRL(p) (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08))
  44. #define MTU3_DRIVER_NAME "mtu3-gadget"
  45. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  46. #define MTU3_EP_ENABLED BIT(0)
  47. #define MTU3_EP_STALL BIT(1)
  48. #define MTU3_EP_WEDGE BIT(2)
  49. #define MTU3_EP_BUSY BIT(3)
  50. /* should be set as 1 */
  51. #define MTU3_U2_IP_SLOT_DEFAULT 1
  52. #define MTU3_U3_IP_SLOT_DEFAULT (MTU3_U2_IP_SLOT_DEFAULT)
  53. /**
  54. * IP TRUNK version
  55. * from 0x1003 version, USB3 Gen2 is supported, two changes affect driver:
  56. * 1. MAXPKT and MULTI bits layout of TXCSR1 and RXCSR1 are adjusted,
  57. * but not backward compatible
  58. * 2. QMU extend buffer length supported
  59. */
  60. #define MTU3_TRUNK_VERS_1003 0x1003
  61. /**
  62. * Normally the device works on HS or SS, to simplify fifo management,
  63. * devide fifo into some 2*maxp parts, use bitmap to manage it; And
  64. * 32 bits size of bitmap is large enough, that means it can manage
  65. * up to 32KB/64KB fifo size.
  66. * NOTE: MTU3_U2/3IP_EP_FIFO_UNIT should be power of two;
  67. * FIFO size is allocated according to @slot which is 1 by default
  68. */
  69. #define USB_HS_MAXP 512
  70. #define USB_SS_MAXP 1024
  71. #define MTU3_U2IP_EP_FIFO_UNIT \
  72. ((USB_HS_MAXP) * ((MTU3_U2_IP_SLOT_DEFAULT) + 1))
  73. #define MTU3_U3IP_EP_FIFO_UNIT \
  74. ((USB_SS_MAXP) * ((MTU3_U3_IP_SLOT_DEFAULT) + 1))
  75. #define MTU3_FIFO_BIT_SIZE 32
  76. #define MTU3_U2_IP_EP0_FIFO_SIZE 64
  77. /**
  78. * Maximum size of ep0 response buffer for ch9 requests,
  79. * the SET_SEL request uses 6 so far, and GET_STATUS is 2
  80. */
  81. #define EP0_RESPONSE_BUF 6
  82. /* device operated link and speed got from DEVICE_CONF register */
  83. enum mtu3_speed {
  84. MTU3_SPEED_INACTIVE = 0,
  85. MTU3_SPEED_FULL = 1,
  86. MTU3_SPEED_HIGH = 3,
  87. MTU3_SPEED_SUPER = 4,
  88. MTU3_SPEED_SUPER_PLUS = 5,
  89. };
  90. /**
  91. * @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP
  92. * without data stage.
  93. * @MU3D_EP0_STATE_TX: IN data stage
  94. * @MU3D_EP0_STATE_RX: OUT data stage
  95. * @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and
  96. * waits for its completion interrupt
  97. * @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared
  98. * after receives a SETUP.
  99. */
  100. enum mtu3_g_ep0_state {
  101. MU3D_EP0_STATE_SETUP = 1,
  102. MU3D_EP0_STATE_TX,
  103. MU3D_EP0_STATE_RX,
  104. MU3D_EP0_STATE_TX_END,
  105. MU3D_EP0_STATE_STALL,
  106. };
  107. /**
  108. * MTU3_DR_FORCE_NONE: automatically switch host and peripheral mode
  109. * by IDPIN signal.
  110. * MTU3_DR_FORCE_HOST: force to enter host mode and override OTG
  111. * IDPIN signal.
  112. * MTU3_DR_FORCE_DEVICE: force to enter peripheral mode.
  113. */
  114. enum mtu3_dr_force_mode {
  115. MTU3_DR_FORCE_NONE = 0,
  116. MTU3_DR_FORCE_HOST,
  117. MTU3_DR_FORCE_DEVICE,
  118. };
  119. /**
  120. * @mac_base: register base address of MAC, include xHCI and device
  121. * @ippc_base: register base address of IP Power and Clock interface (IPPC)
  122. * @vusb33_supply: usb3.3V shared by device/host IP
  123. * @vbus_supply: vbus 5v of OTG port
  124. * @clks: optional clocks, include "sys_ck", "ref_ck", "mcu_ck",
  125. * "dma_ck" and "xhci_ck"
  126. * @phys: phys used
  127. * @dr_mode: works in which mode:
  128. * host only, device only or dual-role mode
  129. */
  130. struct ssusb_mtk {
  131. struct udevice *dev;
  132. struct mtu3 *u3d;
  133. struct mtu3_host *u3h;
  134. void __iomem *mac_base;
  135. void __iomem *ippc_base;
  136. /* common power & clock */
  137. struct udevice *vusb33_supply;
  138. struct udevice *vbus_supply;
  139. struct clk_bulk clks;
  140. struct phy_bulk phys;
  141. /* otg */
  142. enum usb_dr_mode dr_mode;
  143. };
  144. /**
  145. * @ctrl: xHCI controller, needs to come first in this struct!
  146. * @hcd: xHCI's register base address
  147. * @u2_ports: number of usb2 host ports
  148. * @u3_ports: number of usb3 host ports
  149. * @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to
  150. * disable u3port0, bit1==1 to disable u3port1,... etc
  151. */
  152. struct mtu3_host {
  153. struct xhci_ctrl ctrl;
  154. struct xhci_hccr *hcd;
  155. void __iomem *ippc_base;
  156. struct ssusb_mtk *ssusb;
  157. struct udevice *dev;
  158. u32 u2_ports;
  159. u32 u3_ports;
  160. u32 u3p_dis_msk;
  161. };
  162. /**
  163. * @base: the base address of fifo
  164. * @limit: the bitmap size in bits
  165. * @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT
  166. */
  167. struct mtu3_fifo_info {
  168. u32 base;
  169. u32 limit;
  170. DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE);
  171. };
  172. /**
  173. * General Purpose Descriptor (GPD):
  174. * The format of TX GPD is a little different from RX one.
  175. * And the size of GPD is 16 bytes.
  176. *
  177. * @flag:
  178. * bit0: Hardware Own (HWO)
  179. * bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported
  180. * bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1
  181. * bit7: Interrupt On Completion (IOC)
  182. * @chksum: This is used to validate the contents of this GPD;
  183. * If TXQ_CS_EN / RXQ_CS_EN bit is set, an interrupt is issued
  184. * when checksum validation fails;
  185. * Checksum value is calculated over the 16 bytes of the GPD by default;
  186. * @data_buf_len (RX ONLY): This value indicates the length of
  187. * the assigned data buffer
  188. * @next_gpd: Physical address of the next GPD
  189. * @buffer: Physical address of the data buffer
  190. * @buf_len:
  191. * (TX): This value indicates the length of the assigned data buffer
  192. * (RX): The total length of data received
  193. * @ext_len: reserved
  194. * @ext_flag:
  195. * bit5 (TX ONLY): Zero Length Packet (ZLP),
  196. */
  197. struct qmu_gpd {
  198. __u8 flag;
  199. __u8 chksum;
  200. __le16 data_buf_len;
  201. __le32 next_gpd;
  202. __le32 buffer;
  203. __le16 buf_len;
  204. __u8 ext_len;
  205. __u8 ext_flag;
  206. } __packed;
  207. /**
  208. * dma: physical base address of GPD segment
  209. * start: virtual base address of GPD segment
  210. * end: the last GPD element
  211. * enqueue: the first empty GPD to use
  212. * dequeue: the first completed GPD serviced by ISR
  213. * NOTE: the size of GPD ring should be >= 2
  214. */
  215. struct mtu3_gpd_ring {
  216. dma_addr_t dma;
  217. struct qmu_gpd *start;
  218. struct qmu_gpd *end;
  219. struct qmu_gpd *enqueue;
  220. struct qmu_gpd *dequeue;
  221. };
  222. /**
  223. * @fifo_size: it is (@slot + 1) * @fifo_seg_size
  224. * @fifo_seg_size: it is roundup_pow_of_two(@maxp)
  225. */
  226. struct mtu3_ep {
  227. struct usb_ep ep;
  228. char name[12];
  229. struct mtu3 *mtu;
  230. u8 epnum;
  231. u8 type;
  232. u8 is_in;
  233. u16 maxp;
  234. int slot;
  235. u32 fifo_size;
  236. u32 fifo_addr;
  237. u32 fifo_seg_size;
  238. struct mtu3_fifo_info *fifo;
  239. struct list_head req_list;
  240. struct mtu3_gpd_ring gpd_ring;
  241. const struct usb_ss_ep_comp_descriptor *comp_desc;
  242. const struct usb_endpoint_descriptor *desc;
  243. int flags;
  244. };
  245. struct mtu3_request {
  246. struct usb_request request;
  247. struct list_head list;
  248. struct mtu3_ep *mep;
  249. struct mtu3 *mtu;
  250. struct qmu_gpd *gpd;
  251. int epnum;
  252. };
  253. static inline struct ssusb_mtk *dev_to_ssusb(struct udevice *dev)
  254. {
  255. return dev_get_priv(dev);
  256. }
  257. /**
  258. * struct mtu3 - device driver instance data.
  259. * @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only,
  260. * MTU3_U3_IP_SLOT_DEFAULT for U3 IP
  261. * @may_wakeup: means device's remote wakeup is enabled
  262. * @is_self_powered: is reported in device status and the config descriptor
  263. * @delayed_status: true when function drivers ask for delayed status
  264. * @gen2cp: compatible with USB3 Gen2 IP
  265. * @ep0_req: dummy request used while handling standard USB requests
  266. * for GET_STATUS and SET_SEL
  267. * @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests
  268. */
  269. struct mtu3 {
  270. spinlock_t lock;
  271. struct ssusb_mtk *ssusb;
  272. struct udevice *dev;
  273. void __iomem *mac_base;
  274. void __iomem *ippc_base;
  275. int irq;
  276. struct mtu3_fifo_info tx_fifo;
  277. struct mtu3_fifo_info rx_fifo;
  278. struct mtu3_ep *ep_array;
  279. struct mtu3_ep *in_eps;
  280. struct mtu3_ep *out_eps;
  281. struct mtu3_ep *ep0;
  282. int num_eps;
  283. int slot;
  284. int active_ep;
  285. enum mtu3_g_ep0_state ep0_state;
  286. struct usb_gadget g; /* the gadget */
  287. struct usb_gadget_driver *gadget_driver;
  288. struct mtu3_request ep0_req;
  289. u8 setup_buf[EP0_RESPONSE_BUF];
  290. enum usb_device_speed max_speed;
  291. enum usb_device_speed speed;
  292. unsigned is_active:1;
  293. unsigned may_wakeup:1;
  294. unsigned is_self_powered:1;
  295. unsigned test_mode:1;
  296. unsigned softconnect:1;
  297. unsigned u1_enable:1;
  298. unsigned u2_enable:1;
  299. unsigned is_u3_ip:1;
  300. unsigned delayed_status:1;
  301. unsigned gen2cp:1;
  302. unsigned force_vbus:1;
  303. u8 address;
  304. u8 test_mode_nr;
  305. u32 hw_version;
  306. };
  307. static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g)
  308. {
  309. return container_of(g, struct mtu3, g);
  310. }
  311. static inline int is_first_entry(const struct list_head *list,
  312. const struct list_head *head)
  313. {
  314. return list_is_last(head, list);
  315. }
  316. static inline struct mtu3_request *to_mtu3_request(struct usb_request *req)
  317. {
  318. return req ? container_of(req, struct mtu3_request, request) : NULL;
  319. }
  320. static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep)
  321. {
  322. return ep ? container_of(ep, struct mtu3_ep, ep) : NULL;
  323. }
  324. static inline struct mtu3_request *next_request(struct mtu3_ep *mep)
  325. {
  326. if (list_empty(&mep->req_list))
  327. return NULL;
  328. return list_first_entry(&mep->req_list, struct mtu3_request, list);
  329. }
  330. static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data)
  331. {
  332. writel(data, base + offset);
  333. }
  334. static inline u32 mtu3_readl(void __iomem *base, u32 offset)
  335. {
  336. return readl(base + offset);
  337. }
  338. static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits)
  339. {
  340. void __iomem *addr = base + offset;
  341. u32 tmp = readl(addr);
  342. writel((tmp | (bits)), addr);
  343. }
  344. static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits)
  345. {
  346. void __iomem *addr = base + offset;
  347. u32 tmp = readl(addr);
  348. writel((tmp & ~(bits)), addr);
  349. }
  350. int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks);
  351. struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags);
  352. void mtu3_free_request(struct usb_ep *ep, struct usb_request *req);
  353. void mtu3_req_complete(struct mtu3_ep *mep,
  354. struct usb_request *req, int status);
  355. int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
  356. int interval, int burst, int mult);
  357. void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep);
  358. void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set);
  359. void mtu3_ep0_setup(struct mtu3 *mtu);
  360. void mtu3_start(struct mtu3 *mtu);
  361. void mtu3_stop(struct mtu3 *mtu);
  362. void mtu3_dev_on_off(struct mtu3 *mtu, int is_on);
  363. void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed);
  364. int mtu3_gadget_setup(struct mtu3 *mtu);
  365. void mtu3_gadget_cleanup(struct mtu3 *mtu);
  366. void mtu3_gadget_reset(struct mtu3 *mtu);
  367. void mtu3_gadget_suspend(struct mtu3 *mtu);
  368. void mtu3_gadget_resume(struct mtu3 *mtu);
  369. void mtu3_gadget_disconnect(struct mtu3 *mtu);
  370. irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu);
  371. extern const struct usb_ep_ops mtu3_ep0_ops;
  372. #endif