pxa25x_udc.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
  4. *
  5. * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
  6. * Copyright (C) 2003 Robert Schwebel, Pengutronix
  7. * Copyright (C) 2003 Benedikt Spranger, Pengutronix
  8. * Copyright (C) 2003 David Brownell
  9. * Copyright (C) 2003 Joshua Wise
  10. * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
  11. *
  12. * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
  13. */
  14. #define CONFIG_USB_PXA25X_SMALL
  15. #define DRIVER_NAME "pxa25x_udc_linux"
  16. #define ARCH_HAS_PREFETCH
  17. #include <common.h>
  18. #include <errno.h>
  19. #include <log.h>
  20. #include <asm/byteorder.h>
  21. #include <asm/system.h>
  22. #include <asm/mach-types.h>
  23. #include <asm/unaligned.h>
  24. #include <dm/devres.h>
  25. #include <linux/bug.h>
  26. #include <linux/compat.h>
  27. #include <malloc.h>
  28. #include <asm/io.h>
  29. #include <asm/arch/pxa.h>
  30. #include <linux/delay.h>
  31. #include <linux/usb/ch9.h>
  32. #include <linux/usb/gadget.h>
  33. #include <asm/arch/pxa-regs.h>
  34. #include "pxa25x_udc.h"
  35. /*
  36. * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
  37. * series processors. The UDC for the IXP 4xx series is very similar.
  38. * There are fifteen endpoints, in addition to ep0.
  39. *
  40. * Such controller drivers work with a gadget driver. The gadget driver
  41. * returns descriptors, implements configuration and data protocols used
  42. * by the host to interact with this device, and allocates endpoints to
  43. * the different protocol interfaces. The controller driver virtualizes
  44. * usb hardware so that the gadget drivers will be more portable.
  45. *
  46. * This UDC hardware wants to implement a bit too much USB protocol, so
  47. * it constrains the sorts of USB configuration change events that work.
  48. * The errata for these chips are misleading; some "fixed" bugs from
  49. * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
  50. *
  51. * Note that the UDC hardware supports DMA (except on IXP) but that's
  52. * not used here. IN-DMA (to host) is simple enough, when the data is
  53. * suitably aligned (16 bytes) ... the network stack doesn't do that,
  54. * other software can. OUT-DMA is buggy in most chip versions, as well
  55. * as poorly designed (data toggle not automatic). So this driver won't
  56. * bother using DMA. (Mostly-working IN-DMA support was available in
  57. * kernels before 2.6.23, but was never enabled or well tested.)
  58. */
  59. #define DRIVER_VERSION "18-August-2012"
  60. #define DRIVER_DESC "PXA 25x USB Device Controller driver"
  61. static const char driver_name[] = "pxa25x_udc";
  62. static const char ep0name[] = "ep0";
  63. /* Watchdog */
  64. static inline void start_watchdog(struct pxa25x_udc *udc)
  65. {
  66. debug("Started watchdog\n");
  67. udc->watchdog.base = get_timer(0);
  68. udc->watchdog.running = 1;
  69. }
  70. static inline void stop_watchdog(struct pxa25x_udc *udc)
  71. {
  72. udc->watchdog.running = 0;
  73. debug("Stopped watchdog\n");
  74. }
  75. static inline void test_watchdog(struct pxa25x_udc *udc)
  76. {
  77. if (!udc->watchdog.running)
  78. return;
  79. debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base),
  80. udc->watchdog.period);
  81. if (get_timer(udc->watchdog.base) >= udc->watchdog.period) {
  82. stop_watchdog(udc);
  83. udc->watchdog.function(udc);
  84. }
  85. }
  86. static void udc_watchdog(struct pxa25x_udc *dev)
  87. {
  88. uint32_t udccs0 = readl(&dev->regs->udccs[0]);
  89. debug("Fired up udc_watchdog\n");
  90. local_irq_disable();
  91. if (dev->ep0state == EP0_STALL
  92. && (udccs0 & UDCCS0_FST) == 0
  93. && (udccs0 & UDCCS0_SST) == 0) {
  94. writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]);
  95. debug("ep0 re-stall\n");
  96. start_watchdog(dev);
  97. }
  98. local_irq_enable();
  99. }
  100. #ifdef DEBUG
  101. static const char * const state_name[] = {
  102. "EP0_IDLE",
  103. "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
  104. "EP0_END_XFER", "EP0_STALL"
  105. };
  106. static void
  107. dump_udccr(const char *label)
  108. {
  109. u32 udccr = readl(&UDC_REGS->udccr);
  110. debug("%s %02X =%s%s%s%s%s%s%s%s\n",
  111. label, udccr,
  112. (udccr & UDCCR_REM) ? " rem" : "",
  113. (udccr & UDCCR_RSTIR) ? " rstir" : "",
  114. (udccr & UDCCR_SRM) ? " srm" : "",
  115. (udccr & UDCCR_SUSIR) ? " susir" : "",
  116. (udccr & UDCCR_RESIR) ? " resir" : "",
  117. (udccr & UDCCR_RSM) ? " rsm" : "",
  118. (udccr & UDCCR_UDA) ? " uda" : "",
  119. (udccr & UDCCR_UDE) ? " ude" : "");
  120. }
  121. static void
  122. dump_udccs0(const char *label)
  123. {
  124. u32 udccs0 = readl(&UDC_REGS->udccs[0]);
  125. debug("%s %s %02X =%s%s%s%s%s%s%s%s\n",
  126. label, state_name[the_controller->ep0state], udccs0,
  127. (udccs0 & UDCCS0_SA) ? " sa" : "",
  128. (udccs0 & UDCCS0_RNE) ? " rne" : "",
  129. (udccs0 & UDCCS0_FST) ? " fst" : "",
  130. (udccs0 & UDCCS0_SST) ? " sst" : "",
  131. (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
  132. (udccs0 & UDCCS0_FTF) ? " ftf" : "",
  133. (udccs0 & UDCCS0_IPR) ? " ipr" : "",
  134. (udccs0 & UDCCS0_OPR) ? " opr" : "");
  135. }
  136. static void
  137. dump_state(struct pxa25x_udc *dev)
  138. {
  139. u32 tmp;
  140. unsigned i;
  141. debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
  142. state_name[dev->ep0state],
  143. readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0),
  144. readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0),
  145. readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl));
  146. dump_udccr("udccr");
  147. if (dev->has_cfr) {
  148. tmp = readl(&UDC_REGS->udccfr);
  149. debug("udccfr %02X =%s%s\n", tmp,
  150. (tmp & UDCCFR_AREN) ? " aren" : "",
  151. (tmp & UDCCFR_ACM) ? " acm" : "");
  152. }
  153. if (!dev->driver) {
  154. debug("no gadget driver bound\n");
  155. return;
  156. } else
  157. debug("ep0 driver '%s'\n", "ether");
  158. dump_udccs0("udccs0");
  159. debug("ep0 IN %lu/%lu, OUT %lu/%lu\n",
  160. dev->stats.write.bytes, dev->stats.write.ops,
  161. dev->stats.read.bytes, dev->stats.read.ops);
  162. for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
  163. if (dev->ep[i].desc == NULL)
  164. continue;
  165. debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs);
  166. }
  167. }
  168. #else /* DEBUG */
  169. static inline void dump_udccr(const char *label) { }
  170. static inline void dump_udccs0(const char *label) { }
  171. static inline void dump_state(struct pxa25x_udc *dev) { }
  172. #endif /* DEBUG */
  173. /*
  174. * ---------------------------------------------------------------------------
  175. * endpoint related parts of the api to the usb controller hardware,
  176. * used by gadget driver; and the inner talker-to-hardware core.
  177. * ---------------------------------------------------------------------------
  178. */
  179. static void pxa25x_ep_fifo_flush(struct usb_ep *ep);
  180. static void nuke(struct pxa25x_ep *, int status);
  181. /* one GPIO should control a D+ pullup, so host sees this device (or not) */
  182. static void pullup_off(void)
  183. {
  184. struct pxa2xx_udc_mach_info *mach = the_controller->mach;
  185. if (mach->udc_command)
  186. mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
  187. }
  188. static void pullup_on(void)
  189. {
  190. struct pxa2xx_udc_mach_info *mach = the_controller->mach;
  191. if (mach->udc_command)
  192. mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
  193. }
  194. static void pio_irq_enable(int bEndpointAddress)
  195. {
  196. bEndpointAddress &= 0xf;
  197. if (bEndpointAddress < 8) {
  198. clrbits_le32(&the_controller->regs->uicr0,
  199. 1 << bEndpointAddress);
  200. } else {
  201. bEndpointAddress -= 8;
  202. clrbits_le32(&the_controller->regs->uicr1,
  203. 1 << bEndpointAddress);
  204. }
  205. }
  206. static void pio_irq_disable(int bEndpointAddress)
  207. {
  208. bEndpointAddress &= 0xf;
  209. if (bEndpointAddress < 8) {
  210. setbits_le32(&the_controller->regs->uicr0,
  211. 1 << bEndpointAddress);
  212. } else {
  213. bEndpointAddress -= 8;
  214. setbits_le32(&the_controller->regs->uicr1,
  215. 1 << bEndpointAddress);
  216. }
  217. }
  218. static inline void udc_set_mask_UDCCR(int mask)
  219. {
  220. /*
  221. * The UDCCR reg contains mask and interrupt status bits,
  222. * so using '|=' isn't safe as it may ack an interrupt.
  223. */
  224. const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
  225. mask &= mask_bits;
  226. clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
  227. }
  228. static inline void udc_clear_mask_UDCCR(int mask)
  229. {
  230. const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
  231. mask = ~mask & mask_bits;
  232. clrbits_le32(&the_controller->regs->udccr, ~mask);
  233. }
  234. static inline void udc_ack_int_UDCCR(int mask)
  235. {
  236. const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
  237. mask &= ~mask_bits;
  238. clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
  239. }
  240. /*
  241. * endpoint enable/disable
  242. *
  243. * we need to verify the descriptors used to enable endpoints. since pxa25x
  244. * endpoint configurations are fixed, and are pretty much always enabled,
  245. * there's not a lot to manage here.
  246. *
  247. * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
  248. * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
  249. * for a single interface (with only the default altsetting) and for gadget
  250. * drivers that don't halt endpoints (not reset by set_interface). that also
  251. * means that if you use ISO, you must violate the USB spec rule that all
  252. * iso endpoints must be in non-default altsettings.
  253. */
  254. static int pxa25x_ep_enable(struct usb_ep *_ep,
  255. const struct usb_endpoint_descriptor *desc)
  256. {
  257. struct pxa25x_ep *ep;
  258. struct pxa25x_udc *dev;
  259. ep = container_of(_ep, struct pxa25x_ep, ep);
  260. if (!_ep || !desc || ep->desc || _ep->name == ep0name
  261. || desc->bDescriptorType != USB_DT_ENDPOINT
  262. || ep->bEndpointAddress != desc->bEndpointAddress
  263. || ep->fifo_size <
  264. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
  265. printf("%s, bad ep or descriptor\n", __func__);
  266. return -EINVAL;
  267. }
  268. /* xfer types must match, except that interrupt ~= bulk */
  269. if (ep->bmAttributes != desc->bmAttributes
  270. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  271. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  272. printf("%s, %s type mismatch\n", __func__, _ep->name);
  273. return -EINVAL;
  274. }
  275. /* hardware _could_ do smaller, but driver doesn't */
  276. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
  277. && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))
  278. != BULK_FIFO_SIZE)
  279. || !get_unaligned(&desc->wMaxPacketSize)) {
  280. printf("%s, bad %s maxpacket\n", __func__, _ep->name);
  281. return -ERANGE;
  282. }
  283. dev = ep->dev;
  284. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
  285. printf("%s, bogus device state\n", __func__);
  286. return -ESHUTDOWN;
  287. }
  288. ep->desc = desc;
  289. ep->stopped = 0;
  290. ep->pio_irqs = 0;
  291. ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
  292. /* flush fifo (mostly for OUT buffers) */
  293. pxa25x_ep_fifo_flush(_ep);
  294. /* ... reset halt state too, if we could ... */
  295. debug("enabled %s\n", _ep->name);
  296. return 0;
  297. }
  298. static int pxa25x_ep_disable(struct usb_ep *_ep)
  299. {
  300. struct pxa25x_ep *ep;
  301. unsigned long flags;
  302. ep = container_of(_ep, struct pxa25x_ep, ep);
  303. if (!_ep || !ep->desc) {
  304. printf("%s, %s not enabled\n", __func__,
  305. _ep ? ep->ep.name : NULL);
  306. return -EINVAL;
  307. }
  308. local_irq_save(flags);
  309. nuke(ep, -ESHUTDOWN);
  310. /* flush fifo (mostly for IN buffers) */
  311. pxa25x_ep_fifo_flush(_ep);
  312. ep->desc = NULL;
  313. ep->stopped = 1;
  314. local_irq_restore(flags);
  315. debug("%s disabled\n", _ep->name);
  316. return 0;
  317. }
  318. /*-------------------------------------------------------------------------*/
  319. /*
  320. * for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers
  321. * must still pass correctly initialized endpoints, since other controller
  322. * drivers may care about how it's currently set up (dma issues etc).
  323. */
  324. /*
  325. * pxa25x_ep_alloc_request - allocate a request data structure
  326. */
  327. static struct usb_request *
  328. pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  329. {
  330. struct pxa25x_request *req;
  331. req = kzalloc(sizeof(*req), gfp_flags);
  332. if (!req)
  333. return NULL;
  334. INIT_LIST_HEAD(&req->queue);
  335. return &req->req;
  336. }
  337. /*
  338. * pxa25x_ep_free_request - deallocate a request data structure
  339. */
  340. static void
  341. pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  342. {
  343. struct pxa25x_request *req;
  344. req = container_of(_req, struct pxa25x_request, req);
  345. WARN_ON(!list_empty(&req->queue));
  346. kfree(req);
  347. }
  348. /*-------------------------------------------------------------------------*/
  349. /*
  350. * done - retire a request; caller blocked irqs
  351. */
  352. static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
  353. {
  354. unsigned stopped = ep->stopped;
  355. list_del_init(&req->queue);
  356. if (likely(req->req.status == -EINPROGRESS))
  357. req->req.status = status;
  358. else
  359. status = req->req.status;
  360. if (status && status != -ESHUTDOWN)
  361. debug("complete %s req %p stat %d len %u/%u\n",
  362. ep->ep.name, &req->req, status,
  363. req->req.actual, req->req.length);
  364. /* don't modify queue heads during completion callback */
  365. ep->stopped = 1;
  366. req->req.complete(&ep->ep, &req->req);
  367. ep->stopped = stopped;
  368. }
  369. static inline void ep0_idle(struct pxa25x_udc *dev)
  370. {
  371. dev->ep0state = EP0_IDLE;
  372. }
  373. static int
  374. write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max)
  375. {
  376. u8 *buf;
  377. unsigned length, count;
  378. debug("%s(): uddr %p\n", __func__, uddr);
  379. buf = req->req.buf + req->req.actual;
  380. prefetch(buf);
  381. /* how big will this packet be? */
  382. length = min(req->req.length - req->req.actual, max);
  383. req->req.actual += length;
  384. count = length;
  385. while (likely(count--))
  386. writeb(*buf++, uddr);
  387. return length;
  388. }
  389. /*
  390. * write to an IN endpoint fifo, as many packets as possible.
  391. * irqs will use this to write the rest later.
  392. * caller guarantees at least one packet buffer is ready (or a zlp).
  393. */
  394. static int
  395. write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
  396. {
  397. unsigned max;
  398. max = le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize));
  399. do {
  400. unsigned count;
  401. int is_last, is_short;
  402. count = write_packet(ep->reg_uddr, req, max);
  403. /* last packet is usually short (or a zlp) */
  404. if (unlikely(count != max))
  405. is_last = is_short = 1;
  406. else {
  407. if (likely(req->req.length != req->req.actual)
  408. || req->req.zero)
  409. is_last = 0;
  410. else
  411. is_last = 1;
  412. /* interrupt/iso maxpacket may not fill the fifo */
  413. is_short = unlikely(max < ep->fifo_size);
  414. }
  415. debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n",
  416. ep->ep.name, count,
  417. is_last ? "/L" : "", is_short ? "/S" : "",
  418. req->req.length - req->req.actual, req);
  419. /*
  420. * let loose that packet. maybe try writing another one,
  421. * double buffering might work. TSP, TPC, and TFS
  422. * bit values are the same for all normal IN endpoints.
  423. */
  424. writel(UDCCS_BI_TPC, ep->reg_udccs);
  425. if (is_short)
  426. writel(UDCCS_BI_TSP, ep->reg_udccs);
  427. /* requests complete when all IN data is in the FIFO */
  428. if (is_last) {
  429. done(ep, req, 0);
  430. if (list_empty(&ep->queue))
  431. pio_irq_disable(ep->bEndpointAddress);
  432. return 1;
  433. }
  434. /*
  435. * TODO experiment: how robust can fifo mode tweaking be?
  436. * double buffering is off in the default fifo mode, which
  437. * prevents TFS from being set here.
  438. */
  439. } while (readl(ep->reg_udccs) & UDCCS_BI_TFS);
  440. return 0;
  441. }
  442. /*
  443. * caller asserts req->pending (ep0 irq status nyet cleared); starts
  444. * ep0 data stage. these chips want very simple state transitions.
  445. */
  446. static inline
  447. void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
  448. {
  449. writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]);
  450. writel(USIR0_IR0, &dev->regs->usir0);
  451. dev->req_pending = 0;
  452. debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n",
  453. __func__, tag, readl(&dev->regs->udccs[0]), flags,
  454. readl(&dev->regs->usir1), readl(&dev->regs->usir0));
  455. }
  456. static int
  457. write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
  458. {
  459. unsigned count;
  460. int is_short;
  461. count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE);
  462. ep->dev->stats.write.bytes += count;
  463. /* last packet "must be" short (or a zlp) */
  464. is_short = (count != EP0_FIFO_SIZE);
  465. debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count,
  466. req->req.length - req->req.actual, req);
  467. if (unlikely(is_short)) {
  468. if (ep->dev->req_pending)
  469. ep0start(ep->dev, UDCCS0_IPR, "short IN");
  470. else
  471. writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]);
  472. count = req->req.length;
  473. done(ep, req, 0);
  474. ep0_idle(ep->dev);
  475. /*
  476. * This seems to get rid of lost status irqs in some cases:
  477. * host responds quickly, or next request involves config
  478. * change automagic, or should have been hidden, or ...
  479. *
  480. * FIXME get rid of all udelays possible...
  481. */
  482. if (count >= EP0_FIFO_SIZE) {
  483. count = 100;
  484. do {
  485. if ((readl(&ep->dev->regs->udccs[0]) &
  486. UDCCS0_OPR) != 0) {
  487. /* clear OPR, generate ack */
  488. writel(UDCCS0_OPR,
  489. &ep->dev->regs->udccs[0]);
  490. break;
  491. }
  492. count--;
  493. udelay(1);
  494. } while (count);
  495. }
  496. } else if (ep->dev->req_pending)
  497. ep0start(ep->dev, 0, "IN");
  498. return is_short;
  499. }
  500. /*
  501. * read_fifo - unload packet(s) from the fifo we use for usb OUT
  502. * transfers and put them into the request. caller should have made
  503. * sure there's at least one packet ready.
  504. *
  505. * returns true if the request completed because of short packet or the
  506. * request buffer having filled (and maybe overran till end-of-packet).
  507. */
  508. static int
  509. read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
  510. {
  511. u32 udccs;
  512. u8 *buf;
  513. unsigned bufferspace, count, is_short;
  514. for (;;) {
  515. /*
  516. * make sure there's a packet in the FIFO.
  517. * UDCCS_{BO,IO}_RPC are all the same bit value.
  518. * UDCCS_{BO,IO}_RNE are all the same bit value.
  519. */
  520. udccs = readl(ep->reg_udccs);
  521. if (unlikely((udccs & UDCCS_BO_RPC) == 0))
  522. break;
  523. buf = req->req.buf + req->req.actual;
  524. prefetchw(buf);
  525. bufferspace = req->req.length - req->req.actual;
  526. /* read all bytes from this packet */
  527. if (likely(udccs & UDCCS_BO_RNE)) {
  528. count = 1 + (0x0ff & readl(ep->reg_ubcr));
  529. req->req.actual += min(count, bufferspace);
  530. } else /* zlp */
  531. count = 0;
  532. is_short = (count < ep->ep.maxpacket);
  533. debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
  534. ep->ep.name, udccs, count,
  535. is_short ? "/S" : "",
  536. req, req->req.actual, req->req.length);
  537. while (likely(count-- != 0)) {
  538. u8 byte = readb(ep->reg_uddr);
  539. if (unlikely(bufferspace == 0)) {
  540. /*
  541. * this happens when the driver's buffer
  542. * is smaller than what the host sent.
  543. * discard the extra data.
  544. */
  545. if (req->req.status != -EOVERFLOW)
  546. printf("%s overflow %d\n",
  547. ep->ep.name, count);
  548. req->req.status = -EOVERFLOW;
  549. } else {
  550. *buf++ = byte;
  551. bufferspace--;
  552. }
  553. }
  554. writel(UDCCS_BO_RPC, ep->reg_udccs);
  555. /* RPC/RSP/RNE could now reflect the other packet buffer */
  556. /* iso is one request per packet */
  557. if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
  558. if (udccs & UDCCS_IO_ROF)
  559. req->req.status = -EHOSTUNREACH;
  560. /* more like "is_done" */
  561. is_short = 1;
  562. }
  563. /* completion */
  564. if (is_short || req->req.actual == req->req.length) {
  565. done(ep, req, 0);
  566. if (list_empty(&ep->queue))
  567. pio_irq_disable(ep->bEndpointAddress);
  568. return 1;
  569. }
  570. /* finished that packet. the next one may be waiting... */
  571. }
  572. return 0;
  573. }
  574. /*
  575. * special ep0 version of the above. no UBCR0 or double buffering; status
  576. * handshaking is magic. most device protocols don't need control-OUT.
  577. * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
  578. * protocols do use them.
  579. */
  580. static int
  581. read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
  582. {
  583. u8 *buf, byte;
  584. unsigned bufferspace;
  585. buf = req->req.buf + req->req.actual;
  586. bufferspace = req->req.length - req->req.actual;
  587. while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) {
  588. byte = (u8)readb(&ep->dev->regs->uddr0);
  589. if (unlikely(bufferspace == 0)) {
  590. /*
  591. * this happens when the driver's buffer
  592. * is smaller than what the host sent.
  593. * discard the extra data.
  594. */
  595. if (req->req.status != -EOVERFLOW)
  596. printf("%s overflow\n", ep->ep.name);
  597. req->req.status = -EOVERFLOW;
  598. } else {
  599. *buf++ = byte;
  600. req->req.actual++;
  601. bufferspace--;
  602. }
  603. }
  604. writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]);
  605. /* completion */
  606. if (req->req.actual >= req->req.length)
  607. return 1;
  608. /* finished that packet. the next one may be waiting... */
  609. return 0;
  610. }
  611. /*-------------------------------------------------------------------------*/
  612. static int
  613. pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  614. {
  615. struct pxa25x_request *req;
  616. struct pxa25x_ep *ep;
  617. struct pxa25x_udc *dev;
  618. unsigned long flags;
  619. req = container_of(_req, struct pxa25x_request, req);
  620. if (unlikely(!_req || !_req->complete || !_req->buf
  621. || !list_empty(&req->queue))) {
  622. printf("%s, bad params\n", __func__);
  623. return -EINVAL;
  624. }
  625. ep = container_of(_ep, struct pxa25x_ep, ep);
  626. if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  627. printf("%s, bad ep\n", __func__);
  628. return -EINVAL;
  629. }
  630. dev = ep->dev;
  631. if (unlikely(!dev->driver
  632. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  633. printf("%s, bogus device state\n", __func__);
  634. return -ESHUTDOWN;
  635. }
  636. /*
  637. * iso is always one packet per request, that's the only way
  638. * we can report per-packet status. that also helps with dma.
  639. */
  640. if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
  641. && req->req.length >
  642. le16_to_cpu(get_unaligned(&ep->desc->wMaxPacketSize))))
  643. return -EMSGSIZE;
  644. debug_cond(NOISY, "%s queue req %p, len %d buf %p\n",
  645. _ep->name, _req, _req->length, _req->buf);
  646. local_irq_save(flags);
  647. _req->status = -EINPROGRESS;
  648. _req->actual = 0;
  649. /* kickstart this i/o queue? */
  650. if (list_empty(&ep->queue) && !ep->stopped) {
  651. if (ep->desc == NULL/* ep0 */) {
  652. unsigned length = _req->length;
  653. switch (dev->ep0state) {
  654. case EP0_IN_DATA_PHASE:
  655. dev->stats.write.ops++;
  656. if (write_ep0_fifo(ep, req))
  657. req = NULL;
  658. break;
  659. case EP0_OUT_DATA_PHASE:
  660. dev->stats.read.ops++;
  661. /* messy ... */
  662. if (dev->req_config) {
  663. debug("ep0 config ack%s\n",
  664. dev->has_cfr ? "" : " raced");
  665. if (dev->has_cfr)
  666. writel(UDCCFR_AREN|UDCCFR_ACM
  667. |UDCCFR_MB1,
  668. &ep->dev->regs->udccfr);
  669. done(ep, req, 0);
  670. dev->ep0state = EP0_END_XFER;
  671. local_irq_restore(flags);
  672. return 0;
  673. }
  674. if (dev->req_pending)
  675. ep0start(dev, UDCCS0_IPR, "OUT");
  676. if (length == 0 ||
  677. ((readl(
  678. &ep->dev->regs->udccs[0])
  679. & UDCCS0_RNE) != 0
  680. && read_ep0_fifo(ep, req))) {
  681. ep0_idle(dev);
  682. done(ep, req, 0);
  683. req = NULL;
  684. }
  685. break;
  686. default:
  687. printf("ep0 i/o, odd state %d\n",
  688. dev->ep0state);
  689. local_irq_restore(flags);
  690. return -EL2HLT;
  691. }
  692. /* can the FIFO can satisfy the request immediately? */
  693. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  694. if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0
  695. && write_fifo(ep, req))
  696. req = NULL;
  697. } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0
  698. && read_fifo(ep, req)) {
  699. req = NULL;
  700. }
  701. if (likely(req && ep->desc))
  702. pio_irq_enable(ep->bEndpointAddress);
  703. }
  704. /* pio or dma irq handler advances the queue. */
  705. if (likely(req != NULL))
  706. list_add_tail(&req->queue, &ep->queue);
  707. local_irq_restore(flags);
  708. return 0;
  709. }
  710. /*
  711. * nuke - dequeue ALL requests
  712. */
  713. static void nuke(struct pxa25x_ep *ep, int status)
  714. {
  715. struct pxa25x_request *req;
  716. /* called with irqs blocked */
  717. while (!list_empty(&ep->queue)) {
  718. req = list_entry(ep->queue.next,
  719. struct pxa25x_request,
  720. queue);
  721. done(ep, req, status);
  722. }
  723. if (ep->desc)
  724. pio_irq_disable(ep->bEndpointAddress);
  725. }
  726. /* dequeue JUST ONE request */
  727. static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  728. {
  729. struct pxa25x_ep *ep;
  730. struct pxa25x_request *req;
  731. unsigned long flags;
  732. ep = container_of(_ep, struct pxa25x_ep, ep);
  733. if (!_ep || ep->ep.name == ep0name)
  734. return -EINVAL;
  735. local_irq_save(flags);
  736. /* make sure it's actually queued on this endpoint */
  737. list_for_each_entry(req, &ep->queue, queue) {
  738. if (&req->req == _req)
  739. break;
  740. }
  741. if (&req->req != _req) {
  742. local_irq_restore(flags);
  743. return -EINVAL;
  744. }
  745. done(ep, req, -ECONNRESET);
  746. local_irq_restore(flags);
  747. return 0;
  748. }
  749. /*-------------------------------------------------------------------------*/
  750. static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
  751. {
  752. struct pxa25x_ep *ep;
  753. unsigned long flags;
  754. ep = container_of(_ep, struct pxa25x_ep, ep);
  755. if (unlikely(!_ep
  756. || (!ep->desc && ep->ep.name != ep0name))
  757. || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
  758. printf("%s, bad ep\n", __func__);
  759. return -EINVAL;
  760. }
  761. if (value == 0) {
  762. /*
  763. * this path (reset toggle+halt) is needed to implement
  764. * SET_INTERFACE on normal hardware. but it can't be
  765. * done from software on the PXA UDC, and the hardware
  766. * forgets to do it as part of SET_INTERFACE automagic.
  767. */
  768. printf("only host can clear %s halt\n", _ep->name);
  769. return -EROFS;
  770. }
  771. local_irq_save(flags);
  772. if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  773. && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0
  774. || !list_empty(&ep->queue))) {
  775. local_irq_restore(flags);
  776. return -EAGAIN;
  777. }
  778. /* FST bit is the same for control, bulk in, bulk out, interrupt in */
  779. writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs);
  780. /* ep0 needs special care */
  781. if (!ep->desc) {
  782. start_watchdog(ep->dev);
  783. ep->dev->req_pending = 0;
  784. ep->dev->ep0state = EP0_STALL;
  785. /* and bulk/intr endpoints like dropping stalls too */
  786. } else {
  787. unsigned i;
  788. for (i = 0; i < 1000; i += 20) {
  789. if (readl(ep->reg_udccs) & UDCCS_BI_SST)
  790. break;
  791. udelay(20);
  792. }
  793. }
  794. local_irq_restore(flags);
  795. debug("%s halt\n", _ep->name);
  796. return 0;
  797. }
  798. static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
  799. {
  800. struct pxa25x_ep *ep;
  801. ep = container_of(_ep, struct pxa25x_ep, ep);
  802. if (!_ep) {
  803. printf("%s, bad ep\n", __func__);
  804. return -ENODEV;
  805. }
  806. /* pxa can't report unclaimed bytes from IN fifos */
  807. if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
  808. return -EOPNOTSUPP;
  809. if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
  810. || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0)
  811. return 0;
  812. else
  813. return (readl(ep->reg_ubcr) & 0xfff) + 1;
  814. }
  815. static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
  816. {
  817. struct pxa25x_ep *ep;
  818. ep = container_of(_ep, struct pxa25x_ep, ep);
  819. if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
  820. printf("%s, bad ep\n", __func__);
  821. return;
  822. }
  823. /* toggle and halt bits stay unchanged */
  824. /* for OUT, just read and discard the FIFO contents. */
  825. if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
  826. while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0)
  827. (void)readb(ep->reg_uddr);
  828. return;
  829. }
  830. /* most IN status is the same, but ISO can't stall */
  831. writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
  832. | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
  833. ? 0 : UDCCS_BI_SST), ep->reg_udccs);
  834. }
  835. static struct usb_ep_ops pxa25x_ep_ops = {
  836. .enable = pxa25x_ep_enable,
  837. .disable = pxa25x_ep_disable,
  838. .alloc_request = pxa25x_ep_alloc_request,
  839. .free_request = pxa25x_ep_free_request,
  840. .queue = pxa25x_ep_queue,
  841. .dequeue = pxa25x_ep_dequeue,
  842. .set_halt = pxa25x_ep_set_halt,
  843. .fifo_status = pxa25x_ep_fifo_status,
  844. .fifo_flush = pxa25x_ep_fifo_flush,
  845. };
  846. /* ---------------------------------------------------------------------------
  847. * device-scoped parts of the api to the usb controller hardware
  848. * ---------------------------------------------------------------------------
  849. */
  850. static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
  851. {
  852. return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) |
  853. (readl(&the_controller->regs->ufnrl) & 0xff);
  854. }
  855. static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
  856. {
  857. /* host may not have enabled remote wakeup */
  858. if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0)
  859. return -EHOSTUNREACH;
  860. udc_set_mask_UDCCR(UDCCR_RSM);
  861. return 0;
  862. }
  863. static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
  864. static void udc_enable(struct pxa25x_udc *);
  865. static void udc_disable(struct pxa25x_udc *);
  866. /*
  867. * We disable the UDC -- and its 48 MHz clock -- whenever it's not
  868. * in active use.
  869. */
  870. static int pullup(struct pxa25x_udc *udc)
  871. {
  872. if (udc->pullup)
  873. pullup_on();
  874. else
  875. pullup_off();
  876. int is_active = udc->pullup;
  877. if (is_active) {
  878. if (!udc->active) {
  879. udc->active = 1;
  880. udc_enable(udc);
  881. }
  882. } else {
  883. if (udc->active) {
  884. if (udc->gadget.speed != USB_SPEED_UNKNOWN)
  885. stop_activity(udc, udc->driver);
  886. udc_disable(udc);
  887. udc->active = 0;
  888. }
  889. }
  890. return 0;
  891. }
  892. /* VBUS reporting logically comes from a transceiver */
  893. static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
  894. {
  895. struct pxa25x_udc *udc;
  896. udc = container_of(_gadget, struct pxa25x_udc, gadget);
  897. printf("vbus %s\n", is_active ? "supplied" : "inactive");
  898. pullup(udc);
  899. return 0;
  900. }
  901. /* drivers may have software control over D+ pullup */
  902. static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
  903. {
  904. struct pxa25x_udc *udc;
  905. udc = container_of(_gadget, struct pxa25x_udc, gadget);
  906. /* not all boards support pullup control */
  907. if (!udc->mach->udc_command)
  908. return -EOPNOTSUPP;
  909. udc->pullup = (is_active != 0);
  910. pullup(udc);
  911. return 0;
  912. }
  913. /*
  914. * boards may consume current from VBUS, up to 100-500mA based on config.
  915. * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
  916. * violate USB specs.
  917. */
  918. static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  919. {
  920. return -EOPNOTSUPP;
  921. }
  922. static const struct usb_gadget_ops pxa25x_udc_ops = {
  923. .get_frame = pxa25x_udc_get_frame,
  924. .wakeup = pxa25x_udc_wakeup,
  925. .vbus_session = pxa25x_udc_vbus_session,
  926. .pullup = pxa25x_udc_pullup,
  927. .vbus_draw = pxa25x_udc_vbus_draw,
  928. };
  929. /*-------------------------------------------------------------------------*/
  930. /*
  931. * udc_disable - disable USB device controller
  932. */
  933. static void udc_disable(struct pxa25x_udc *dev)
  934. {
  935. /* block all irqs */
  936. udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
  937. writel(0xff, &dev->regs->uicr0);
  938. writel(0xff, &dev->regs->uicr1);
  939. writel(UFNRH_SIM, &dev->regs->ufnrh);
  940. /* if hardware supports it, disconnect from usb */
  941. pullup_off();
  942. udc_clear_mask_UDCCR(UDCCR_UDE);
  943. ep0_idle(dev);
  944. dev->gadget.speed = USB_SPEED_UNKNOWN;
  945. }
  946. /*
  947. * udc_reinit - initialize software state
  948. */
  949. static void udc_reinit(struct pxa25x_udc *dev)
  950. {
  951. u32 i;
  952. /* device/ep0 records init */
  953. INIT_LIST_HEAD(&dev->gadget.ep_list);
  954. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  955. dev->ep0state = EP0_IDLE;
  956. /* basic endpoint records init */
  957. for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
  958. struct pxa25x_ep *ep = &dev->ep[i];
  959. if (i != 0)
  960. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  961. ep->desc = NULL;
  962. ep->stopped = 0;
  963. INIT_LIST_HEAD(&ep->queue);
  964. ep->pio_irqs = 0;
  965. }
  966. /* the rest was statically initialized, and is read-only */
  967. }
  968. /*
  969. * until it's enabled, this UDC should be completely invisible
  970. * to any USB host.
  971. */
  972. static void udc_enable(struct pxa25x_udc *dev)
  973. {
  974. debug("udc: enabling udc\n");
  975. udc_clear_mask_UDCCR(UDCCR_UDE);
  976. /*
  977. * Try to clear these bits before we enable the udc.
  978. * Do not touch reset ack bit, we would take care of it in
  979. * interrupt handle routine
  980. */
  981. udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR);
  982. ep0_idle(dev);
  983. dev->gadget.speed = USB_SPEED_UNKNOWN;
  984. dev->stats.irqs = 0;
  985. /*
  986. * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
  987. * - enable UDC
  988. * - if RESET is already in progress, ack interrupt
  989. * - unmask reset interrupt
  990. */
  991. udc_set_mask_UDCCR(UDCCR_UDE);
  992. if (!(readl(&dev->regs->udccr) & UDCCR_UDA))
  993. udc_ack_int_UDCCR(UDCCR_RSTIR);
  994. if (dev->has_cfr /* UDC_RES2 is defined */) {
  995. /*
  996. * pxa255 (a0+) can avoid a set_config race that could
  997. * prevent gadget drivers from configuring correctly
  998. */
  999. writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr);
  1000. }
  1001. /* enable suspend/resume and reset irqs */
  1002. udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
  1003. /* enable ep0 irqs */
  1004. clrbits_le32(&dev->regs->uicr0, UICR0_IM0);
  1005. /* if hardware supports it, pullup D+ and wait for reset */
  1006. pullup_on();
  1007. }
  1008. static inline void clear_ep_state(struct pxa25x_udc *dev)
  1009. {
  1010. unsigned i;
  1011. /*
  1012. * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
  1013. * fifos, and pending transactions mustn't be continued in any case.
  1014. */
  1015. for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
  1016. nuke(&dev->ep[i], -ECONNABORTED);
  1017. }
  1018. static void handle_ep0(struct pxa25x_udc *dev)
  1019. {
  1020. u32 udccs0 = readl(&dev->regs->udccs[0]);
  1021. struct pxa25x_ep *ep = &dev->ep[0];
  1022. struct pxa25x_request *req;
  1023. union {
  1024. struct usb_ctrlrequest r;
  1025. u8 raw[8];
  1026. u32 word[2];
  1027. } u;
  1028. if (list_empty(&ep->queue))
  1029. req = NULL;
  1030. else
  1031. req = list_entry(ep->queue.next, struct pxa25x_request, queue);
  1032. /* clear stall status */
  1033. if (udccs0 & UDCCS0_SST) {
  1034. nuke(ep, -EPIPE);
  1035. writel(UDCCS0_SST, &dev->regs->udccs[0]);
  1036. stop_watchdog(dev);
  1037. ep0_idle(dev);
  1038. }
  1039. /* previous request unfinished? non-error iff back-to-back ... */
  1040. if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
  1041. nuke(ep, 0);
  1042. stop_watchdog(dev);
  1043. ep0_idle(dev);
  1044. }
  1045. switch (dev->ep0state) {
  1046. case EP0_IDLE:
  1047. /* late-breaking status? */
  1048. udccs0 = readl(&dev->regs->udccs[0]);
  1049. /* start control request? */
  1050. if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
  1051. == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
  1052. int i;
  1053. nuke(ep, -EPROTO);
  1054. /* read SETUP packet */
  1055. for (i = 0; i < 8; i++) {
  1056. if (unlikely(!(readl(&dev->regs->udccs[0]) &
  1057. UDCCS0_RNE))) {
  1058. bad_setup:
  1059. debug("SETUP %d!\n", i);
  1060. goto stall;
  1061. }
  1062. u.raw[i] = (u8)readb(&dev->regs->uddr0);
  1063. }
  1064. if (unlikely((readl(&dev->regs->udccs[0]) &
  1065. UDCCS0_RNE) != 0))
  1066. goto bad_setup;
  1067. got_setup:
  1068. debug("SETUP %02x.%02x v%04x i%04x l%04x\n",
  1069. u.r.bRequestType, u.r.bRequest,
  1070. le16_to_cpu(u.r.wValue),
  1071. le16_to_cpu(u.r.wIndex),
  1072. le16_to_cpu(u.r.wLength));
  1073. /* cope with automagic for some standard requests. */
  1074. dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
  1075. == USB_TYPE_STANDARD;
  1076. dev->req_config = 0;
  1077. dev->req_pending = 1;
  1078. switch (u.r.bRequest) {
  1079. /* hardware restricts gadget drivers here! */
  1080. case USB_REQ_SET_CONFIGURATION:
  1081. debug("GOT SET_CONFIGURATION\n");
  1082. if (u.r.bRequestType == USB_RECIP_DEVICE) {
  1083. /*
  1084. * reflect hardware's automagic
  1085. * up to the gadget driver.
  1086. */
  1087. config_change:
  1088. dev->req_config = 1;
  1089. clear_ep_state(dev);
  1090. /*
  1091. * if !has_cfr, there's no synch
  1092. * else use AREN (later) not SA|OPR
  1093. * USIR0_IR0 acts edge sensitive
  1094. */
  1095. }
  1096. break;
  1097. /* ... and here, even more ... */
  1098. case USB_REQ_SET_INTERFACE:
  1099. if (u.r.bRequestType == USB_RECIP_INTERFACE) {
  1100. /*
  1101. * udc hardware is broken by design:
  1102. * - altsetting may only be zero;
  1103. * - hw resets all interfaces' eps;
  1104. * - ep reset doesn't include halt(?).
  1105. */
  1106. printf("broken set_interface (%d/%d)\n",
  1107. le16_to_cpu(u.r.wIndex),
  1108. le16_to_cpu(u.r.wValue));
  1109. goto config_change;
  1110. }
  1111. break;
  1112. /* hardware was supposed to hide this */
  1113. case USB_REQ_SET_ADDRESS:
  1114. debug("GOT SET ADDRESS\n");
  1115. if (u.r.bRequestType == USB_RECIP_DEVICE) {
  1116. ep0start(dev, 0, "address");
  1117. return;
  1118. }
  1119. break;
  1120. }
  1121. if (u.r.bRequestType & USB_DIR_IN)
  1122. dev->ep0state = EP0_IN_DATA_PHASE;
  1123. else
  1124. dev->ep0state = EP0_OUT_DATA_PHASE;
  1125. i = dev->driver->setup(&dev->gadget, &u.r);
  1126. if (i < 0) {
  1127. /* hardware automagic preventing STALL... */
  1128. if (dev->req_config) {
  1129. /*
  1130. * hardware sometimes neglects to tell
  1131. * tell us about config change events,
  1132. * so later ones may fail...
  1133. */
  1134. printf("config change %02x fail %d?\n",
  1135. u.r.bRequest, i);
  1136. return;
  1137. /*
  1138. * TODO experiment: if has_cfr,
  1139. * hardware didn't ACK; maybe we
  1140. * could actually STALL!
  1141. */
  1142. }
  1143. if (0) {
  1144. stall:
  1145. /* uninitialized when goto stall */
  1146. i = 0;
  1147. }
  1148. debug("protocol STALL, "
  1149. "%02x err %d\n",
  1150. readl(&dev->regs->udccs[0]), i);
  1151. /*
  1152. * the watchdog timer helps deal with cases
  1153. * where udc seems to clear FST wrongly, and
  1154. * then NAKs instead of STALLing.
  1155. */
  1156. ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
  1157. start_watchdog(dev);
  1158. dev->ep0state = EP0_STALL;
  1159. /* deferred i/o == no response yet */
  1160. } else if (dev->req_pending) {
  1161. if (likely(dev->ep0state == EP0_IN_DATA_PHASE
  1162. || dev->req_std || u.r.wLength))
  1163. ep0start(dev, 0, "defer");
  1164. else
  1165. ep0start(dev, UDCCS0_IPR, "defer/IPR");
  1166. }
  1167. /* expect at least one data or status stage irq */
  1168. return;
  1169. } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
  1170. == (UDCCS0_OPR|UDCCS0_SA))) {
  1171. unsigned i;
  1172. /*
  1173. * pxa210/250 erratum 131 for B0/B1 says RNE lies.
  1174. * still observed on a pxa255 a0.
  1175. */
  1176. debug("e131\n");
  1177. nuke(ep, -EPROTO);
  1178. /* read SETUP data, but don't trust it too much */
  1179. for (i = 0; i < 8; i++)
  1180. u.raw[i] = (u8)readb(&dev->regs->uddr0);
  1181. if ((u.r.bRequestType & USB_RECIP_MASK)
  1182. > USB_RECIP_OTHER)
  1183. goto stall;
  1184. if (u.word[0] == 0 && u.word[1] == 0)
  1185. goto stall;
  1186. goto got_setup;
  1187. } else {
  1188. /*
  1189. * some random early IRQ:
  1190. * - we acked FST
  1191. * - IPR cleared
  1192. * - OPR got set, without SA (likely status stage)
  1193. */
  1194. debug("random IRQ %X %X\n", udccs0,
  1195. readl(&dev->regs->udccs[0]));
  1196. writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR),
  1197. &dev->regs->udccs[0]);
  1198. }
  1199. break;
  1200. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  1201. if (udccs0 & UDCCS0_OPR) {
  1202. debug("ep0in premature status\n");
  1203. if (req)
  1204. done(ep, req, 0);
  1205. ep0_idle(dev);
  1206. } else /* irq was IPR clearing */ {
  1207. if (req) {
  1208. debug("next ep0 in packet\n");
  1209. /* this IN packet might finish the request */
  1210. (void) write_ep0_fifo(ep, req);
  1211. } /* else IN token before response was written */
  1212. }
  1213. break;
  1214. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  1215. if (udccs0 & UDCCS0_OPR) {
  1216. if (req) {
  1217. /* this OUT packet might finish the request */
  1218. if (read_ep0_fifo(ep, req))
  1219. done(ep, req, 0);
  1220. /* else more OUT packets expected */
  1221. } /* else OUT token before read was issued */
  1222. } else /* irq was IPR clearing */ {
  1223. debug("ep0out premature status\n");
  1224. if (req)
  1225. done(ep, req, 0);
  1226. ep0_idle(dev);
  1227. }
  1228. break;
  1229. case EP0_END_XFER:
  1230. if (req)
  1231. done(ep, req, 0);
  1232. /*
  1233. * ack control-IN status (maybe in-zlp was skipped)
  1234. * also appears after some config change events.
  1235. */
  1236. if (udccs0 & UDCCS0_OPR)
  1237. writel(UDCCS0_OPR, &dev->regs->udccs[0]);
  1238. ep0_idle(dev);
  1239. break;
  1240. case EP0_STALL:
  1241. writel(UDCCS0_FST, &dev->regs->udccs[0]);
  1242. break;
  1243. }
  1244. writel(USIR0_IR0, &dev->regs->usir0);
  1245. }
  1246. static void handle_ep(struct pxa25x_ep *ep)
  1247. {
  1248. struct pxa25x_request *req;
  1249. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  1250. int completed;
  1251. u32 udccs, tmp;
  1252. do {
  1253. completed = 0;
  1254. if (likely(!list_empty(&ep->queue)))
  1255. req = list_entry(ep->queue.next,
  1256. struct pxa25x_request, queue);
  1257. else
  1258. req = NULL;
  1259. /* TODO check FST handling */
  1260. udccs = readl(ep->reg_udccs);
  1261. if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */
  1262. tmp = UDCCS_BI_TUR;
  1263. if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
  1264. tmp |= UDCCS_BI_SST;
  1265. tmp &= udccs;
  1266. if (likely(tmp))
  1267. writel(tmp, ep->reg_udccs);
  1268. if (req && likely((udccs & UDCCS_BI_TFS) != 0))
  1269. completed = write_fifo(ep, req);
  1270. } else { /* irq from RPC (or for ISO, ROF) */
  1271. if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
  1272. tmp = UDCCS_BO_SST | UDCCS_BO_DME;
  1273. else
  1274. tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
  1275. tmp &= udccs;
  1276. if (likely(tmp))
  1277. writel(tmp, ep->reg_udccs);
  1278. /* fifos can hold packets, ready for reading... */
  1279. if (likely(req))
  1280. completed = read_fifo(ep, req);
  1281. else
  1282. pio_irq_disable(ep->bEndpointAddress);
  1283. }
  1284. ep->pio_irqs++;
  1285. } while (completed);
  1286. }
  1287. /*
  1288. * pxa25x_udc_irq - interrupt handler
  1289. *
  1290. * avoid delays in ep0 processing. the control handshaking isn't always
  1291. * under software control (pxa250c0 and the pxa255 are better), and delays
  1292. * could cause usb protocol errors.
  1293. */
  1294. static struct pxa25x_udc memory;
  1295. static int
  1296. pxa25x_udc_irq(void)
  1297. {
  1298. struct pxa25x_udc *dev = &memory;
  1299. int handled;
  1300. test_watchdog(dev);
  1301. dev->stats.irqs++;
  1302. do {
  1303. u32 udccr = readl(&dev->regs->udccr);
  1304. handled = 0;
  1305. /* SUSpend Interrupt Request */
  1306. if (unlikely(udccr & UDCCR_SUSIR)) {
  1307. udc_ack_int_UDCCR(UDCCR_SUSIR);
  1308. handled = 1;
  1309. debug("USB suspend\n");
  1310. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  1311. && dev->driver
  1312. && dev->driver->suspend)
  1313. dev->driver->suspend(&dev->gadget);
  1314. ep0_idle(dev);
  1315. }
  1316. /* RESume Interrupt Request */
  1317. if (unlikely(udccr & UDCCR_RESIR)) {
  1318. udc_ack_int_UDCCR(UDCCR_RESIR);
  1319. handled = 1;
  1320. debug("USB resume\n");
  1321. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  1322. && dev->driver
  1323. && dev->driver->resume)
  1324. dev->driver->resume(&dev->gadget);
  1325. }
  1326. /* ReSeT Interrupt Request - USB reset */
  1327. if (unlikely(udccr & UDCCR_RSTIR)) {
  1328. udc_ack_int_UDCCR(UDCCR_RSTIR);
  1329. handled = 1;
  1330. if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) {
  1331. debug("USB reset start\n");
  1332. /*
  1333. * reset driver and endpoints,
  1334. * in case that's not yet done
  1335. */
  1336. stop_activity(dev, dev->driver);
  1337. } else {
  1338. debug("USB reset end\n");
  1339. dev->gadget.speed = USB_SPEED_FULL;
  1340. memset(&dev->stats, 0, sizeof dev->stats);
  1341. /* driver and endpoints are still reset */
  1342. }
  1343. } else {
  1344. u32 uicr0 = readl(&dev->regs->uicr0);
  1345. u32 uicr1 = readl(&dev->regs->uicr1);
  1346. u32 usir0 = readl(&dev->regs->usir0);
  1347. u32 usir1 = readl(&dev->regs->usir1);
  1348. usir0 = usir0 & ~uicr0;
  1349. usir1 = usir1 & ~uicr1;
  1350. int i;
  1351. if (unlikely(!usir0 && !usir1))
  1352. continue;
  1353. debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0);
  1354. /* control traffic */
  1355. if (usir0 & USIR0_IR0) {
  1356. dev->ep[0].pio_irqs++;
  1357. handle_ep0(dev);
  1358. handled = 1;
  1359. }
  1360. /* endpoint data transfers */
  1361. for (i = 0; i < 8; i++) {
  1362. u32 tmp = 1 << i;
  1363. if (i && (usir0 & tmp)) {
  1364. handle_ep(&dev->ep[i]);
  1365. setbits_le32(&dev->regs->usir0, tmp);
  1366. handled = 1;
  1367. }
  1368. #ifndef CONFIG_USB_PXA25X_SMALL
  1369. if (usir1 & tmp) {
  1370. handle_ep(&dev->ep[i+8]);
  1371. setbits_le32(&dev->regs->usir1, tmp);
  1372. handled = 1;
  1373. }
  1374. #endif
  1375. }
  1376. }
  1377. /* we could also ask for 1 msec SOF (SIR) interrupts */
  1378. } while (handled);
  1379. return IRQ_HANDLED;
  1380. }
  1381. /*-------------------------------------------------------------------------*/
  1382. /*
  1383. * this uses load-time allocation and initialization (instead of
  1384. * doing it at run-time) to save code, eliminate fault paths, and
  1385. * be more obviously correct.
  1386. */
  1387. static struct pxa25x_udc memory = {
  1388. .regs = UDC_REGS,
  1389. .gadget = {
  1390. .ops = &pxa25x_udc_ops,
  1391. .ep0 = &memory.ep[0].ep,
  1392. .name = driver_name,
  1393. },
  1394. /* control endpoint */
  1395. .ep[0] = {
  1396. .ep = {
  1397. .name = ep0name,
  1398. .ops = &pxa25x_ep_ops,
  1399. .maxpacket = EP0_FIFO_SIZE,
  1400. },
  1401. .dev = &memory,
  1402. .reg_udccs = &UDC_REGS->udccs[0],
  1403. .reg_uddr = &UDC_REGS->uddr0,
  1404. },
  1405. /* first group of endpoints */
  1406. .ep[1] = {
  1407. .ep = {
  1408. .name = "ep1in-bulk",
  1409. .ops = &pxa25x_ep_ops,
  1410. .maxpacket = BULK_FIFO_SIZE,
  1411. },
  1412. .dev = &memory,
  1413. .fifo_size = BULK_FIFO_SIZE,
  1414. .bEndpointAddress = USB_DIR_IN | 1,
  1415. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1416. .reg_udccs = &UDC_REGS->udccs[1],
  1417. .reg_uddr = &UDC_REGS->uddr1,
  1418. },
  1419. .ep[2] = {
  1420. .ep = {
  1421. .name = "ep2out-bulk",
  1422. .ops = &pxa25x_ep_ops,
  1423. .maxpacket = BULK_FIFO_SIZE,
  1424. },
  1425. .dev = &memory,
  1426. .fifo_size = BULK_FIFO_SIZE,
  1427. .bEndpointAddress = 2,
  1428. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1429. .reg_udccs = &UDC_REGS->udccs[2],
  1430. .reg_ubcr = &UDC_REGS->ubcr2,
  1431. .reg_uddr = &UDC_REGS->uddr2,
  1432. },
  1433. #ifndef CONFIG_USB_PXA25X_SMALL
  1434. .ep[3] = {
  1435. .ep = {
  1436. .name = "ep3in-iso",
  1437. .ops = &pxa25x_ep_ops,
  1438. .maxpacket = ISO_FIFO_SIZE,
  1439. },
  1440. .dev = &memory,
  1441. .fifo_size = ISO_FIFO_SIZE,
  1442. .bEndpointAddress = USB_DIR_IN | 3,
  1443. .bmAttributes = USB_ENDPOINT_XFER_ISOC,
  1444. .reg_udccs = &UDC_REGS->udccs[3],
  1445. .reg_uddr = &UDC_REGS->uddr3,
  1446. },
  1447. .ep[4] = {
  1448. .ep = {
  1449. .name = "ep4out-iso",
  1450. .ops = &pxa25x_ep_ops,
  1451. .maxpacket = ISO_FIFO_SIZE,
  1452. },
  1453. .dev = &memory,
  1454. .fifo_size = ISO_FIFO_SIZE,
  1455. .bEndpointAddress = 4,
  1456. .bmAttributes = USB_ENDPOINT_XFER_ISOC,
  1457. .reg_udccs = &UDC_REGS->udccs[4],
  1458. .reg_ubcr = &UDC_REGS->ubcr4,
  1459. .reg_uddr = &UDC_REGS->uddr4,
  1460. },
  1461. .ep[5] = {
  1462. .ep = {
  1463. .name = "ep5in-int",
  1464. .ops = &pxa25x_ep_ops,
  1465. .maxpacket = INT_FIFO_SIZE,
  1466. },
  1467. .dev = &memory,
  1468. .fifo_size = INT_FIFO_SIZE,
  1469. .bEndpointAddress = USB_DIR_IN | 5,
  1470. .bmAttributes = USB_ENDPOINT_XFER_INT,
  1471. .reg_udccs = &UDC_REGS->udccs[5],
  1472. .reg_uddr = &UDC_REGS->uddr5,
  1473. },
  1474. /* second group of endpoints */
  1475. .ep[6] = {
  1476. .ep = {
  1477. .name = "ep6in-bulk",
  1478. .ops = &pxa25x_ep_ops,
  1479. .maxpacket = BULK_FIFO_SIZE,
  1480. },
  1481. .dev = &memory,
  1482. .fifo_size = BULK_FIFO_SIZE,
  1483. .bEndpointAddress = USB_DIR_IN | 6,
  1484. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1485. .reg_udccs = &UDC_REGS->udccs[6],
  1486. .reg_uddr = &UDC_REGS->uddr6,
  1487. },
  1488. .ep[7] = {
  1489. .ep = {
  1490. .name = "ep7out-bulk",
  1491. .ops = &pxa25x_ep_ops,
  1492. .maxpacket = BULK_FIFO_SIZE,
  1493. },
  1494. .dev = &memory,
  1495. .fifo_size = BULK_FIFO_SIZE,
  1496. .bEndpointAddress = 7,
  1497. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1498. .reg_udccs = &UDC_REGS->udccs[7],
  1499. .reg_ubcr = &UDC_REGS->ubcr7,
  1500. .reg_uddr = &UDC_REGS->uddr7,
  1501. },
  1502. .ep[8] = {
  1503. .ep = {
  1504. .name = "ep8in-iso",
  1505. .ops = &pxa25x_ep_ops,
  1506. .maxpacket = ISO_FIFO_SIZE,
  1507. },
  1508. .dev = &memory,
  1509. .fifo_size = ISO_FIFO_SIZE,
  1510. .bEndpointAddress = USB_DIR_IN | 8,
  1511. .bmAttributes = USB_ENDPOINT_XFER_ISOC,
  1512. .reg_udccs = &UDC_REGS->udccs[8],
  1513. .reg_uddr = &UDC_REGS->uddr8,
  1514. },
  1515. .ep[9] = {
  1516. .ep = {
  1517. .name = "ep9out-iso",
  1518. .ops = &pxa25x_ep_ops,
  1519. .maxpacket = ISO_FIFO_SIZE,
  1520. },
  1521. .dev = &memory,
  1522. .fifo_size = ISO_FIFO_SIZE,
  1523. .bEndpointAddress = 9,
  1524. .bmAttributes = USB_ENDPOINT_XFER_ISOC,
  1525. .reg_udccs = &UDC_REGS->udccs[9],
  1526. .reg_ubcr = &UDC_REGS->ubcr9,
  1527. .reg_uddr = &UDC_REGS->uddr9,
  1528. },
  1529. .ep[10] = {
  1530. .ep = {
  1531. .name = "ep10in-int",
  1532. .ops = &pxa25x_ep_ops,
  1533. .maxpacket = INT_FIFO_SIZE,
  1534. },
  1535. .dev = &memory,
  1536. .fifo_size = INT_FIFO_SIZE,
  1537. .bEndpointAddress = USB_DIR_IN | 10,
  1538. .bmAttributes = USB_ENDPOINT_XFER_INT,
  1539. .reg_udccs = &UDC_REGS->udccs[10],
  1540. .reg_uddr = &UDC_REGS->uddr10,
  1541. },
  1542. /* third group of endpoints */
  1543. .ep[11] = {
  1544. .ep = {
  1545. .name = "ep11in-bulk",
  1546. .ops = &pxa25x_ep_ops,
  1547. .maxpacket = BULK_FIFO_SIZE,
  1548. },
  1549. .dev = &memory,
  1550. .fifo_size = BULK_FIFO_SIZE,
  1551. .bEndpointAddress = USB_DIR_IN | 11,
  1552. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1553. .reg_udccs = &UDC_REGS->udccs[11],
  1554. .reg_uddr = &UDC_REGS->uddr11,
  1555. },
  1556. .ep[12] = {
  1557. .ep = {
  1558. .name = "ep12out-bulk",
  1559. .ops = &pxa25x_ep_ops,
  1560. .maxpacket = BULK_FIFO_SIZE,
  1561. },
  1562. .dev = &memory,
  1563. .fifo_size = BULK_FIFO_SIZE,
  1564. .bEndpointAddress = 12,
  1565. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1566. .reg_udccs = &UDC_REGS->udccs[12],
  1567. .reg_ubcr = &UDC_REGS->ubcr12,
  1568. .reg_uddr = &UDC_REGS->uddr12,
  1569. },
  1570. .ep[13] = {
  1571. .ep = {
  1572. .name = "ep13in-iso",
  1573. .ops = &pxa25x_ep_ops,
  1574. .maxpacket = ISO_FIFO_SIZE,
  1575. },
  1576. .dev = &memory,
  1577. .fifo_size = ISO_FIFO_SIZE,
  1578. .bEndpointAddress = USB_DIR_IN | 13,
  1579. .bmAttributes = USB_ENDPOINT_XFER_ISOC,
  1580. .reg_udccs = &UDC_REGS->udccs[13],
  1581. .reg_uddr = &UDC_REGS->uddr13,
  1582. },
  1583. .ep[14] = {
  1584. .ep = {
  1585. .name = "ep14out-iso",
  1586. .ops = &pxa25x_ep_ops,
  1587. .maxpacket = ISO_FIFO_SIZE,
  1588. },
  1589. .dev = &memory,
  1590. .fifo_size = ISO_FIFO_SIZE,
  1591. .bEndpointAddress = 14,
  1592. .bmAttributes = USB_ENDPOINT_XFER_ISOC,
  1593. .reg_udccs = &UDC_REGS->udccs[14],
  1594. .reg_ubcr = &UDC_REGS->ubcr14,
  1595. .reg_uddr = &UDC_REGS->uddr14,
  1596. },
  1597. .ep[15] = {
  1598. .ep = {
  1599. .name = "ep15in-int",
  1600. .ops = &pxa25x_ep_ops,
  1601. .maxpacket = INT_FIFO_SIZE,
  1602. },
  1603. .dev = &memory,
  1604. .fifo_size = INT_FIFO_SIZE,
  1605. .bEndpointAddress = USB_DIR_IN | 15,
  1606. .bmAttributes = USB_ENDPOINT_XFER_INT,
  1607. .reg_udccs = &UDC_REGS->udccs[15],
  1608. .reg_uddr = &UDC_REGS->uddr15,
  1609. },
  1610. #endif /* !CONFIG_USB_PXA25X_SMALL */
  1611. };
  1612. static void udc_command(int cmd)
  1613. {
  1614. switch (cmd) {
  1615. case PXA2XX_UDC_CMD_CONNECT:
  1616. setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
  1617. GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
  1618. /* enable pullup */
  1619. writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
  1620. GPCR(CONFIG_USB_DEV_PULLUP_GPIO));
  1621. debug("Connected to USB\n");
  1622. break;
  1623. case PXA2XX_UDC_CMD_DISCONNECT:
  1624. /* disable pullup resistor */
  1625. writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
  1626. GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
  1627. /* setup pin as input, line will float */
  1628. clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
  1629. GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
  1630. debug("Disconnected from USB\n");
  1631. break;
  1632. }
  1633. }
  1634. static struct pxa2xx_udc_mach_info mach_info = {
  1635. .udc_command = udc_command,
  1636. };
  1637. /*
  1638. * when a driver is successfully registered, it will receive
  1639. * control requests including set_configuration(), which enables
  1640. * non-control requests. then usb traffic follows until a
  1641. * disconnect is reported. then a host may connect again, or
  1642. * the driver might get unbound.
  1643. */
  1644. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1645. {
  1646. struct pxa25x_udc *dev = &memory;
  1647. int retval;
  1648. uint32_t chiprev;
  1649. if (!driver
  1650. || driver->speed < USB_SPEED_FULL
  1651. || !driver->disconnect
  1652. || !driver->setup)
  1653. return -EINVAL;
  1654. if (!dev)
  1655. return -ENODEV;
  1656. if (dev->driver)
  1657. return -EBUSY;
  1658. /* Enable clock for usb controller */
  1659. setbits_le32(CKEN, CKEN11_USB);
  1660. /* first hook up the driver ... */
  1661. dev->driver = driver;
  1662. dev->pullup = 1;
  1663. /* trigger chiprev-specific logic */
  1664. switch ((chiprev = pxa_get_cpu_revision())) {
  1665. case PXA255_A0:
  1666. dev->has_cfr = 1;
  1667. break;
  1668. case PXA250_A0:
  1669. case PXA250_A1:
  1670. /* A0/A1 "not released"; ep 13, 15 unusable */
  1671. /* fall through */
  1672. case PXA250_B2: case PXA210_B2:
  1673. case PXA250_B1: case PXA210_B1:
  1674. case PXA250_B0: case PXA210_B0:
  1675. /* OUT-DMA is broken ... */
  1676. /* fall through */
  1677. case PXA250_C0: case PXA210_C0:
  1678. break;
  1679. default:
  1680. printf("%s: unrecognized processor: %08x\n",
  1681. DRIVER_NAME, chiprev);
  1682. return -ENODEV;
  1683. }
  1684. the_controller = dev;
  1685. /* prepare watchdog timer */
  1686. dev->watchdog.running = 0;
  1687. dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */
  1688. dev->watchdog.function = udc_watchdog;
  1689. dev->mach = &mach_info;
  1690. udc_disable(dev);
  1691. udc_reinit(dev);
  1692. dev->gadget.name = "pxa2xx_udc";
  1693. retval = driver->bind(&dev->gadget);
  1694. if (retval) {
  1695. printf("bind to driver %s --> error %d\n",
  1696. DRIVER_NAME, retval);
  1697. dev->driver = NULL;
  1698. return retval;
  1699. }
  1700. /*
  1701. * ... then enable host detection and ep0; and we're ready
  1702. * for set_configuration as well as eventual disconnect.
  1703. */
  1704. printf("registered gadget driver '%s'\n", DRIVER_NAME);
  1705. pullup(dev);
  1706. dump_state(dev);
  1707. return 0;
  1708. }
  1709. static void
  1710. stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
  1711. {
  1712. int i;
  1713. /* don't disconnect drivers more than once */
  1714. if (dev->gadget.speed == USB_SPEED_UNKNOWN)
  1715. driver = NULL;
  1716. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1717. /* prevent new request submissions, kill any outstanding requests */
  1718. for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
  1719. struct pxa25x_ep *ep = &dev->ep[i];
  1720. ep->stopped = 1;
  1721. nuke(ep, -ESHUTDOWN);
  1722. }
  1723. stop_watchdog(dev);
  1724. /* report disconnect; the driver is already quiesced */
  1725. if (driver)
  1726. driver->disconnect(&dev->gadget);
  1727. /* re-init driver-visible data structures */
  1728. udc_reinit(dev);
  1729. }
  1730. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1731. {
  1732. struct pxa25x_udc *dev = the_controller;
  1733. if (!dev)
  1734. return -ENODEV;
  1735. if (!driver || driver != dev->driver || !driver->unbind)
  1736. return -EINVAL;
  1737. local_irq_disable();
  1738. dev->pullup = 0;
  1739. pullup(dev);
  1740. stop_activity(dev, driver);
  1741. local_irq_enable();
  1742. driver->unbind(&dev->gadget);
  1743. dev->driver = NULL;
  1744. printf("unregistered gadget driver '%s'\n", DRIVER_NAME);
  1745. dump_state(dev);
  1746. the_controller = NULL;
  1747. clrbits_le32(CKEN, CKEN11_USB);
  1748. return 0;
  1749. }
  1750. extern void udc_disconnect(void)
  1751. {
  1752. setbits_le32(CKEN, CKEN11_USB);
  1753. udc_clear_mask_UDCCR(UDCCR_UDE);
  1754. udc_command(PXA2XX_UDC_CMD_DISCONNECT);
  1755. clrbits_le32(CKEN, CKEN11_USB);
  1756. }
  1757. /*-------------------------------------------------------------------------*/
  1758. extern int
  1759. usb_gadget_handle_interrupts(int index)
  1760. {
  1761. return pxa25x_udc_irq();
  1762. }