dwc2_udc_otg_phy.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/usb/gadget/dwc2_udc_otg.c
  4. * Designware DWC2 on-chip full/high speed USB OTG 2.0 device controllers
  5. *
  6. * Copyright (C) 2008 for Samsung Electronics
  7. *
  8. * BSP Support for Samsung's UDC driver
  9. * available at:
  10. * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  11. *
  12. * State machine bugfixes:
  13. * Marek Szyprowski <m.szyprowski@samsung.com>
  14. *
  15. * Ported to u-boot:
  16. * Marek Szyprowski <m.szyprowski@samsung.com>
  17. * Lukasz Majewski <l.majewski@samsumg.com>
  18. */
  19. #include <common.h>
  20. #include <linux/delay.h>
  21. #include <linux/errno.h>
  22. #include <linux/list.h>
  23. #include <malloc.h>
  24. #include <linux/usb/ch9.h>
  25. #include <linux/usb/gadget.h>
  26. #include <asm/byteorder.h>
  27. #include <asm/unaligned.h>
  28. #include <asm/io.h>
  29. #include <asm/mach-types.h>
  30. #include "dwc2_udc_otg_regs.h"
  31. #include "dwc2_udc_otg_priv.h"
  32. #include <usb/dwc2_udc.h>
  33. void otg_phy_init(struct dwc2_udc *dev)
  34. {
  35. unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
  36. struct dwc2_usbotg_phy *phy =
  37. (struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
  38. dev->pdata->phy_control(1);
  39. /* USB PHY0 Enable */
  40. printf("USB PHY0 Enable\n");
  41. /* Enable PHY */
  42. writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
  43. if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
  44. writel((readl(&phy->phypwr)
  45. &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
  46. &~FORCE_SUSPEND_0), &phy->phypwr);
  47. else /* C110 GONI */
  48. writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
  49. &~FORCE_SUSPEND_0), &phy->phypwr);
  50. if (s5p_cpu_id == 0x4412)
  51. writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
  52. EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
  53. &phy->phyclk); /* PLL 24Mhz */
  54. else
  55. writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
  56. CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
  57. writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
  58. | PHY_SW_RST0, &phy->rstcon);
  59. udelay(10);
  60. writel(readl(&phy->rstcon)
  61. &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
  62. udelay(10);
  63. }
  64. void otg_phy_off(struct dwc2_udc *dev)
  65. {
  66. unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
  67. struct dwc2_usbotg_phy *phy =
  68. (struct dwc2_usbotg_phy *)dev->pdata->regs_phy;
  69. /* reset controller just in case */
  70. writel(PHY_SW_RST0, &phy->rstcon);
  71. udelay(20);
  72. writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
  73. udelay(20);
  74. writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
  75. | FORCE_SUSPEND_0, &phy->phypwr);
  76. writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
  77. writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
  78. &phy->phyclk);
  79. udelay(10000);
  80. dev->pdata->phy_control(0);
  81. }