smsc95xx.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Copyright (c) 2011 The Chromium OS Authors.
  5. * Copyright (C) 2009 NVIDIA, Corporation
  6. * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <memalign.h>
  14. #include <net.h>
  15. #include <usb.h>
  16. #include <asm/unaligned.h>
  17. #include <linux/delay.h>
  18. #include <linux/mii.h>
  19. #include "usb_ether.h"
  20. /* SMSC LAN95xx based USB 2.0 Ethernet Devices */
  21. /* LED defines */
  22. #define LED_GPIO_CFG (0x24)
  23. #define LED_GPIO_CFG_SPD_LED (0x01000000)
  24. #define LED_GPIO_CFG_LNK_LED (0x00100000)
  25. #define LED_GPIO_CFG_FDX_LED (0x00010000)
  26. /* Tx command words */
  27. #define TX_CMD_A_FIRST_SEG_ 0x00002000
  28. #define TX_CMD_A_LAST_SEG_ 0x00001000
  29. /* Rx status word */
  30. #define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
  31. #define RX_STS_ES_ 0x00008000 /* Error Summary */
  32. /* SCSRs */
  33. #define ID_REV 0x00
  34. #define INT_STS 0x08
  35. #define TX_CFG 0x10
  36. #define TX_CFG_ON_ 0x00000004
  37. #define HW_CFG 0x14
  38. #define HW_CFG_BIR_ 0x00001000
  39. #define HW_CFG_RXDOFF_ 0x00000600
  40. #define HW_CFG_MEF_ 0x00000020
  41. #define HW_CFG_BCE_ 0x00000002
  42. #define HW_CFG_LRST_ 0x00000008
  43. #define PM_CTRL 0x20
  44. #define PM_CTL_PHY_RST_ 0x00000010
  45. #define AFC_CFG 0x2C
  46. /*
  47. * Hi watermark = 15.5Kb (~10 mtu pkts)
  48. * low watermark = 3k (~2 mtu pkts)
  49. * backpressure duration = ~ 350us
  50. * Apply FC on any frame.
  51. */
  52. #define AFC_CFG_DEFAULT 0x00F830A1
  53. #define E2P_CMD 0x30
  54. #define E2P_CMD_BUSY_ 0x80000000
  55. #define E2P_CMD_READ_ 0x00000000
  56. #define E2P_CMD_TIMEOUT_ 0x00000400
  57. #define E2P_CMD_LOADED_ 0x00000200
  58. #define E2P_CMD_ADDR_ 0x000001FF
  59. #define E2P_DATA 0x34
  60. #define BURST_CAP 0x38
  61. #define INT_EP_CTL 0x68
  62. #define INT_EP_CTL_PHY_INT_ 0x00008000
  63. #define BULK_IN_DLY 0x6C
  64. /* MAC CSRs */
  65. #define MAC_CR 0x100
  66. #define MAC_CR_MCPAS_ 0x00080000
  67. #define MAC_CR_PRMS_ 0x00040000
  68. #define MAC_CR_HPFILT_ 0x00002000
  69. #define MAC_CR_TXEN_ 0x00000008
  70. #define MAC_CR_RXEN_ 0x00000004
  71. #define ADDRH 0x104
  72. #define ADDRL 0x108
  73. #define MII_ADDR 0x114
  74. #define MII_WRITE_ 0x02
  75. #define MII_BUSY_ 0x01
  76. #define MII_READ_ 0x00 /* ~of MII Write bit */
  77. #define MII_DATA 0x118
  78. #define FLOW 0x11C
  79. #define VLAN1 0x120
  80. #define COE_CR 0x130
  81. #define Tx_COE_EN_ 0x00010000
  82. #define Rx_COE_EN_ 0x00000001
  83. /* Vendor-specific PHY Definitions */
  84. #define PHY_INT_SRC 29
  85. #define PHY_INT_MASK 30
  86. #define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
  87. #define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
  88. #define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
  89. PHY_INT_MASK_LINK_DOWN_)
  90. /* USB Vendor Requests */
  91. #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
  92. #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
  93. /* Some extra defines */
  94. #define HS_USB_PKT_SIZE 512
  95. #define FS_USB_PKT_SIZE 64
  96. /* 5/33 is lower limit for BURST_CAP to work */
  97. #define DEFAULT_HS_BURST_CAP_SIZE (5 * HS_USB_PKT_SIZE)
  98. #define DEFAULT_FS_BURST_CAP_SIZE (33 * FS_USB_PKT_SIZE)
  99. #define DEFAULT_BULK_IN_DELAY 0x00002000
  100. #define MAX_SINGLE_PACKET_SIZE 2048
  101. #define EEPROM_MAC_OFFSET 0x01
  102. #define SMSC95XX_INTERNAL_PHY_ID 1
  103. #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
  104. /* local defines */
  105. #define SMSC95XX_BASE_NAME "sms"
  106. #define USB_CTRL_SET_TIMEOUT 5000
  107. #define USB_CTRL_GET_TIMEOUT 5000
  108. #define USB_BULK_SEND_TIMEOUT 5000
  109. #define USB_BULK_RECV_TIMEOUT 5000
  110. #define RX_URB_SIZE DEFAULT_HS_BURST_CAP_SIZE
  111. #define PHY_CONNECT_TIMEOUT 5000
  112. #define TURBO_MODE
  113. #ifndef CONFIG_DM_ETH
  114. /* local vars */
  115. static int curr_eth_dev; /* index for name of next device detected */
  116. #endif
  117. /* driver private */
  118. struct smsc95xx_private {
  119. #ifdef CONFIG_DM_ETH
  120. struct ueth_data ueth;
  121. #endif
  122. size_t rx_urb_size; /* maximum USB URB size */
  123. u32 mac_cr; /* MAC control register value */
  124. int have_hwaddr; /* 1 if we have a hardware MAC address */
  125. };
  126. /*
  127. * Smsc95xx infrastructure commands
  128. */
  129. static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
  130. {
  131. int len;
  132. ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
  133. cpu_to_le32s(&data);
  134. tmpbuf[0] = data;
  135. len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
  136. USB_VENDOR_REQUEST_WRITE_REGISTER,
  137. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  138. 0, index, tmpbuf, sizeof(data),
  139. USB_CTRL_SET_TIMEOUT);
  140. if (len != sizeof(data)) {
  141. debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
  142. index, data, len);
  143. return -EIO;
  144. }
  145. return 0;
  146. }
  147. static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
  148. {
  149. int len;
  150. ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
  151. len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
  152. USB_VENDOR_REQUEST_READ_REGISTER,
  153. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  154. 0, index, tmpbuf, sizeof(*data),
  155. USB_CTRL_GET_TIMEOUT);
  156. *data = tmpbuf[0];
  157. if (len != sizeof(*data)) {
  158. debug("smsc95xx_read_reg failed: index=%d, len=%d",
  159. index, len);
  160. return -EIO;
  161. }
  162. le32_to_cpus(data);
  163. return 0;
  164. }
  165. /* Loop until the read is completed with timeout */
  166. static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
  167. {
  168. unsigned long start_time = get_timer(0);
  169. u32 val;
  170. do {
  171. smsc95xx_read_reg(udev, MII_ADDR, &val);
  172. if (!(val & MII_BUSY_))
  173. return 0;
  174. } while (get_timer(start_time) < 1000);
  175. return -ETIMEDOUT;
  176. }
  177. static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
  178. {
  179. u32 val, addr;
  180. /* confirm MII not busy */
  181. if (smsc95xx_phy_wait_not_busy(udev)) {
  182. debug("MII is busy in smsc95xx_mdio_read\n");
  183. return -ETIMEDOUT;
  184. }
  185. /* set the address, index & direction (read from PHY) */
  186. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  187. smsc95xx_write_reg(udev, MII_ADDR, addr);
  188. if (smsc95xx_phy_wait_not_busy(udev)) {
  189. debug("Timed out reading MII reg %02X\n", idx);
  190. return -ETIMEDOUT;
  191. }
  192. smsc95xx_read_reg(udev, MII_DATA, &val);
  193. return (u16)(val & 0xFFFF);
  194. }
  195. static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
  196. int regval)
  197. {
  198. u32 val, addr;
  199. /* confirm MII not busy */
  200. if (smsc95xx_phy_wait_not_busy(udev)) {
  201. debug("MII is busy in smsc95xx_mdio_write\n");
  202. return;
  203. }
  204. val = regval;
  205. smsc95xx_write_reg(udev, MII_DATA, val);
  206. /* set the address, index & direction (write to PHY) */
  207. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  208. smsc95xx_write_reg(udev, MII_ADDR, addr);
  209. if (smsc95xx_phy_wait_not_busy(udev))
  210. debug("Timed out writing MII reg %02X\n", idx);
  211. }
  212. static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
  213. {
  214. unsigned long start_time = get_timer(0);
  215. u32 val;
  216. do {
  217. smsc95xx_read_reg(udev, E2P_CMD, &val);
  218. if (!(val & E2P_CMD_BUSY_))
  219. return 0;
  220. udelay(40);
  221. } while (get_timer(start_time) < 1 * 1000 * 1000);
  222. debug("EEPROM is busy\n");
  223. return -ETIMEDOUT;
  224. }
  225. static int smsc95xx_wait_eeprom(struct usb_device *udev)
  226. {
  227. unsigned long start_time = get_timer(0);
  228. u32 val;
  229. do {
  230. smsc95xx_read_reg(udev, E2P_CMD, &val);
  231. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  232. break;
  233. udelay(40);
  234. } while (get_timer(start_time) < 1 * 1000 * 1000);
  235. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  236. debug("EEPROM read operation timeout\n");
  237. return -ETIMEDOUT;
  238. }
  239. return 0;
  240. }
  241. static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
  242. u8 *data)
  243. {
  244. u32 val;
  245. int i, ret;
  246. ret = smsc95xx_eeprom_confirm_not_busy(udev);
  247. if (ret)
  248. return ret;
  249. for (i = 0; i < length; i++) {
  250. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  251. smsc95xx_write_reg(udev, E2P_CMD, val);
  252. ret = smsc95xx_wait_eeprom(udev);
  253. if (ret < 0)
  254. return ret;
  255. smsc95xx_read_reg(udev, E2P_DATA, &val);
  256. data[i] = val & 0xFF;
  257. offset++;
  258. }
  259. return 0;
  260. }
  261. /*
  262. * mii_nway_restart - restart NWay (autonegotiation) for this interface
  263. *
  264. * Returns 0 on success, negative on error.
  265. */
  266. static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
  267. {
  268. int bmcr;
  269. int r = -1;
  270. /* if autoneg is off, it's an error */
  271. bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
  272. if (bmcr & BMCR_ANENABLE) {
  273. bmcr |= BMCR_ANRESTART;
  274. smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
  275. r = 0;
  276. }
  277. return r;
  278. }
  279. static int smsc95xx_phy_initialize(struct usb_device *udev,
  280. struct ueth_data *dev)
  281. {
  282. smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
  283. smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
  284. ADVERTISE_ALL | ADVERTISE_CSMA |
  285. ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  286. /* read to clear */
  287. smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
  288. smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
  289. PHY_INT_MASK_DEFAULT_);
  290. mii_nway_restart(udev, dev);
  291. debug("phy initialised succesfully\n");
  292. return 0;
  293. }
  294. static int smsc95xx_init_mac_address(unsigned char *enetaddr,
  295. struct usb_device *udev)
  296. {
  297. int ret;
  298. /* try reading mac address from EEPROM */
  299. ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
  300. if (ret)
  301. return ret;
  302. if (is_valid_ethaddr(enetaddr)) {
  303. /* eeprom values are valid so use them */
  304. debug("MAC address read from EEPROM\n");
  305. return 0;
  306. }
  307. /*
  308. * No eeprom, or eeprom values are invalid. Generating a random MAC
  309. * address is not safe. Just return an error.
  310. */
  311. debug("Invalid MAC address read from EEPROM\n");
  312. return -ENXIO;
  313. }
  314. static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
  315. struct smsc95xx_private *priv,
  316. unsigned char *enetaddr)
  317. {
  318. u32 addr_lo = get_unaligned_le32(&enetaddr[0]);
  319. u32 addr_hi = get_unaligned_le16(&enetaddr[4]);
  320. int ret;
  321. /* set hardware address */
  322. debug("** %s()\n", __func__);
  323. ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
  324. if (ret < 0)
  325. return ret;
  326. ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
  327. if (ret < 0)
  328. return ret;
  329. debug("MAC %pM\n", enetaddr);
  330. priv->have_hwaddr = 1;
  331. return 0;
  332. }
  333. /* Enable or disable Tx & Rx checksum offload engines */
  334. static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
  335. int use_rx_csum)
  336. {
  337. u32 read_buf;
  338. int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
  339. if (ret < 0)
  340. return ret;
  341. if (use_tx_csum)
  342. read_buf |= Tx_COE_EN_;
  343. else
  344. read_buf &= ~Tx_COE_EN_;
  345. if (use_rx_csum)
  346. read_buf |= Rx_COE_EN_;
  347. else
  348. read_buf &= ~Rx_COE_EN_;
  349. ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
  350. if (ret < 0)
  351. return ret;
  352. debug("COE_CR = 0x%08x\n", read_buf);
  353. return 0;
  354. }
  355. static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
  356. {
  357. /* No multicast in u-boot */
  358. priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  359. }
  360. /* starts the TX path */
  361. static void smsc95xx_start_tx_path(struct usb_device *udev,
  362. struct smsc95xx_private *priv)
  363. {
  364. u32 reg_val;
  365. /* Enable Tx at MAC */
  366. priv->mac_cr |= MAC_CR_TXEN_;
  367. smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
  368. /* Enable Tx at SCSRs */
  369. reg_val = TX_CFG_ON_;
  370. smsc95xx_write_reg(udev, TX_CFG, reg_val);
  371. }
  372. /* Starts the Receive path */
  373. static void smsc95xx_start_rx_path(struct usb_device *udev,
  374. struct smsc95xx_private *priv)
  375. {
  376. priv->mac_cr |= MAC_CR_RXEN_;
  377. smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
  378. }
  379. static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
  380. struct smsc95xx_private *priv,
  381. unsigned char *enetaddr)
  382. {
  383. int ret;
  384. u32 write_buf;
  385. u32 read_buf;
  386. u32 burst_cap;
  387. int timeout;
  388. #define TIMEOUT_RESOLUTION 50 /* ms */
  389. int link_detected;
  390. debug("** %s()\n", __func__);
  391. dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
  392. write_buf = HW_CFG_LRST_;
  393. ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
  394. if (ret < 0)
  395. return ret;
  396. timeout = 0;
  397. do {
  398. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  399. if (ret < 0)
  400. return ret;
  401. udelay(10 * 1000);
  402. timeout++;
  403. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  404. if (timeout >= 100) {
  405. debug("timeout waiting for completion of Lite Reset\n");
  406. return -ETIMEDOUT;
  407. }
  408. write_buf = PM_CTL_PHY_RST_;
  409. ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
  410. if (ret < 0)
  411. return ret;
  412. timeout = 0;
  413. do {
  414. ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
  415. if (ret < 0)
  416. return ret;
  417. udelay(10 * 1000);
  418. timeout++;
  419. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  420. if (timeout >= 100) {
  421. debug("timeout waiting for PHY Reset\n");
  422. return -ETIMEDOUT;
  423. }
  424. #ifndef CONFIG_DM_ETH
  425. if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
  426. 0)
  427. priv->have_hwaddr = 1;
  428. #endif
  429. if (!priv->have_hwaddr) {
  430. puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
  431. return -EADDRNOTAVAIL;
  432. }
  433. ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
  434. if (ret < 0)
  435. return ret;
  436. #ifdef TURBO_MODE
  437. if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
  438. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  439. priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  440. } else {
  441. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  442. priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  443. }
  444. #else
  445. burst_cap = 0;
  446. priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  447. #endif
  448. debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
  449. ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
  450. if (ret < 0)
  451. return ret;
  452. ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
  453. if (ret < 0)
  454. return ret;
  455. debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
  456. read_buf = DEFAULT_BULK_IN_DELAY;
  457. ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
  458. if (ret < 0)
  459. return ret;
  460. ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
  461. if (ret < 0)
  462. return ret;
  463. debug("Read Value from BULK_IN_DLY after writing: "
  464. "0x%08x\n", read_buf);
  465. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  466. if (ret < 0)
  467. return ret;
  468. debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
  469. #ifdef TURBO_MODE
  470. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  471. #endif
  472. read_buf &= ~HW_CFG_RXDOFF_;
  473. #define NET_IP_ALIGN 0
  474. read_buf |= NET_IP_ALIGN << 9;
  475. ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
  476. if (ret < 0)
  477. return ret;
  478. ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
  479. if (ret < 0)
  480. return ret;
  481. debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  482. write_buf = 0xFFFFFFFF;
  483. ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
  484. if (ret < 0)
  485. return ret;
  486. ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
  487. if (ret < 0)
  488. return ret;
  489. debug("ID_REV = 0x%08x\n", read_buf);
  490. /* Configure GPIO pins as LED outputs */
  491. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  492. LED_GPIO_CFG_FDX_LED;
  493. ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
  494. if (ret < 0)
  495. return ret;
  496. debug("LED_GPIO_CFG set\n");
  497. /* Init Tx */
  498. write_buf = 0;
  499. ret = smsc95xx_write_reg(udev, FLOW, write_buf);
  500. if (ret < 0)
  501. return ret;
  502. read_buf = AFC_CFG_DEFAULT;
  503. ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
  504. if (ret < 0)
  505. return ret;
  506. ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
  507. if (ret < 0)
  508. return ret;
  509. /* Init Rx. Set Vlan */
  510. write_buf = (u32)ETH_P_8021Q;
  511. ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
  512. if (ret < 0)
  513. return ret;
  514. /* Disable checksum offload engines */
  515. ret = smsc95xx_set_csums(udev, 0, 0);
  516. if (ret < 0) {
  517. debug("Failed to set csum offload: %d\n", ret);
  518. return ret;
  519. }
  520. smsc95xx_set_multicast(priv);
  521. ret = smsc95xx_phy_initialize(udev, dev);
  522. if (ret < 0)
  523. return ret;
  524. ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
  525. if (ret < 0)
  526. return ret;
  527. /* enable PHY interrupts */
  528. read_buf |= INT_EP_CTL_PHY_INT_;
  529. ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
  530. if (ret < 0)
  531. return ret;
  532. smsc95xx_start_tx_path(udev, priv);
  533. smsc95xx_start_rx_path(udev, priv);
  534. timeout = 0;
  535. do {
  536. link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
  537. & BMSR_LSTATUS;
  538. if (!link_detected) {
  539. if (timeout == 0)
  540. printf("Waiting for Ethernet connection... ");
  541. udelay(TIMEOUT_RESOLUTION * 1000);
  542. timeout += TIMEOUT_RESOLUTION;
  543. }
  544. } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
  545. if (link_detected) {
  546. if (timeout != 0)
  547. printf("done.\n");
  548. } else {
  549. printf("unable to connect.\n");
  550. return -EIO;
  551. }
  552. return 0;
  553. }
  554. static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
  555. {
  556. int err;
  557. int actual_len;
  558. u32 tx_cmd_a;
  559. u32 tx_cmd_b;
  560. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
  561. PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
  562. debug("** %s(), len %d, buf %#x\n", __func__, length,
  563. (unsigned int)(ulong)msg);
  564. if (length > PKTSIZE)
  565. return -ENOSPC;
  566. tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  567. tx_cmd_b = (u32)length;
  568. cpu_to_le32s(&tx_cmd_a);
  569. cpu_to_le32s(&tx_cmd_b);
  570. /* prepend cmd_a and cmd_b */
  571. memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
  572. memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
  573. memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
  574. length);
  575. err = usb_bulk_msg(dev->pusb_dev,
  576. usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
  577. (void *)msg,
  578. length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
  579. &actual_len,
  580. USB_BULK_SEND_TIMEOUT);
  581. debug("Tx: len = %u, actual = %u, err = %d\n",
  582. (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)),
  583. (unsigned int)actual_len, err);
  584. return err;
  585. }
  586. #ifndef CONFIG_DM_ETH
  587. /*
  588. * Smsc95xx callbacks
  589. */
  590. static int smsc95xx_init(struct eth_device *eth, struct bd_info *bd)
  591. {
  592. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  593. struct usb_device *udev = dev->pusb_dev;
  594. struct smsc95xx_private *priv =
  595. (struct smsc95xx_private *)dev->dev_priv;
  596. return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
  597. }
  598. static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
  599. {
  600. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  601. return smsc95xx_send_common(dev, packet, length);
  602. }
  603. static int smsc95xx_recv(struct eth_device *eth)
  604. {
  605. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  606. DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
  607. unsigned char *buf_ptr;
  608. int err;
  609. int actual_len;
  610. u32 packet_len;
  611. int cur_buf_align;
  612. debug("** %s()\n", __func__);
  613. err = usb_bulk_msg(dev->pusb_dev,
  614. usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
  615. (void *)recv_buf, RX_URB_SIZE, &actual_len,
  616. USB_BULK_RECV_TIMEOUT);
  617. debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
  618. actual_len, err);
  619. if (err != 0) {
  620. debug("Rx: failed to receive\n");
  621. return -err;
  622. }
  623. if (actual_len > RX_URB_SIZE) {
  624. debug("Rx: received too many bytes %d\n", actual_len);
  625. return -ENOSPC;
  626. }
  627. buf_ptr = recv_buf;
  628. while (actual_len > 0) {
  629. /*
  630. * 1st 4 bytes contain the length of the actual data plus error
  631. * info. Extract data length.
  632. */
  633. if (actual_len < sizeof(packet_len)) {
  634. debug("Rx: incomplete packet length\n");
  635. return -EIO;
  636. }
  637. memcpy(&packet_len, buf_ptr, sizeof(packet_len));
  638. le32_to_cpus(&packet_len);
  639. if (packet_len & RX_STS_ES_) {
  640. debug("Rx: Error header=%#x", packet_len);
  641. return -EIO;
  642. }
  643. packet_len = ((packet_len & RX_STS_FL_) >> 16);
  644. if (packet_len > actual_len - sizeof(packet_len)) {
  645. debug("Rx: too large packet: %d\n", packet_len);
  646. return -EIO;
  647. }
  648. /* Notify net stack */
  649. net_process_received_packet(buf_ptr + sizeof(packet_len),
  650. packet_len - 4);
  651. /* Adjust for next iteration */
  652. actual_len -= sizeof(packet_len) + packet_len;
  653. buf_ptr += sizeof(packet_len) + packet_len;
  654. cur_buf_align = (ulong)buf_ptr - (ulong)recv_buf;
  655. if (cur_buf_align & 0x03) {
  656. int align = 4 - (cur_buf_align & 0x03);
  657. actual_len -= align;
  658. buf_ptr += align;
  659. }
  660. }
  661. return err;
  662. }
  663. static void smsc95xx_halt(struct eth_device *eth)
  664. {
  665. debug("** %s()\n", __func__);
  666. }
  667. static int smsc95xx_write_hwaddr(struct eth_device *eth)
  668. {
  669. struct ueth_data *dev = eth->priv;
  670. struct usb_device *udev = dev->pusb_dev;
  671. struct smsc95xx_private *priv = dev->dev_priv;
  672. return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
  673. }
  674. /*
  675. * SMSC probing functions
  676. */
  677. void smsc95xx_eth_before_probe(void)
  678. {
  679. curr_eth_dev = 0;
  680. }
  681. struct smsc95xx_dongle {
  682. unsigned short vendor;
  683. unsigned short product;
  684. };
  685. static const struct smsc95xx_dongle smsc95xx_dongles[] = {
  686. { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
  687. { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
  688. { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
  689. { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
  690. { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
  691. { 0x0000, 0x0000 } /* END - Do not remove */
  692. };
  693. /* Probe to see if a new device is actually an SMSC device */
  694. int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
  695. struct ueth_data *ss)
  696. {
  697. struct usb_interface *iface;
  698. struct usb_interface_descriptor *iface_desc;
  699. int i;
  700. /* let's examine the device now */
  701. iface = &dev->config.if_desc[ifnum];
  702. iface_desc = &dev->config.if_desc[ifnum].desc;
  703. for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
  704. if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
  705. dev->descriptor.idProduct == smsc95xx_dongles[i].product)
  706. /* Found a supported dongle */
  707. break;
  708. }
  709. if (smsc95xx_dongles[i].vendor == 0)
  710. return 0;
  711. /* At this point, we know we've got a live one */
  712. debug("\n\nUSB Ethernet device detected\n");
  713. memset(ss, '\0', sizeof(struct ueth_data));
  714. /* Initialize the ueth_data structure with some useful info */
  715. ss->ifnum = ifnum;
  716. ss->pusb_dev = dev;
  717. ss->subclass = iface_desc->bInterfaceSubClass;
  718. ss->protocol = iface_desc->bInterfaceProtocol;
  719. /*
  720. * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
  721. * We will ignore any others.
  722. */
  723. for (i = 0; i < iface_desc->bNumEndpoints; i++) {
  724. /* is it an BULK endpoint? */
  725. if ((iface->ep_desc[i].bmAttributes &
  726. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
  727. if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
  728. ss->ep_in =
  729. iface->ep_desc[i].bEndpointAddress &
  730. USB_ENDPOINT_NUMBER_MASK;
  731. else
  732. ss->ep_out =
  733. iface->ep_desc[i].bEndpointAddress &
  734. USB_ENDPOINT_NUMBER_MASK;
  735. }
  736. /* is it an interrupt endpoint? */
  737. if ((iface->ep_desc[i].bmAttributes &
  738. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
  739. ss->ep_int = iface->ep_desc[i].bEndpointAddress &
  740. USB_ENDPOINT_NUMBER_MASK;
  741. ss->irqinterval = iface->ep_desc[i].bInterval;
  742. }
  743. }
  744. debug("Endpoints In %d Out %d Int %d\n",
  745. ss->ep_in, ss->ep_out, ss->ep_int);
  746. /* Do some basic sanity checks, and bail if we find a problem */
  747. if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
  748. !ss->ep_in || !ss->ep_out || !ss->ep_int) {
  749. debug("Problems with device\n");
  750. return 0;
  751. }
  752. dev->privptr = (void *)ss;
  753. /* alloc driver private */
  754. ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
  755. if (!ss->dev_priv)
  756. return 0;
  757. return 1;
  758. }
  759. int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
  760. struct eth_device *eth)
  761. {
  762. debug("** %s()\n", __func__);
  763. if (!eth) {
  764. debug("%s: missing parameter.\n", __func__);
  765. return 0;
  766. }
  767. sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
  768. eth->init = smsc95xx_init;
  769. eth->send = smsc95xx_send;
  770. eth->recv = smsc95xx_recv;
  771. eth->halt = smsc95xx_halt;
  772. eth->write_hwaddr = smsc95xx_write_hwaddr;
  773. eth->priv = ss;
  774. return 1;
  775. }
  776. #endif /* !CONFIG_DM_ETH */
  777. #ifdef CONFIG_DM_ETH
  778. static int smsc95xx_eth_start(struct udevice *dev)
  779. {
  780. struct usb_device *udev = dev_get_parent_priv(dev);
  781. struct smsc95xx_private *priv = dev_get_priv(dev);
  782. struct eth_pdata *pdata = dev_get_platdata(dev);
  783. /* Driver-model Ethernet ensures we have this */
  784. priv->have_hwaddr = 1;
  785. return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr);
  786. }
  787. void smsc95xx_eth_stop(struct udevice *dev)
  788. {
  789. debug("** %s()\n", __func__);
  790. }
  791. int smsc95xx_eth_send(struct udevice *dev, void *packet, int length)
  792. {
  793. struct smsc95xx_private *priv = dev_get_priv(dev);
  794. return smsc95xx_send_common(&priv->ueth, packet, length);
  795. }
  796. int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  797. {
  798. struct smsc95xx_private *priv = dev_get_priv(dev);
  799. struct ueth_data *ueth = &priv->ueth;
  800. uint8_t *ptr;
  801. int ret, len;
  802. u32 packet_len;
  803. len = usb_ether_get_rx_bytes(ueth, &ptr);
  804. debug("%s: first try, len=%d\n", __func__, len);
  805. if (!len) {
  806. if (!(flags & ETH_RECV_CHECK_DEVICE))
  807. return -EAGAIN;
  808. ret = usb_ether_receive(ueth, RX_URB_SIZE);
  809. if (ret == -EAGAIN)
  810. return ret;
  811. len = usb_ether_get_rx_bytes(ueth, &ptr);
  812. debug("%s: second try, len=%d\n", __func__, len);
  813. }
  814. /*
  815. * 1st 4 bytes contain the length of the actual data plus error info.
  816. * Extract data length.
  817. */
  818. if (len < sizeof(packet_len)) {
  819. debug("Rx: incomplete packet length\n");
  820. goto err;
  821. }
  822. memcpy(&packet_len, ptr, sizeof(packet_len));
  823. le32_to_cpus(&packet_len);
  824. if (packet_len & RX_STS_ES_) {
  825. debug("Rx: Error header=%#x", packet_len);
  826. goto err;
  827. }
  828. packet_len = ((packet_len & RX_STS_FL_) >> 16);
  829. if (packet_len > len - sizeof(packet_len)) {
  830. debug("Rx: too large packet: %d\n", packet_len);
  831. goto err;
  832. }
  833. *packetp = ptr + sizeof(packet_len);
  834. return packet_len - 4;
  835. err:
  836. usb_ether_advance_rxbuf(ueth, -1);
  837. return -EINVAL;
  838. }
  839. static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
  840. {
  841. struct smsc95xx_private *priv = dev_get_priv(dev);
  842. packet_len = ALIGN(packet_len + sizeof(u32), 4);
  843. usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
  844. return 0;
  845. }
  846. int smsc95xx_write_hwaddr(struct udevice *dev)
  847. {
  848. struct usb_device *udev = dev_get_parent_priv(dev);
  849. struct eth_pdata *pdata = dev_get_platdata(dev);
  850. struct smsc95xx_private *priv = dev_get_priv(dev);
  851. return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr);
  852. }
  853. int smsc95xx_read_rom_hwaddr(struct udevice *dev)
  854. {
  855. struct usb_device *udev = dev_get_parent_priv(dev);
  856. struct eth_pdata *pdata = dev_get_platdata(dev);
  857. int ret;
  858. ret = smsc95xx_init_mac_address(pdata->enetaddr, udev);
  859. if (ret)
  860. memset(pdata->enetaddr, 0, 6);
  861. return 0;
  862. }
  863. static int smsc95xx_eth_probe(struct udevice *dev)
  864. {
  865. struct smsc95xx_private *priv = dev_get_priv(dev);
  866. struct ueth_data *ueth = &priv->ueth;
  867. return usb_ether_register(dev, ueth, RX_URB_SIZE);
  868. }
  869. static const struct eth_ops smsc95xx_eth_ops = {
  870. .start = smsc95xx_eth_start,
  871. .send = smsc95xx_eth_send,
  872. .recv = smsc95xx_eth_recv,
  873. .free_pkt = smsc95xx_free_pkt,
  874. .stop = smsc95xx_eth_stop,
  875. .write_hwaddr = smsc95xx_write_hwaddr,
  876. .read_rom_hwaddr = smsc95xx_read_rom_hwaddr,
  877. };
  878. U_BOOT_DRIVER(smsc95xx_eth) = {
  879. .name = "smsc95xx_eth",
  880. .id = UCLASS_ETH,
  881. .probe = smsc95xx_eth_probe,
  882. .ops = &smsc95xx_eth_ops,
  883. .priv_auto_alloc_size = sizeof(struct smsc95xx_private),
  884. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  885. };
  886. static const struct usb_device_id smsc95xx_eth_id_table[] = {
  887. { USB_DEVICE(0x05ac, 0x1402) },
  888. { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */
  889. { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */
  890. { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */
  891. { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */
  892. { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */
  893. { } /* Terminating entry */
  894. };
  895. U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);
  896. #endif