r8152.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <memalign.h>
  12. #include <net.h>
  13. #include <usb.h>
  14. #include <linux/delay.h>
  15. #include <linux/mii.h>
  16. #include <linux/bitops.h>
  17. #include "usb_ether.h"
  18. #include "r8152.h"
  19. #ifndef CONFIG_DM_ETH
  20. /* local vars */
  21. static int curr_eth_dev; /* index for name of next device detected */
  22. struct r8152_dongle {
  23. unsigned short vendor;
  24. unsigned short product;
  25. };
  26. static const struct r8152_dongle r8152_dongles[] = {
  27. /* Realtek */
  28. { 0x0bda, 0x8050 },
  29. { 0x0bda, 0x8152 },
  30. { 0x0bda, 0x8153 },
  31. /* Samsung */
  32. { 0x04e8, 0xa101 },
  33. /* Lenovo */
  34. { 0x17ef, 0x304f },
  35. { 0x17ef, 0x3052 },
  36. { 0x17ef, 0x3054 },
  37. { 0x17ef, 0x3057 },
  38. { 0x17ef, 0x7205 },
  39. { 0x17ef, 0x720a },
  40. { 0x17ef, 0x720b },
  41. { 0x17ef, 0x720c },
  42. /* TP-LINK */
  43. { 0x2357, 0x0601 },
  44. /* Nvidia */
  45. { 0x0955, 0x09ff },
  46. };
  47. #endif
  48. struct r8152_version {
  49. unsigned short tcr;
  50. unsigned short version;
  51. bool gmii;
  52. };
  53. static const struct r8152_version r8152_versions[] = {
  54. { 0x4c00, RTL_VER_01, 0 },
  55. { 0x4c10, RTL_VER_02, 0 },
  56. { 0x5c00, RTL_VER_03, 1 },
  57. { 0x5c10, RTL_VER_04, 1 },
  58. { 0x5c20, RTL_VER_05, 1 },
  59. { 0x5c30, RTL_VER_06, 1 },
  60. { 0x4800, RTL_VER_07, 0 },
  61. { 0x6000, RTL_VER_08, 1 },
  62. { 0x6010, RTL_VER_09, 1 },
  63. };
  64. static
  65. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  66. {
  67. ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
  68. int ret;
  69. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  70. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  71. value, index, tmp, size, 500);
  72. memcpy(data, tmp, size);
  73. return ret;
  74. }
  75. static
  76. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  77. {
  78. ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size);
  79. memcpy(tmp, data, size);
  80. return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  81. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  82. value, index, tmp, size, 500);
  83. }
  84. int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  85. void *data, u16 type)
  86. {
  87. u16 burst_size = 64;
  88. int ret;
  89. int txsize;
  90. /* both size and index must be 4 bytes align */
  91. if ((size & 3) || !size || (index & 3) || !data)
  92. return -EINVAL;
  93. if (index + size > 0xffff)
  94. return -EINVAL;
  95. while (size) {
  96. txsize = min(size, burst_size);
  97. ret = get_registers(tp, index, type, txsize, data);
  98. if (ret < 0)
  99. break;
  100. index += txsize;
  101. data += txsize;
  102. size -= txsize;
  103. }
  104. return ret;
  105. }
  106. int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  107. u16 size, void *data, u16 type)
  108. {
  109. int ret;
  110. u16 byteen_start, byteen_end, byte_en_to_hw;
  111. u16 burst_size = 512;
  112. int txsize;
  113. /* both size and index must be 4 bytes align */
  114. if ((size & 3) || !size || (index & 3) || !data)
  115. return -EINVAL;
  116. if (index + size > 0xffff)
  117. return -EINVAL;
  118. byteen_start = byteen & BYTE_EN_START_MASK;
  119. byteen_end = byteen & BYTE_EN_END_MASK;
  120. byte_en_to_hw = byteen_start | (byteen_start << 4);
  121. ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
  122. if (ret < 0)
  123. return ret;
  124. index += 4;
  125. data += 4;
  126. size -= 4;
  127. if (size) {
  128. size -= 4;
  129. while (size) {
  130. txsize = min(size, burst_size);
  131. ret = set_registers(tp, index,
  132. type | BYTE_EN_DWORD,
  133. txsize, data);
  134. if (ret < 0)
  135. return ret;
  136. index += txsize;
  137. data += txsize;
  138. size -= txsize;
  139. }
  140. byte_en_to_hw = byteen_end | (byteen_end >> 4);
  141. ret = set_registers(tp, index, type | byte_en_to_hw, 4, data);
  142. if (ret < 0)
  143. return ret;
  144. }
  145. return ret;
  146. }
  147. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  148. {
  149. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  150. }
  151. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  152. {
  153. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  154. }
  155. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  156. {
  157. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  158. }
  159. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  160. {
  161. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  162. }
  163. u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  164. {
  165. __le32 data;
  166. generic_ocp_read(tp, index, sizeof(data), &data, type);
  167. return __le32_to_cpu(data);
  168. }
  169. void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  170. {
  171. __le32 tmp = __cpu_to_le32(data);
  172. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  173. }
  174. u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  175. {
  176. u32 data;
  177. __le32 tmp;
  178. u8 shift = index & 2;
  179. index &= ~3;
  180. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  181. data = __le32_to_cpu(tmp);
  182. data >>= (shift * 8);
  183. data &= 0xffff;
  184. return data;
  185. }
  186. void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  187. {
  188. u32 mask = 0xffff;
  189. __le32 tmp;
  190. u16 byen = BYTE_EN_WORD;
  191. u8 shift = index & 2;
  192. data &= mask;
  193. if (index & 2) {
  194. byen <<= shift;
  195. mask <<= (shift * 8);
  196. data <<= (shift * 8);
  197. index &= ~3;
  198. }
  199. tmp = __cpu_to_le32(data);
  200. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  201. }
  202. u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  203. {
  204. u32 data;
  205. __le32 tmp;
  206. u8 shift = index & 3;
  207. index &= ~3;
  208. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  209. data = __le32_to_cpu(tmp);
  210. data >>= (shift * 8);
  211. data &= 0xff;
  212. return data;
  213. }
  214. void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  215. {
  216. u32 mask = 0xff;
  217. __le32 tmp;
  218. u16 byen = BYTE_EN_BYTE;
  219. u8 shift = index & 3;
  220. data &= mask;
  221. if (index & 3) {
  222. byen <<= shift;
  223. mask <<= (shift * 8);
  224. data <<= (shift * 8);
  225. index &= ~3;
  226. }
  227. tmp = __cpu_to_le32(data);
  228. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  229. }
  230. u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  231. {
  232. u16 ocp_base, ocp_index;
  233. ocp_base = addr & 0xf000;
  234. if (ocp_base != tp->ocp_base) {
  235. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  236. tp->ocp_base = ocp_base;
  237. }
  238. ocp_index = (addr & 0x0fff) | 0xb000;
  239. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  240. }
  241. void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  242. {
  243. u16 ocp_base, ocp_index;
  244. ocp_base = addr & 0xf000;
  245. if (ocp_base != tp->ocp_base) {
  246. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  247. tp->ocp_base = ocp_base;
  248. }
  249. ocp_index = (addr & 0x0fff) | 0xb000;
  250. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  251. }
  252. static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  253. {
  254. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  255. }
  256. static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  257. {
  258. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  259. }
  260. void sram_write(struct r8152 *tp, u16 addr, u16 data)
  261. {
  262. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  263. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  264. }
  265. static u16 sram_read(struct r8152 *tp, u16 addr)
  266. {
  267. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  268. return ocp_reg_read(tp, OCP_SRAM_DATA);
  269. }
  270. int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index,
  271. const u32 mask, bool set, unsigned int timeout)
  272. {
  273. u32 val;
  274. while (--timeout) {
  275. if (ocp_reg)
  276. val = ocp_reg_read(tp, index);
  277. else
  278. val = ocp_read_dword(tp, type, index);
  279. if (!set)
  280. val = ~val;
  281. if ((val & mask) == mask)
  282. return 0;
  283. mdelay(1);
  284. }
  285. debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n",
  286. __func__, index, mask, timeout);
  287. return -ETIMEDOUT;
  288. }
  289. static void r8152b_reset_packet_filter(struct r8152 *tp)
  290. {
  291. u32 ocp_data;
  292. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  293. ocp_data &= ~FMC_FCR_MCU_EN;
  294. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  295. ocp_data |= FMC_FCR_MCU_EN;
  296. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  297. }
  298. static void rtl8152_wait_fifo_empty(struct r8152 *tp)
  299. {
  300. int ret;
  301. ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
  302. PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT);
  303. if (ret)
  304. debug("Timeout waiting for FIFO empty\n");
  305. ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0,
  306. TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT);
  307. if (ret)
  308. debug("Timeout waiting for TX empty\n");
  309. }
  310. static void rtl8152_nic_reset(struct r8152 *tp)
  311. {
  312. int ret;
  313. u32 ocp_data;
  314. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL);
  315. ocp_data |= BIST_CTRL_SW_RESET;
  316. ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data);
  317. ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL,
  318. BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT);
  319. if (ret)
  320. debug("Timeout waiting for NIC reset\n");
  321. }
  322. static u8 rtl8152_get_speed(struct r8152 *tp)
  323. {
  324. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  325. }
  326. static void rtl_set_eee_plus(struct r8152 *tp)
  327. {
  328. u32 ocp_data;
  329. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  330. ocp_data &= ~EEEP_CR_EEEP_TX;
  331. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  332. }
  333. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  334. {
  335. u32 ocp_data;
  336. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  337. if (enable)
  338. ocp_data |= RXDY_GATED_EN;
  339. else
  340. ocp_data &= ~RXDY_GATED_EN;
  341. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  342. }
  343. static void rtl8152_set_rx_mode(struct r8152 *tp)
  344. {
  345. u32 ocp_data;
  346. __le32 tmp[2];
  347. tmp[0] = 0xffffffff;
  348. tmp[1] = 0xffffffff;
  349. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  350. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  351. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  352. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  353. }
  354. static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
  355. {
  356. ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
  357. OWN_UPDATE | OWN_CLEAR);
  358. }
  359. static int rtl_enable(struct r8152 *tp)
  360. {
  361. u32 ocp_data;
  362. r8152b_reset_packet_filter(tp);
  363. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  364. ocp_data |= PLA_CR_RE | PLA_CR_TE;
  365. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  366. switch (tp->version) {
  367. case RTL_VER_08:
  368. case RTL_VER_09:
  369. r8153b_rx_agg_chg_indicate(tp);
  370. break;
  371. default:
  372. break;
  373. }
  374. rxdy_gated_en(tp, false);
  375. rtl8152_set_rx_mode(tp);
  376. return 0;
  377. }
  378. static int rtl8152_enable(struct r8152 *tp)
  379. {
  380. rtl_set_eee_plus(tp);
  381. return rtl_enable(tp);
  382. }
  383. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  384. {
  385. u32 ocp_data = tp->coalesce / 8;
  386. switch (tp->version) {
  387. case RTL_VER_03:
  388. case RTL_VER_04:
  389. case RTL_VER_05:
  390. case RTL_VER_06:
  391. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
  392. ocp_data);
  393. break;
  394. case RTL_VER_08:
  395. case RTL_VER_09:
  396. /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
  397. * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 1264ns.
  398. */
  399. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
  400. RX_AUXILIARY_TIMER / 8);
  401. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
  402. ocp_data);
  403. break;
  404. default:
  405. debug("** %s Invalid Device\n", __func__);
  406. break;
  407. }
  408. }
  409. static void r8153_set_rx_early_size(struct r8152 *tp)
  410. {
  411. u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS -
  412. sizeof(struct rx_desc));
  413. switch (tp->version) {
  414. case RTL_VER_03:
  415. case RTL_VER_04:
  416. case RTL_VER_05:
  417. case RTL_VER_06:
  418. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
  419. ocp_data / 4);
  420. break;
  421. case RTL_VER_08:
  422. case RTL_VER_09:
  423. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
  424. ocp_data / 8);
  425. break;
  426. default:
  427. debug("** %s Invalid Device\n", __func__);
  428. break;
  429. }
  430. }
  431. static int rtl8153_enable(struct r8152 *tp)
  432. {
  433. rtl_set_eee_plus(tp);
  434. r8153_set_rx_early_timeout(tp);
  435. r8153_set_rx_early_size(tp);
  436. return rtl_enable(tp);
  437. }
  438. static void rtl_disable(struct r8152 *tp)
  439. {
  440. u32 ocp_data;
  441. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  442. ocp_data &= ~RCR_ACPT_ALL;
  443. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  444. rxdy_gated_en(tp, true);
  445. rtl8152_wait_fifo_empty(tp);
  446. rtl8152_nic_reset(tp);
  447. }
  448. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  449. {
  450. u32 ocp_data;
  451. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  452. if (enable)
  453. ocp_data |= POWER_CUT;
  454. else
  455. ocp_data &= ~POWER_CUT;
  456. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  457. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  458. ocp_data &= ~RESUME_INDICATE;
  459. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  460. }
  461. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  462. {
  463. u32 ocp_data;
  464. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  465. if (enable)
  466. ocp_data |= CPCR_RX_VLAN;
  467. else
  468. ocp_data &= ~CPCR_RX_VLAN;
  469. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  470. }
  471. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  472. {
  473. u8 u1u2[8];
  474. if (enable)
  475. memset(u1u2, 0xff, sizeof(u1u2));
  476. else
  477. memset(u1u2, 0x00, sizeof(u1u2));
  478. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  479. }
  480. static void r8153b_u1u2en(struct r8152 *tp, bool enable)
  481. {
  482. u16 ocp_data;
  483. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
  484. if (enable)
  485. ocp_data |= LPM_U1U2_EN;
  486. else
  487. ocp_data &= ~LPM_U1U2_EN;
  488. ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
  489. }
  490. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  491. {
  492. u32 ocp_data;
  493. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  494. if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
  495. ocp_data |= U2P3_ENABLE;
  496. else
  497. ocp_data &= ~U2P3_ENABLE;
  498. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  499. }
  500. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  501. {
  502. u32 ocp_data;
  503. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  504. if (enable)
  505. ocp_data |= PWR_EN | PHASE2_EN;
  506. else
  507. ocp_data &= ~(PWR_EN | PHASE2_EN);
  508. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  509. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  510. ocp_data &= ~PCUT_STATUS;
  511. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  512. }
  513. static void rtl_reset_bmu(struct r8152 *tp)
  514. {
  515. u8 ocp_data;
  516. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
  517. ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
  518. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  519. ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
  520. ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  521. }
  522. static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr)
  523. {
  524. int ret;
  525. unsigned char enetaddr[8] = {0};
  526. ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr);
  527. if (ret < 0)
  528. return ret;
  529. memcpy(macaddr, enetaddr, ETH_ALEN);
  530. return 0;
  531. }
  532. static void r8152b_disable_aldps(struct r8152 *tp)
  533. {
  534. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  535. mdelay(20);
  536. }
  537. static void r8152b_enable_aldps(struct r8152 *tp)
  538. {
  539. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  540. LINKENA | DIS_SDSAVE);
  541. }
  542. static void rtl8152_disable(struct r8152 *tp)
  543. {
  544. r8152b_disable_aldps(tp);
  545. rtl_disable(tp);
  546. r8152b_enable_aldps(tp);
  547. }
  548. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  549. {
  550. u16 data;
  551. data = r8152_mdio_read(tp, MII_BMCR);
  552. if (data & BMCR_PDOWN) {
  553. data &= ~BMCR_PDOWN;
  554. r8152_mdio_write(tp, MII_BMCR, data);
  555. }
  556. r8152b_firmware(tp);
  557. }
  558. static void rtl8152_reinit_ll(struct r8152 *tp)
  559. {
  560. u32 ocp_data;
  561. int ret;
  562. ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
  563. PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
  564. if (ret)
  565. debug("Timeout waiting for link list ready\n");
  566. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  567. ocp_data |= RE_INIT_LL;
  568. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  569. ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR,
  570. PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT);
  571. if (ret)
  572. debug("Timeout waiting for link list ready\n");
  573. }
  574. static void r8152b_exit_oob(struct r8152 *tp)
  575. {
  576. u32 ocp_data;
  577. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  578. ocp_data &= ~RCR_ACPT_ALL;
  579. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  580. rxdy_gated_en(tp, true);
  581. r8152b_hw_phy_cfg(tp);
  582. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  583. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  584. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  585. ocp_data &= ~NOW_IS_OOB;
  586. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  587. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  588. ocp_data &= ~MCU_BORW_EN;
  589. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  590. rtl8152_reinit_ll(tp);
  591. rtl8152_nic_reset(tp);
  592. /* rx share fifo credit full threshold */
  593. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  594. if (tp->udev->speed == USB_SPEED_FULL ||
  595. tp->udev->speed == USB_SPEED_LOW) {
  596. /* rx share fifo credit near full threshold */
  597. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  598. RXFIFO_THR2_FULL);
  599. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  600. RXFIFO_THR3_FULL);
  601. } else {
  602. /* rx share fifo credit near full threshold */
  603. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  604. RXFIFO_THR2_HIGH);
  605. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  606. RXFIFO_THR3_HIGH);
  607. }
  608. /* TX share fifo free credit full threshold */
  609. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  610. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  611. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  612. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  613. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  614. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  615. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  616. ocp_data |= TCR0_AUTO_FIFO;
  617. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  618. }
  619. static void r8152b_enter_oob(struct r8152 *tp)
  620. {
  621. u32 ocp_data;
  622. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  623. ocp_data &= ~NOW_IS_OOB;
  624. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  625. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  626. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  627. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  628. rtl_disable(tp);
  629. rtl8152_reinit_ll(tp);
  630. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  631. rtl_rx_vlan_en(tp, false);
  632. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
  633. ocp_data |= ALDPS_PROXY_MODE;
  634. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
  635. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  636. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  637. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  638. rxdy_gated_en(tp, false);
  639. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  640. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  641. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  642. }
  643. static void r8153_hw_phy_cfg(struct r8152 *tp)
  644. {
  645. u32 ocp_data;
  646. u16 data;
  647. if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
  648. tp->version == RTL_VER_05)
  649. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  650. data = r8152_mdio_read(tp, MII_BMCR);
  651. if (data & BMCR_PDOWN) {
  652. data &= ~BMCR_PDOWN;
  653. r8152_mdio_write(tp, MII_BMCR, data);
  654. }
  655. r8153_firmware(tp);
  656. if (tp->version == RTL_VER_03) {
  657. data = ocp_reg_read(tp, OCP_EEE_CFG);
  658. data &= ~CTAP_SHORT_EN;
  659. ocp_reg_write(tp, OCP_EEE_CFG, data);
  660. }
  661. data = ocp_reg_read(tp, OCP_POWER_CFG);
  662. data |= EEE_CLKDIV_EN;
  663. ocp_reg_write(tp, OCP_POWER_CFG, data);
  664. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  665. data |= EN_10M_BGOFF;
  666. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  667. data = ocp_reg_read(tp, OCP_POWER_CFG);
  668. data |= EN_10M_PLLOFF;
  669. ocp_reg_write(tp, OCP_POWER_CFG, data);
  670. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  671. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  672. ocp_data |= PFM_PWM_SWITCH;
  673. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  674. /* Enable LPF corner auto tune */
  675. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  676. /* Adjust 10M Amplitude */
  677. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  678. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  679. }
  680. static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
  681. {
  682. u32 ocp_data;
  683. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
  684. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
  685. ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
  686. ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
  687. return ocp_data;
  688. }
  689. static void r8153b_hw_phy_cfg(struct r8152 *tp)
  690. {
  691. u32 ocp_data;
  692. u16 data;
  693. data = r8152_mdio_read(tp, MII_BMCR);
  694. if (data & BMCR_PDOWN) {
  695. data &= ~BMCR_PDOWN;
  696. r8152_mdio_write(tp, MII_BMCR, data);
  697. }
  698. /* U1/U2/L1 idle timer. 500 us */
  699. ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
  700. r8153b_firmware(tp);
  701. data = sram_read(tp, SRAM_GREEN_CFG);
  702. data |= R_TUNE_EN;
  703. sram_write(tp, SRAM_GREEN_CFG, data);
  704. data = ocp_reg_read(tp, OCP_NCTL_CFG);
  705. data |= PGA_RETURN_EN;
  706. ocp_reg_write(tp, OCP_NCTL_CFG, data);
  707. /* ADC Bias Calibration:
  708. * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
  709. * bit (bit3) to rebuild the real 16-bit data. Write the data to the
  710. * ADC ioffset.
  711. */
  712. ocp_data = r8152_efuse_read(tp, 0x7d);
  713. ocp_data = ((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7);
  714. if (ocp_data != 0xffff)
  715. ocp_reg_write(tp, OCP_ADC_IOFFSET, ocp_data);
  716. /* ups mode tx-link-pulse timing adjustment:
  717. * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
  718. * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
  719. */
  720. ocp_data = ocp_reg_read(tp, 0xc426);
  721. ocp_data &= 0x3fff;
  722. if (ocp_data) {
  723. u32 swr_cnt_1ms_ini;
  724. swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
  725. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
  726. ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
  727. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
  728. }
  729. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  730. ocp_data |= PFM_PWM_SWITCH;
  731. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  732. }
  733. static void r8153_first_init(struct r8152 *tp)
  734. {
  735. u32 ocp_data;
  736. rxdy_gated_en(tp, true);
  737. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  738. ocp_data &= ~RCR_ACPT_ALL;
  739. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  740. r8153_hw_phy_cfg(tp);
  741. rtl8152_nic_reset(tp);
  742. rtl_reset_bmu(tp);
  743. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  744. ocp_data &= ~NOW_IS_OOB;
  745. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  746. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  747. ocp_data &= ~MCU_BORW_EN;
  748. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  749. rtl8152_reinit_ll(tp);
  750. rtl_rx_vlan_en(tp, false);
  751. ocp_data = RTL8153_RMS;
  752. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
  753. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  754. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  755. ocp_data |= TCR0_AUTO_FIFO;
  756. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  757. rtl8152_nic_reset(tp);
  758. /* rx share fifo credit full threshold */
  759. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  760. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  761. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  762. /* TX share fifo free credit full threshold */
  763. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  764. /* rx aggregation */
  765. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  766. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  767. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  768. }
  769. static void r8153_enter_oob(struct r8152 *tp)
  770. {
  771. u32 ocp_data;
  772. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  773. ocp_data &= ~NOW_IS_OOB;
  774. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  775. rtl_disable(tp);
  776. rtl_reset_bmu(tp);
  777. rtl8152_reinit_ll(tp);
  778. ocp_data = RTL8153_RMS;
  779. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
  780. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  781. ocp_data &= ~TEREDO_WAKE_MASK;
  782. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  783. rtl_rx_vlan_en(tp, false);
  784. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
  785. ocp_data |= ALDPS_PROXY_MODE;
  786. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
  787. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  788. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  789. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  790. rxdy_gated_en(tp, false);
  791. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  792. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  793. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  794. }
  795. static void r8153_disable_aldps(struct r8152 *tp)
  796. {
  797. u16 data;
  798. data = ocp_reg_read(tp, OCP_POWER_CFG);
  799. data &= ~EN_ALDPS;
  800. ocp_reg_write(tp, OCP_POWER_CFG, data);
  801. mdelay(20);
  802. }
  803. static void rtl8153_disable(struct r8152 *tp)
  804. {
  805. r8153_disable_aldps(tp);
  806. rtl_disable(tp);
  807. rtl_reset_bmu(tp);
  808. }
  809. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  810. {
  811. u16 bmcr, anar, gbcr;
  812. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  813. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  814. ADVERTISE_100HALF | ADVERTISE_100FULL);
  815. if (tp->supports_gmii) {
  816. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  817. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  818. } else {
  819. gbcr = 0;
  820. }
  821. if (autoneg == AUTONEG_DISABLE) {
  822. if (speed == SPEED_10) {
  823. bmcr = 0;
  824. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  825. } else if (speed == SPEED_100) {
  826. bmcr = BMCR_SPEED100;
  827. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  828. } else if (speed == SPEED_1000 && tp->supports_gmii) {
  829. bmcr = BMCR_SPEED1000;
  830. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  831. } else {
  832. return -EINVAL;
  833. }
  834. if (duplex == DUPLEX_FULL)
  835. bmcr |= BMCR_FULLDPLX;
  836. } else {
  837. if (speed == SPEED_10) {
  838. if (duplex == DUPLEX_FULL)
  839. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  840. else
  841. anar |= ADVERTISE_10HALF;
  842. } else if (speed == SPEED_100) {
  843. if (duplex == DUPLEX_FULL) {
  844. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  845. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  846. } else {
  847. anar |= ADVERTISE_10HALF;
  848. anar |= ADVERTISE_100HALF;
  849. }
  850. } else if (speed == SPEED_1000 && tp->supports_gmii) {
  851. if (duplex == DUPLEX_FULL) {
  852. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  853. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  854. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  855. } else {
  856. anar |= ADVERTISE_10HALF;
  857. anar |= ADVERTISE_100HALF;
  858. gbcr |= ADVERTISE_1000HALF;
  859. }
  860. } else {
  861. return -EINVAL;
  862. }
  863. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  864. }
  865. if (tp->supports_gmii)
  866. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  867. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  868. r8152_mdio_write(tp, MII_BMCR, bmcr);
  869. return 0;
  870. }
  871. static void rtl8152_up(struct r8152 *tp)
  872. {
  873. r8152b_disable_aldps(tp);
  874. r8152b_exit_oob(tp);
  875. r8152b_enable_aldps(tp);
  876. }
  877. static void rtl8152_down(struct r8152 *tp)
  878. {
  879. r8152_power_cut_en(tp, false);
  880. r8152b_disable_aldps(tp);
  881. r8152b_enter_oob(tp);
  882. r8152b_enable_aldps(tp);
  883. }
  884. static void rtl8153_up(struct r8152 *tp)
  885. {
  886. r8153_u1u2en(tp, false);
  887. r8153_disable_aldps(tp);
  888. r8153_first_init(tp);
  889. r8153_u2p3en(tp, false);
  890. }
  891. static void rtl8153_down(struct r8152 *tp)
  892. {
  893. r8153_u1u2en(tp, false);
  894. r8153_u2p3en(tp, false);
  895. r8153_power_cut_en(tp, false);
  896. r8153_disable_aldps(tp);
  897. r8153_enter_oob(tp);
  898. }
  899. static void rtl8153b_up(struct r8152 *tp)
  900. {
  901. r8153_first_init(tp);
  902. }
  903. static void rtl8153b_down(struct r8152 *tp)
  904. {
  905. r8153_enter_oob(tp);
  906. }
  907. static void r8152b_get_version(struct r8152 *tp)
  908. {
  909. u32 ocp_data;
  910. u16 tcr;
  911. int i;
  912. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  913. tcr = (u16)(ocp_data & VERSION_MASK);
  914. for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) {
  915. if (tcr == r8152_versions[i].tcr) {
  916. /* Found a supported version */
  917. tp->version = r8152_versions[i].version;
  918. tp->supports_gmii = r8152_versions[i].gmii;
  919. break;
  920. }
  921. }
  922. if (tp->version == RTL_VER_UNKNOWN)
  923. debug("r8152 Unknown tcr version 0x%04x\n", tcr);
  924. }
  925. static void r8152b_enable_fc(struct r8152 *tp)
  926. {
  927. u16 anar;
  928. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  929. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  930. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  931. }
  932. static void rtl_tally_reset(struct r8152 *tp)
  933. {
  934. u32 ocp_data;
  935. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  936. ocp_data |= TALLY_RESET;
  937. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  938. }
  939. static void r8152b_init(struct r8152 *tp)
  940. {
  941. u32 ocp_data;
  942. r8152b_disable_aldps(tp);
  943. if (tp->version == RTL_VER_01) {
  944. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  945. ocp_data &= ~LED_MODE_MASK;
  946. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  947. }
  948. r8152_power_cut_en(tp, false);
  949. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  950. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  951. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  952. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  953. ocp_data &= ~MCU_CLK_RATIO_MASK;
  954. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  955. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  956. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  957. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  958. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  959. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER);
  960. ocp_data |= BIT(15);
  961. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
  962. ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8);
  963. ocp_data &= ~BIT(15);
  964. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data);
  965. r8152b_enable_fc(tp);
  966. rtl_tally_reset(tp);
  967. /* enable rx aggregation */
  968. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  969. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  970. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  971. }
  972. static void r8153_init(struct r8152 *tp)
  973. {
  974. int i;
  975. u32 ocp_data;
  976. r8153_disable_aldps(tp);
  977. r8153_u1u2en(tp, false);
  978. r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
  979. AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
  980. for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
  981. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  982. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  983. break;
  984. mdelay(1);
  985. }
  986. r8153_u2p3en(tp, false);
  987. if (tp->version == RTL_VER_04) {
  988. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  989. ocp_data &= ~pwd_dn_scale_mask;
  990. ocp_data |= pwd_dn_scale(96);
  991. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  992. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  993. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  994. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  995. } else if (tp->version == RTL_VER_05) {
  996. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  997. ocp_data &= ~ECM_ALDPS;
  998. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  999. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  1000. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  1001. ocp_data &= ~DYNAMIC_BURST;
  1002. else
  1003. ocp_data |= DYNAMIC_BURST;
  1004. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  1005. } else if (tp->version == RTL_VER_06) {
  1006. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  1007. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  1008. ocp_data &= ~DYNAMIC_BURST;
  1009. else
  1010. ocp_data |= DYNAMIC_BURST;
  1011. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  1012. }
  1013. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  1014. ocp_data |= EP4_FULL_FC;
  1015. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  1016. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  1017. ocp_data &= ~TIMER11_EN;
  1018. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  1019. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  1020. ocp_data &= ~LED_MODE_MASK;
  1021. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  1022. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  1023. if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
  1024. ocp_data |= LPM_TIMER_500MS;
  1025. else
  1026. ocp_data |= LPM_TIMER_500US;
  1027. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  1028. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  1029. ocp_data &= ~SEN_VAL_MASK;
  1030. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  1031. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  1032. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  1033. r8153_power_cut_en(tp, false);
  1034. r8152b_enable_fc(tp);
  1035. rtl_tally_reset(tp);
  1036. }
  1037. static void r8153b_init(struct r8152 *tp)
  1038. {
  1039. u32 ocp_data;
  1040. int i;
  1041. r8153_disable_aldps(tp);
  1042. r8153b_u1u2en(tp, false);
  1043. r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL,
  1044. AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT);
  1045. for (i = 0; i < R8152_WAIT_TIMEOUT; i++) {
  1046. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  1047. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  1048. break;
  1049. mdelay(1);
  1050. }
  1051. r8153_u2p3en(tp, false);
  1052. /* MSC timer = 0xfff * 8ms = 32760 ms */
  1053. ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
  1054. r8153_power_cut_en(tp, false);
  1055. /* MAC clock speed down */
  1056. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
  1057. ocp_data |= MAC_CLK_SPDWN_EN;
  1058. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
  1059. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
  1060. ocp_data &= ~PLA_MCU_SPDWN_EN;
  1061. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
  1062. if (tp->version == RTL_VER_09) {
  1063. /* Disable Test IO for 32QFN */
  1064. if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
  1065. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  1066. ocp_data |= TEST_IO_OFF;
  1067. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  1068. }
  1069. }
  1070. /* rx aggregation */
  1071. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  1072. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  1073. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  1074. rtl_tally_reset(tp);
  1075. r8153b_hw_phy_cfg(tp);
  1076. r8152b_enable_fc(tp);
  1077. }
  1078. static void rtl8152_unload(struct r8152 *tp)
  1079. {
  1080. if (tp->version != RTL_VER_01)
  1081. r8152_power_cut_en(tp, true);
  1082. }
  1083. static void rtl8153_unload(struct r8152 *tp)
  1084. {
  1085. r8153_power_cut_en(tp, false);
  1086. }
  1087. static int rtl_ops_init(struct r8152 *tp)
  1088. {
  1089. struct rtl_ops *ops = &tp->rtl_ops;
  1090. int ret = 0;
  1091. switch (tp->version) {
  1092. case RTL_VER_01:
  1093. case RTL_VER_02:
  1094. case RTL_VER_07:
  1095. ops->init = r8152b_init;
  1096. ops->enable = rtl8152_enable;
  1097. ops->disable = rtl8152_disable;
  1098. ops->up = rtl8152_up;
  1099. ops->down = rtl8152_down;
  1100. ops->unload = rtl8152_unload;
  1101. break;
  1102. case RTL_VER_03:
  1103. case RTL_VER_04:
  1104. case RTL_VER_05:
  1105. case RTL_VER_06:
  1106. ops->init = r8153_init;
  1107. ops->enable = rtl8153_enable;
  1108. ops->disable = rtl8153_disable;
  1109. ops->up = rtl8153_up;
  1110. ops->down = rtl8153_down;
  1111. ops->unload = rtl8153_unload;
  1112. break;
  1113. case RTL_VER_08:
  1114. case RTL_VER_09:
  1115. ops->init = r8153b_init;
  1116. ops->enable = rtl8153_enable;
  1117. ops->disable = rtl8153_disable;
  1118. ops->up = rtl8153b_up;
  1119. ops->down = rtl8153b_down;
  1120. break;
  1121. default:
  1122. ret = -ENODEV;
  1123. printf("r8152 Unknown Device\n");
  1124. break;
  1125. }
  1126. return ret;
  1127. }
  1128. static int r8152_init_common(struct r8152 *tp)
  1129. {
  1130. u8 speed;
  1131. int timeout = 0;
  1132. int link_detected;
  1133. debug("** %s()\n", __func__);
  1134. do {
  1135. speed = rtl8152_get_speed(tp);
  1136. link_detected = speed & LINK_STATUS;
  1137. if (!link_detected) {
  1138. if (timeout == 0)
  1139. printf("Waiting for Ethernet connection... ");
  1140. mdelay(TIMEOUT_RESOLUTION);
  1141. timeout += TIMEOUT_RESOLUTION;
  1142. }
  1143. } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
  1144. if (link_detected) {
  1145. tp->rtl_ops.enable(tp);
  1146. if (timeout != 0)
  1147. printf("done.\n");
  1148. } else {
  1149. printf("unable to connect.\n");
  1150. }
  1151. return 0;
  1152. }
  1153. static int r8152_send_common(struct ueth_data *ueth, void *packet, int length)
  1154. {
  1155. struct usb_device *udev = ueth->pusb_dev;
  1156. u32 opts1, opts2 = 0;
  1157. int err;
  1158. int actual_len;
  1159. ALLOC_CACHE_ALIGN_BUFFER(uint8_t, msg,
  1160. PKTSIZE + sizeof(struct tx_desc));
  1161. struct tx_desc *tx_desc = (struct tx_desc *)msg;
  1162. debug("** %s(), len %d\n", __func__, length);
  1163. opts1 = length | TX_FS | TX_LS;
  1164. tx_desc->opts2 = cpu_to_le32(opts2);
  1165. tx_desc->opts1 = cpu_to_le32(opts1);
  1166. memcpy(msg + sizeof(struct tx_desc), (void *)packet, length);
  1167. err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out),
  1168. (void *)msg, length + sizeof(struct tx_desc),
  1169. &actual_len, USB_BULK_SEND_TIMEOUT);
  1170. debug("Tx: len = %zu, actual = %u, err = %d\n",
  1171. length + sizeof(struct tx_desc), actual_len, err);
  1172. return err;
  1173. }
  1174. #ifndef CONFIG_DM_ETH
  1175. static int r8152_init(struct eth_device *eth, struct bd_info *bd)
  1176. {
  1177. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  1178. struct r8152 *tp = (struct r8152 *)dev->dev_priv;
  1179. return r8152_init_common(tp);
  1180. }
  1181. static int r8152_send(struct eth_device *eth, void *packet, int length)
  1182. {
  1183. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  1184. return r8152_send_common(dev, packet, length);
  1185. }
  1186. static int r8152_recv(struct eth_device *eth)
  1187. {
  1188. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  1189. ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ);
  1190. unsigned char *pkt_ptr;
  1191. int err;
  1192. int actual_len;
  1193. u16 packet_len;
  1194. u32 bytes_process = 0;
  1195. struct rx_desc *rx_desc;
  1196. debug("** %s()\n", __func__);
  1197. err = usb_bulk_msg(dev->pusb_dev,
  1198. usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
  1199. (void *)recv_buf,
  1200. RTL8152_AGG_BUF_SZ,
  1201. &actual_len,
  1202. USB_BULK_RECV_TIMEOUT);
  1203. debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
  1204. actual_len, err);
  1205. if (err != 0) {
  1206. debug("Rx: failed to receive\n");
  1207. return -1;
  1208. }
  1209. if (actual_len > RTL8152_AGG_BUF_SZ) {
  1210. debug("Rx: received too many bytes %d\n", actual_len);
  1211. return -1;
  1212. }
  1213. while (bytes_process < actual_len) {
  1214. rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
  1215. pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
  1216. packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1217. packet_len -= CRC_SIZE;
  1218. net_process_received_packet(pkt_ptr, packet_len);
  1219. bytes_process +=
  1220. (packet_len + sizeof(struct rx_desc) + CRC_SIZE);
  1221. if (bytes_process % 8)
  1222. bytes_process = bytes_process + 8 - (bytes_process % 8);
  1223. }
  1224. return 0;
  1225. }
  1226. static void r8152_halt(struct eth_device *eth)
  1227. {
  1228. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  1229. struct r8152 *tp = (struct r8152 *)dev->dev_priv;
  1230. debug("** %s()\n", __func__);
  1231. tp->rtl_ops.disable(tp);
  1232. }
  1233. static int r8152_write_hwaddr(struct eth_device *eth)
  1234. {
  1235. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  1236. struct r8152 *tp = (struct r8152 *)dev->dev_priv;
  1237. unsigned char enetaddr[8] = {0};
  1238. memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
  1239. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1240. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
  1241. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1242. debug("MAC %pM\n", eth->enetaddr);
  1243. return 0;
  1244. }
  1245. void r8152_eth_before_probe(void)
  1246. {
  1247. curr_eth_dev = 0;
  1248. }
  1249. /* Probe to see if a new device is actually an realtek device */
  1250. int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
  1251. struct ueth_data *ss)
  1252. {
  1253. struct usb_interface *iface;
  1254. struct usb_interface_descriptor *iface_desc;
  1255. int ep_in_found = 0, ep_out_found = 0;
  1256. struct r8152 *tp;
  1257. int i;
  1258. /* let's examine the device now */
  1259. iface = &dev->config.if_desc[ifnum];
  1260. iface_desc = &dev->config.if_desc[ifnum].desc;
  1261. for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
  1262. if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
  1263. dev->descriptor.idProduct == r8152_dongles[i].product)
  1264. /* Found a supported dongle */
  1265. break;
  1266. }
  1267. if (i == ARRAY_SIZE(r8152_dongles))
  1268. return 0;
  1269. memset(ss, 0, sizeof(struct ueth_data));
  1270. /* At this point, we know we've got a live one */
  1271. debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
  1272. dev->descriptor.idVendor, dev->descriptor.idProduct);
  1273. /* Initialize the ueth_data structure with some useful info */
  1274. ss->ifnum = ifnum;
  1275. ss->pusb_dev = dev;
  1276. ss->subclass = iface_desc->bInterfaceSubClass;
  1277. ss->protocol = iface_desc->bInterfaceProtocol;
  1278. /* alloc driver private */
  1279. ss->dev_priv = calloc(1, sizeof(struct r8152));
  1280. if (!ss->dev_priv)
  1281. return 0;
  1282. /*
  1283. * We are expecting a minimum of 3 endpoints - in, out (bulk), and
  1284. * int. We will ignore any others.
  1285. */
  1286. for (i = 0; i < iface_desc->bNumEndpoints; i++) {
  1287. /* is it an BULK endpoint? */
  1288. if ((iface->ep_desc[i].bmAttributes &
  1289. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
  1290. u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
  1291. if (ep_addr & USB_DIR_IN) {
  1292. if (!ep_in_found) {
  1293. ss->ep_in = ep_addr &
  1294. USB_ENDPOINT_NUMBER_MASK;
  1295. ep_in_found = 1;
  1296. }
  1297. } else {
  1298. if (!ep_out_found) {
  1299. ss->ep_out = ep_addr &
  1300. USB_ENDPOINT_NUMBER_MASK;
  1301. ep_out_found = 1;
  1302. }
  1303. }
  1304. }
  1305. /* is it an interrupt endpoint? */
  1306. if ((iface->ep_desc[i].bmAttributes &
  1307. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
  1308. ss->ep_int = iface->ep_desc[i].bEndpointAddress &
  1309. USB_ENDPOINT_NUMBER_MASK;
  1310. ss->irqinterval = iface->ep_desc[i].bInterval;
  1311. }
  1312. }
  1313. debug("Endpoints In %d Out %d Int %d\n",
  1314. ss->ep_in, ss->ep_out, ss->ep_int);
  1315. /* Do some basic sanity checks, and bail if we find a problem */
  1316. if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
  1317. !ss->ep_in || !ss->ep_out || !ss->ep_int) {
  1318. debug("Problems with device\n");
  1319. goto error;
  1320. }
  1321. dev->privptr = (void *)ss;
  1322. tp = ss->dev_priv;
  1323. tp->udev = dev;
  1324. tp->intf = iface;
  1325. r8152b_get_version(tp);
  1326. if (rtl_ops_init(tp))
  1327. goto error;
  1328. tp->rtl_ops.init(tp);
  1329. tp->rtl_ops.up(tp);
  1330. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  1331. tp->supports_gmii ? SPEED_1000 : SPEED_100,
  1332. DUPLEX_FULL);
  1333. return 1;
  1334. error:
  1335. cfree(ss->dev_priv);
  1336. ss->dev_priv = 0;
  1337. return 0;
  1338. }
  1339. int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
  1340. struct eth_device *eth)
  1341. {
  1342. if (!eth) {
  1343. debug("%s: missing parameter.\n", __func__);
  1344. return 0;
  1345. }
  1346. sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
  1347. eth->init = r8152_init;
  1348. eth->send = r8152_send;
  1349. eth->recv = r8152_recv;
  1350. eth->halt = r8152_halt;
  1351. eth->write_hwaddr = r8152_write_hwaddr;
  1352. eth->priv = ss;
  1353. /* Get the MAC address */
  1354. if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
  1355. return 0;
  1356. debug("MAC %pM\n", eth->enetaddr);
  1357. return 1;
  1358. }
  1359. #endif /* !CONFIG_DM_ETH */
  1360. #ifdef CONFIG_DM_ETH
  1361. static int r8152_eth_start(struct udevice *dev)
  1362. {
  1363. struct r8152 *tp = dev_get_priv(dev);
  1364. debug("** %s (%d)\n", __func__, __LINE__);
  1365. return r8152_init_common(tp);
  1366. }
  1367. void r8152_eth_stop(struct udevice *dev)
  1368. {
  1369. struct r8152 *tp = dev_get_priv(dev);
  1370. debug("** %s (%d)\n", __func__, __LINE__);
  1371. tp->rtl_ops.disable(tp);
  1372. }
  1373. int r8152_eth_send(struct udevice *dev, void *packet, int length)
  1374. {
  1375. struct r8152 *tp = dev_get_priv(dev);
  1376. return r8152_send_common(&tp->ueth, packet, length);
  1377. }
  1378. int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  1379. {
  1380. struct r8152 *tp = dev_get_priv(dev);
  1381. struct ueth_data *ueth = &tp->ueth;
  1382. uint8_t *ptr;
  1383. int ret, len;
  1384. struct rx_desc *rx_desc;
  1385. u16 packet_len;
  1386. len = usb_ether_get_rx_bytes(ueth, &ptr);
  1387. debug("%s: first try, len=%d\n", __func__, len);
  1388. if (!len) {
  1389. if (!(flags & ETH_RECV_CHECK_DEVICE))
  1390. return -EAGAIN;
  1391. ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ);
  1392. if (ret)
  1393. return ret;
  1394. len = usb_ether_get_rx_bytes(ueth, &ptr);
  1395. debug("%s: second try, len=%d\n", __func__, len);
  1396. }
  1397. rx_desc = (struct rx_desc *)ptr;
  1398. packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1399. packet_len -= CRC_SIZE;
  1400. if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) {
  1401. debug("Rx: too large packet: %d\n", packet_len);
  1402. goto err;
  1403. }
  1404. *packetp = ptr + sizeof(struct rx_desc);
  1405. return packet_len;
  1406. err:
  1407. usb_ether_advance_rxbuf(ueth, -1);
  1408. return -ENOSPC;
  1409. }
  1410. static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
  1411. {
  1412. struct r8152 *tp = dev_get_priv(dev);
  1413. packet_len += sizeof(struct rx_desc) + CRC_SIZE;
  1414. packet_len = ALIGN(packet_len, 8);
  1415. usb_ether_advance_rxbuf(&tp->ueth, packet_len);
  1416. return 0;
  1417. }
  1418. static int r8152_write_hwaddr(struct udevice *dev)
  1419. {
  1420. struct eth_pdata *pdata = dev_get_platdata(dev);
  1421. struct r8152 *tp = dev_get_priv(dev);
  1422. unsigned char enetaddr[8] = { 0 };
  1423. debug("** %s (%d)\n", __func__, __LINE__);
  1424. memcpy(enetaddr, pdata->enetaddr, ETH_ALEN);
  1425. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1426. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
  1427. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1428. debug("MAC %pM\n", pdata->enetaddr);
  1429. return 0;
  1430. }
  1431. int r8152_read_rom_hwaddr(struct udevice *dev)
  1432. {
  1433. struct eth_pdata *pdata = dev_get_platdata(dev);
  1434. struct r8152 *tp = dev_get_priv(dev);
  1435. debug("** %s (%d)\n", __func__, __LINE__);
  1436. r8152_read_mac(tp, pdata->enetaddr);
  1437. return 0;
  1438. }
  1439. static int r8152_eth_probe(struct udevice *dev)
  1440. {
  1441. struct usb_device *udev = dev_get_parent_priv(dev);
  1442. struct eth_pdata *pdata = dev_get_platdata(dev);
  1443. struct r8152 *tp = dev_get_priv(dev);
  1444. struct ueth_data *ueth = &tp->ueth;
  1445. int ret;
  1446. tp->udev = udev;
  1447. r8152_read_mac(tp, pdata->enetaddr);
  1448. r8152b_get_version(tp);
  1449. ret = rtl_ops_init(tp);
  1450. if (ret)
  1451. return ret;
  1452. tp->rtl_ops.init(tp);
  1453. tp->rtl_ops.up(tp);
  1454. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  1455. tp->supports_gmii ? SPEED_1000 : SPEED_100,
  1456. DUPLEX_FULL);
  1457. return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ);
  1458. }
  1459. static const struct eth_ops r8152_eth_ops = {
  1460. .start = r8152_eth_start,
  1461. .send = r8152_eth_send,
  1462. .recv = r8152_eth_recv,
  1463. .free_pkt = r8152_free_pkt,
  1464. .stop = r8152_eth_stop,
  1465. .write_hwaddr = r8152_write_hwaddr,
  1466. .read_rom_hwaddr = r8152_read_rom_hwaddr,
  1467. };
  1468. U_BOOT_DRIVER(r8152_eth) = {
  1469. .name = "r8152_eth",
  1470. .id = UCLASS_ETH,
  1471. .probe = r8152_eth_probe,
  1472. .ops = &r8152_eth_ops,
  1473. .priv_auto_alloc_size = sizeof(struct r8152),
  1474. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1475. };
  1476. static const struct usb_device_id r8152_eth_id_table[] = {
  1477. /* Realtek */
  1478. { USB_DEVICE(0x0bda, 0x8050) },
  1479. { USB_DEVICE(0x0bda, 0x8152) },
  1480. { USB_DEVICE(0x0bda, 0x8153) },
  1481. /* Samsung */
  1482. { USB_DEVICE(0x04e8, 0xa101) },
  1483. /* Lenovo */
  1484. { USB_DEVICE(0x17ef, 0x304f) },
  1485. { USB_DEVICE(0x17ef, 0x3052) },
  1486. { USB_DEVICE(0x17ef, 0x3054) },
  1487. { USB_DEVICE(0x17ef, 0x3057) },
  1488. { USB_DEVICE(0x17ef, 0x7205) },
  1489. { USB_DEVICE(0x17ef, 0x720a) },
  1490. { USB_DEVICE(0x17ef, 0x720b) },
  1491. { USB_DEVICE(0x17ef, 0x720c) },
  1492. /* TP-LINK */
  1493. { USB_DEVICE(0x2357, 0x0601) },
  1494. /* Nvidia */
  1495. { USB_DEVICE(0x0955, 0x09ff) },
  1496. { } /* Terminating entry */
  1497. };
  1498. U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
  1499. #endif /* CONFIG_DM_ETH */