asix88179.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de>
  4. * based on the U-Boot Asix driver as well as information
  5. * from the Linux AX88179_178a driver
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <usb.h>
  11. #include <net.h>
  12. #include <linux/delay.h>
  13. #include <linux/mii.h>
  14. #include "usb_ether.h"
  15. #include <malloc.h>
  16. #include <memalign.h>
  17. #include <errno.h>
  18. /* ASIX AX88179 based USB 3.0 Ethernet Devices */
  19. #define AX88179_PHY_ID 0x03
  20. #define AX_EEPROM_LEN 0x100
  21. #define AX88179_EEPROM_MAGIC 0x17900b95
  22. #define AX_MCAST_FLTSIZE 8
  23. #define AX_MAX_MCAST 64
  24. #define AX_INT_PPLS_LINK (1 << 16)
  25. #define AX_RXHDR_L4_TYPE_MASK 0x1c
  26. #define AX_RXHDR_L4_TYPE_UDP 4
  27. #define AX_RXHDR_L4_TYPE_TCP 16
  28. #define AX_RXHDR_L3CSUM_ERR 2
  29. #define AX_RXHDR_L4CSUM_ERR 1
  30. #define AX_RXHDR_CRC_ERR (1 << 29)
  31. #define AX_RXHDR_DROP_ERR (1 << 31)
  32. #define AX_ENDPOINT_INT 0x01
  33. #define AX_ENDPOINT_IN 0x02
  34. #define AX_ENDPOINT_OUT 0x03
  35. #define AX_ACCESS_MAC 0x01
  36. #define AX_ACCESS_PHY 0x02
  37. #define AX_ACCESS_EEPROM 0x04
  38. #define AX_ACCESS_EFUS 0x05
  39. #define AX_PAUSE_WATERLVL_HIGH 0x54
  40. #define AX_PAUSE_WATERLVL_LOW 0x55
  41. #define PHYSICAL_LINK_STATUS 0x02
  42. #define AX_USB_SS (1 << 2)
  43. #define AX_USB_HS (1 << 1)
  44. #define GENERAL_STATUS 0x03
  45. #define AX_SECLD (1 << 2)
  46. #define AX_SROM_ADDR 0x07
  47. #define AX_SROM_CMD 0x0a
  48. #define EEP_RD (1 << 2)
  49. #define EEP_BUSY (1 << 4)
  50. #define AX_SROM_DATA_LOW 0x08
  51. #define AX_SROM_DATA_HIGH 0x09
  52. #define AX_RX_CTL 0x0b
  53. #define AX_RX_CTL_DROPCRCERR (1 << 8)
  54. #define AX_RX_CTL_IPE (1 << 9)
  55. #define AX_RX_CTL_START (1 << 7)
  56. #define AX_RX_CTL_AP (1 << 5)
  57. #define AX_RX_CTL_AM (1 << 4)
  58. #define AX_RX_CTL_AB (1 << 3)
  59. #define AX_RX_CTL_AMALL (1 << 1)
  60. #define AX_RX_CTL_PRO (1 << 0)
  61. #define AX_RX_CTL_STOP 0
  62. #define AX_NODE_ID 0x10
  63. #define AX_MULFLTARY 0x16
  64. #define AX_MEDIUM_STATUS_MODE 0x22
  65. #define AX_MEDIUM_GIGAMODE (1 << 0)
  66. #define AX_MEDIUM_FULL_DUPLEX (1 << 1)
  67. #define AX_MEDIUM_EN_125MHZ (1 << 3)
  68. #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4)
  69. #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5)
  70. #define AX_MEDIUM_RECEIVE_EN (1 << 8)
  71. #define AX_MEDIUM_PS (1 << 9)
  72. #define AX_MEDIUM_JUMBO_EN 0x8040
  73. #define AX_MONITOR_MOD 0x24
  74. #define AX_MONITOR_MODE_RWLC (1 << 1)
  75. #define AX_MONITOR_MODE_RWMP (1 << 2)
  76. #define AX_MONITOR_MODE_PMEPOL (1 << 5)
  77. #define AX_MONITOR_MODE_PMETYPE (1 << 6)
  78. #define AX_GPIO_CTRL 0x25
  79. #define AX_GPIO_CTRL_GPIO3EN (1 << 7)
  80. #define AX_GPIO_CTRL_GPIO2EN (1 << 6)
  81. #define AX_GPIO_CTRL_GPIO1EN (1 << 5)
  82. #define AX_PHYPWR_RSTCTL 0x26
  83. #define AX_PHYPWR_RSTCTL_BZ (1 << 4)
  84. #define AX_PHYPWR_RSTCTL_IPRL (1 << 5)
  85. #define AX_PHYPWR_RSTCTL_AT (1 << 12)
  86. #define AX_RX_BULKIN_QCTRL 0x2e
  87. #define AX_CLK_SELECT 0x33
  88. #define AX_CLK_SELECT_BCS (1 << 0)
  89. #define AX_CLK_SELECT_ACS (1 << 1)
  90. #define AX_CLK_SELECT_ULR (1 << 3)
  91. #define AX_RXCOE_CTL 0x34
  92. #define AX_RXCOE_IP (1 << 0)
  93. #define AX_RXCOE_TCP (1 << 1)
  94. #define AX_RXCOE_UDP (1 << 2)
  95. #define AX_RXCOE_TCPV6 (1 << 5)
  96. #define AX_RXCOE_UDPV6 (1 << 6)
  97. #define AX_TXCOE_CTL 0x35
  98. #define AX_TXCOE_IP (1 << 0)
  99. #define AX_TXCOE_TCP (1 << 1)
  100. #define AX_TXCOE_UDP (1 << 2)
  101. #define AX_TXCOE_TCPV6 (1 << 5)
  102. #define AX_TXCOE_UDPV6 (1 << 6)
  103. #define AX_LEDCTRL 0x73
  104. #define GMII_PHY_PHYSR 0x11
  105. #define GMII_PHY_PHYSR_SMASK 0xc000
  106. #define GMII_PHY_PHYSR_GIGA (1 << 15)
  107. #define GMII_PHY_PHYSR_100 (1 << 14)
  108. #define GMII_PHY_PHYSR_FULL (1 << 13)
  109. #define GMII_PHY_PHYSR_LINK (1 << 10)
  110. #define GMII_LED_ACT 0x1a
  111. #define GMII_LED_ACTIVE_MASK 0xff8f
  112. #define GMII_LED0_ACTIVE (1 << 4)
  113. #define GMII_LED1_ACTIVE (1 << 5)
  114. #define GMII_LED2_ACTIVE (1 << 6)
  115. #define GMII_LED_LINK 0x1c
  116. #define GMII_LED_LINK_MASK 0xf888
  117. #define GMII_LED0_LINK_10 (1 << 0)
  118. #define GMII_LED0_LINK_100 (1 << 1)
  119. #define GMII_LED0_LINK_1000 (1 << 2)
  120. #define GMII_LED1_LINK_10 (1 << 4)
  121. #define GMII_LED1_LINK_100 (1 << 5)
  122. #define GMII_LED1_LINK_1000 (1 << 6)
  123. #define GMII_LED2_LINK_10 (1 << 8)
  124. #define GMII_LED2_LINK_100 (1 << 9)
  125. #define GMII_LED2_LINK_1000 (1 << 10)
  126. #define LED0_ACTIVE (1 << 0)
  127. #define LED0_LINK_10 (1 << 1)
  128. #define LED0_LINK_100 (1 << 2)
  129. #define LED0_LINK_1000 (1 << 3)
  130. #define LED0_FD (1 << 4)
  131. #define LED0_USB3_MASK 0x001f
  132. #define LED1_ACTIVE (1 << 5)
  133. #define LED1_LINK_10 (1 << 6)
  134. #define LED1_LINK_100 (1 << 7)
  135. #define LED1_LINK_1000 (1 << 8)
  136. #define LED1_FD (1 << 9)
  137. #define LED1_USB3_MASK 0x03e0
  138. #define LED2_ACTIVE (1 << 10)
  139. #define LED2_LINK_1000 (1 << 13)
  140. #define LED2_LINK_100 (1 << 12)
  141. #define LED2_LINK_10 (1 << 11)
  142. #define LED2_FD (1 << 14)
  143. #define LED_VALID (1 << 15)
  144. #define LED2_USB3_MASK 0x7c00
  145. #define GMII_PHYPAGE 0x1e
  146. #define GMII_PHY_PAGE_SELECT 0x1f
  147. #define GMII_PHY_PGSEL_EXT 0x0007
  148. #define GMII_PHY_PGSEL_PAGE0 0x0000
  149. /* local defines */
  150. #define ASIX_BASE_NAME "axg"
  151. #define USB_CTRL_SET_TIMEOUT 5000
  152. #define USB_CTRL_GET_TIMEOUT 5000
  153. #define USB_BULK_SEND_TIMEOUT 5000
  154. #define USB_BULK_RECV_TIMEOUT 5000
  155. #define AX_RX_URB_SIZE 1024 * 0x12
  156. #define BLK_FRAME_SIZE 0x200
  157. #define PHY_CONNECT_TIMEOUT 5000
  158. #define TIMEOUT_RESOLUTION 50 /* ms */
  159. #define FLAG_NONE 0
  160. #define FLAG_TYPE_AX88179 (1U << 0)
  161. #define FLAG_TYPE_AX88178a (1U << 1)
  162. #define FLAG_TYPE_DLINK_DUB1312 (1U << 2)
  163. #define FLAG_TYPE_SITECOM (1U << 3)
  164. #define FLAG_TYPE_SAMSUNG (1U << 4)
  165. #define FLAG_TYPE_LENOVO (1U << 5)
  166. #define FLAG_TYPE_GX3 (1U << 6)
  167. /* local vars */
  168. static const struct {
  169. unsigned char ctrl, timer_l, timer_h, size, ifg;
  170. } AX88179_BULKIN_SIZE[] = {
  171. {7, 0x4f, 0, 0x02, 0xff},
  172. {7, 0x20, 3, 0x03, 0xff},
  173. {7, 0xae, 7, 0x04, 0xff},
  174. {7, 0xcc, 0x4c, 0x04, 8},
  175. };
  176. #ifndef CONFIG_DM_ETH
  177. static int curr_eth_dev; /* index for name of next device detected */
  178. #endif
  179. /* driver private */
  180. struct asix_private {
  181. #ifdef CONFIG_DM_ETH
  182. struct ueth_data ueth;
  183. unsigned pkt_cnt;
  184. uint8_t *pkt_data;
  185. uint32_t *pkt_hdr;
  186. #endif
  187. int flags;
  188. int rx_urb_size;
  189. int maxpacketsize;
  190. };
  191. /*
  192. * Asix infrastructure commands
  193. */
  194. static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
  195. u16 size, void *data)
  196. {
  197. int len;
  198. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
  199. debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
  200. cmd, value, index, size);
  201. memcpy(buf, data, size);
  202. len = usb_control_msg(
  203. dev->pusb_dev,
  204. usb_sndctrlpipe(dev->pusb_dev, 0),
  205. cmd,
  206. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  207. value,
  208. index,
  209. buf,
  210. size,
  211. USB_CTRL_SET_TIMEOUT);
  212. return len == size ? 0 : ECOMM;
  213. }
  214. static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
  215. u16 size, void *data)
  216. {
  217. int len;
  218. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size);
  219. debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
  220. cmd, value, index, size);
  221. len = usb_control_msg(
  222. dev->pusb_dev,
  223. usb_rcvctrlpipe(dev->pusb_dev, 0),
  224. cmd,
  225. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  226. value,
  227. index,
  228. buf,
  229. size,
  230. USB_CTRL_GET_TIMEOUT);
  231. memcpy(data, buf, size);
  232. return len == size ? 0 : ECOMM;
  233. }
  234. static int asix_read_mac(struct ueth_data *dev, uint8_t *enetaddr)
  235. {
  236. int ret;
  237. ret = asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, enetaddr);
  238. if (ret < 0)
  239. debug("Failed to read MAC address: %02x\n", ret);
  240. return ret;
  241. }
  242. static int asix_write_mac(struct ueth_data *dev, uint8_t *enetaddr)
  243. {
  244. int ret;
  245. ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
  246. ETH_ALEN, enetaddr);
  247. if (ret < 0)
  248. debug("Failed to set MAC address: %02x\n", ret);
  249. return ret;
  250. }
  251. static int asix_basic_reset(struct ueth_data *dev,
  252. struct asix_private *dev_priv)
  253. {
  254. u8 buf[5];
  255. u16 *tmp16;
  256. u8 *tmp;
  257. tmp16 = (u16 *)buf;
  258. tmp = (u8 *)buf;
  259. /* Power up ethernet PHY */
  260. *tmp16 = 0;
  261. asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  262. *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  263. asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  264. mdelay(200);
  265. *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  266. asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
  267. mdelay(200);
  268. /* RX bulk configuration */
  269. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  270. asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  271. dev_priv->rx_urb_size = 128 * 20;
  272. /* Water Level configuration */
  273. *tmp = 0x34;
  274. asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
  275. *tmp = 0x52;
  276. asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp);
  277. /* Enable checksum offload */
  278. *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  279. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  280. asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
  281. *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
  282. AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  283. asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
  284. /* Configure RX control register => start operation */
  285. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  286. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  287. asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
  288. *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
  289. AX_MONITOR_MODE_RWMP;
  290. asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
  291. /* Configure default medium type => giga */
  292. *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  293. AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
  294. AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN;
  295. asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16);
  296. u16 adv = 0;
  297. adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK |
  298. ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP;
  299. asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv);
  300. adv = ADVERTISE_1000FULL;
  301. asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv);
  302. return 0;
  303. }
  304. static int asix_wait_link(struct ueth_data *dev)
  305. {
  306. int timeout = 0;
  307. int link_detected;
  308. u8 buf[2];
  309. u16 *tmp16;
  310. tmp16 = (u16 *)buf;
  311. do {
  312. asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  313. MII_BMSR, 2, buf);
  314. link_detected = *tmp16 & BMSR_LSTATUS;
  315. if (!link_detected) {
  316. if (timeout == 0)
  317. printf("Waiting for Ethernet connection... ");
  318. mdelay(TIMEOUT_RESOLUTION);
  319. timeout += TIMEOUT_RESOLUTION;
  320. }
  321. } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
  322. if (link_detected) {
  323. if (timeout > 0)
  324. printf("done.\n");
  325. return 0;
  326. } else {
  327. printf("unable to connect.\n");
  328. return -ENETUNREACH;
  329. }
  330. }
  331. static int asix_init_common(struct ueth_data *dev,
  332. struct asix_private *dev_priv)
  333. {
  334. u8 buf[2], tmp[5], link_sts;
  335. u16 *tmp16, mode;
  336. tmp16 = (u16 *)buf;
  337. debug("** %s()\n", __func__);
  338. /* Configure RX control register => start operation */
  339. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  340. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  341. if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0)
  342. goto out_err;
  343. if (asix_wait_link(dev) != 0) {
  344. /*reset device and try again*/
  345. printf("Reset Ethernet Device\n");
  346. asix_basic_reset(dev, dev_priv);
  347. if (asix_wait_link(dev) != 0)
  348. goto out_err;
  349. }
  350. /* Configure link */
  351. mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  352. AX_MEDIUM_RXFLOW_CTRLEN;
  353. asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
  354. 1, 1, &link_sts);
  355. asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  356. GMII_PHY_PHYSR, 2, tmp16);
  357. if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) {
  358. return 0;
  359. } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
  360. mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ |
  361. AX_MEDIUM_JUMBO_EN;
  362. if (link_sts & AX_USB_SS)
  363. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  364. else if (link_sts & AX_USB_HS)
  365. memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
  366. else
  367. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  368. } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) {
  369. mode |= AX_MEDIUM_PS;
  370. if (link_sts & (AX_USB_SS | AX_USB_HS))
  371. memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
  372. else
  373. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  374. } else {
  375. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  376. }
  377. /* RX bulk configuration */
  378. asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  379. dev_priv->rx_urb_size = (1024 * (tmp[3] + 2));
  380. if (*tmp16 & GMII_PHY_PHYSR_FULL)
  381. mode |= AX_MEDIUM_FULL_DUPLEX;
  382. asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  383. 2, 2, &mode);
  384. return 0;
  385. out_err:
  386. return -1;
  387. }
  388. static int asix_send_common(struct ueth_data *dev,
  389. struct asix_private *dev_priv,
  390. void *packet, int length)
  391. {
  392. int err;
  393. u32 packet_len, tx_hdr2;
  394. int actual_len, framesize;
  395. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
  396. PKTSIZE + (2 * sizeof(packet_len)));
  397. debug("** %s(), len %d\n", __func__, length);
  398. packet_len = length;
  399. cpu_to_le32s(&packet_len);
  400. memcpy(msg, &packet_len, sizeof(packet_len));
  401. framesize = dev_priv->maxpacketsize;
  402. tx_hdr2 = 0;
  403. if (((length + 8) % framesize) == 0)
  404. tx_hdr2 |= 0x80008000; /* Enable padding */
  405. cpu_to_le32s(&tx_hdr2);
  406. memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2));
  407. memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2),
  408. (void *)packet, length);
  409. err = usb_bulk_msg(dev->pusb_dev,
  410. usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
  411. (void *)msg,
  412. length + sizeof(packet_len) + sizeof(tx_hdr2),
  413. &actual_len,
  414. USB_BULK_SEND_TIMEOUT);
  415. debug("Tx: len = %zu, actual = %u, err = %d\n",
  416. length + sizeof(packet_len), actual_len, err);
  417. return err;
  418. }
  419. #ifndef CONFIG_DM_ETH
  420. /*
  421. * Asix callbacks
  422. */
  423. static int asix_init(struct eth_device *eth, struct bd_info *bd)
  424. {
  425. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  426. struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
  427. return asix_init_common(dev, dev_priv);
  428. }
  429. static int asix_write_hwaddr(struct eth_device *eth)
  430. {
  431. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  432. return asix_write_mac(dev, eth->enetaddr);
  433. }
  434. static int asix_send(struct eth_device *eth, void *packet, int length)
  435. {
  436. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  437. struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
  438. return asix_send_common(dev, dev_priv, packet, length);
  439. }
  440. static int asix_recv(struct eth_device *eth)
  441. {
  442. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  443. struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
  444. u16 frame_pos;
  445. int err;
  446. int actual_len;
  447. int pkt_cnt;
  448. u32 rx_hdr;
  449. u16 hdr_off;
  450. u32 *pkt_hdr;
  451. ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size);
  452. actual_len = -1;
  453. debug("** %s()\n", __func__);
  454. err = usb_bulk_msg(dev->pusb_dev,
  455. usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
  456. (void *)recv_buf,
  457. dev_priv->rx_urb_size,
  458. &actual_len,
  459. USB_BULK_RECV_TIMEOUT);
  460. debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size,
  461. actual_len, err);
  462. if (err != 0) {
  463. debug("Rx: failed to receive\n");
  464. return -ECOMM;
  465. }
  466. if (actual_len > dev_priv->rx_urb_size) {
  467. debug("Rx: received too many bytes %d\n", actual_len);
  468. return -EMSGSIZE;
  469. }
  470. rx_hdr = *(u32 *)(recv_buf + actual_len - 4);
  471. le32_to_cpus(&rx_hdr);
  472. pkt_cnt = (u16)rx_hdr;
  473. hdr_off = (u16)(rx_hdr >> 16);
  474. pkt_hdr = (u32 *)(recv_buf + hdr_off);
  475. frame_pos = 0;
  476. while (pkt_cnt--) {
  477. u16 pkt_len;
  478. le32_to_cpus(pkt_hdr);
  479. pkt_len = (*pkt_hdr >> 16) & 0x1fff;
  480. frame_pos += 2;
  481. net_process_received_packet(recv_buf + frame_pos, pkt_len);
  482. pkt_hdr++;
  483. frame_pos += ((pkt_len + 7) & 0xFFF8)-2;
  484. if (pkt_cnt == 0)
  485. return 0;
  486. }
  487. return err;
  488. }
  489. static void asix_halt(struct eth_device *eth)
  490. {
  491. debug("** %s()\n", __func__);
  492. }
  493. /*
  494. * Asix probing functions
  495. */
  496. void ax88179_eth_before_probe(void)
  497. {
  498. curr_eth_dev = 0;
  499. }
  500. struct asix_dongle {
  501. unsigned short vendor;
  502. unsigned short product;
  503. int flags;
  504. };
  505. static const struct asix_dongle asix_dongles[] = {
  506. { 0x0b95, 0x1790, FLAG_TYPE_AX88179 },
  507. { 0x0b95, 0x178a, FLAG_TYPE_AX88178a },
  508. { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 },
  509. { 0x0df6, 0x0072, FLAG_TYPE_SITECOM },
  510. { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG },
  511. { 0x17ef, 0x304b, FLAG_TYPE_LENOVO },
  512. { 0x04b4, 0x3610, FLAG_TYPE_GX3 },
  513. { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
  514. };
  515. /* Probe to see if a new device is actually an asix device */
  516. int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum,
  517. struct ueth_data *ss)
  518. {
  519. struct usb_interface *iface;
  520. struct usb_interface_descriptor *iface_desc;
  521. struct asix_private *dev_priv;
  522. int ep_in_found = 0, ep_out_found = 0;
  523. int i;
  524. /* let's examine the device now */
  525. iface = &dev->config.if_desc[ifnum];
  526. iface_desc = &dev->config.if_desc[ifnum].desc;
  527. for (i = 0; asix_dongles[i].vendor != 0; i++) {
  528. if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
  529. dev->descriptor.idProduct == asix_dongles[i].product)
  530. /* Found a supported dongle */
  531. break;
  532. }
  533. if (asix_dongles[i].vendor == 0)
  534. return 0;
  535. memset(ss, 0, sizeof(struct ueth_data));
  536. /* At this point, we know we've got a live one */
  537. debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
  538. dev->descriptor.idVendor, dev->descriptor.idProduct);
  539. /* Initialize the ueth_data structure with some useful info */
  540. ss->ifnum = ifnum;
  541. ss->pusb_dev = dev;
  542. ss->subclass = iface_desc->bInterfaceSubClass;
  543. ss->protocol = iface_desc->bInterfaceProtocol;
  544. /* alloc driver private */
  545. ss->dev_priv = calloc(1, sizeof(struct asix_private));
  546. if (!ss->dev_priv)
  547. return 0;
  548. dev_priv = ss->dev_priv;
  549. dev_priv->flags = asix_dongles[i].flags;
  550. /*
  551. * We are expecting a minimum of 3 endpoints - in, out (bulk), and
  552. * int. We will ignore any others.
  553. */
  554. for (i = 0; i < iface_desc->bNumEndpoints; i++) {
  555. /* is it an interrupt endpoint? */
  556. if ((iface->ep_desc[i].bmAttributes &
  557. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
  558. ss->ep_int = iface->ep_desc[i].bEndpointAddress &
  559. USB_ENDPOINT_NUMBER_MASK;
  560. ss->irqinterval = iface->ep_desc[i].bInterval;
  561. continue;
  562. }
  563. /* is it an BULK endpoint? */
  564. if (!((iface->ep_desc[i].bmAttributes &
  565. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK))
  566. continue;
  567. u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
  568. if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
  569. ss->ep_in = ep_addr &
  570. USB_ENDPOINT_NUMBER_MASK;
  571. ep_in_found = 1;
  572. }
  573. if (!(ep_addr & USB_DIR_IN) && !ep_out_found) {
  574. ss->ep_out = ep_addr &
  575. USB_ENDPOINT_NUMBER_MASK;
  576. dev_priv->maxpacketsize =
  577. dev->epmaxpacketout[AX_ENDPOINT_OUT];
  578. ep_out_found = 1;
  579. }
  580. }
  581. debug("Endpoints In %d Out %d Int %d\n",
  582. ss->ep_in, ss->ep_out, ss->ep_int);
  583. /* Do some basic sanity checks, and bail if we find a problem */
  584. if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
  585. !ss->ep_in || !ss->ep_out || !ss->ep_int) {
  586. debug("Problems with device\n");
  587. return 0;
  588. }
  589. dev->privptr = (void *)ss;
  590. return 1;
  591. }
  592. int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
  593. struct eth_device *eth)
  594. {
  595. struct asix_private *dev_priv = (struct asix_private *)ss->dev_priv;
  596. if (!eth) {
  597. debug("%s: missing parameter.\n", __func__);
  598. return 0;
  599. }
  600. sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
  601. eth->init = asix_init;
  602. eth->send = asix_send;
  603. eth->recv = asix_recv;
  604. eth->halt = asix_halt;
  605. eth->write_hwaddr = asix_write_hwaddr;
  606. eth->priv = ss;
  607. if (asix_basic_reset(ss, dev_priv))
  608. return 0;
  609. /* Get the MAC address */
  610. if (asix_read_mac(ss, eth->enetaddr))
  611. return 0;
  612. debug("MAC %pM\n", eth->enetaddr);
  613. return 1;
  614. }
  615. #else /* !CONFIG_DM_ETH */
  616. static int ax88179_eth_start(struct udevice *dev)
  617. {
  618. struct asix_private *priv = dev_get_priv(dev);
  619. return asix_init_common(&priv->ueth, priv);
  620. }
  621. void ax88179_eth_stop(struct udevice *dev)
  622. {
  623. struct asix_private *priv = dev_get_priv(dev);
  624. struct ueth_data *ueth = &priv->ueth;
  625. debug("** %s()\n", __func__);
  626. usb_ether_advance_rxbuf(ueth, -1);
  627. priv->pkt_cnt = 0;
  628. priv->pkt_data = NULL;
  629. priv->pkt_hdr = NULL;
  630. }
  631. int ax88179_eth_send(struct udevice *dev, void *packet, int length)
  632. {
  633. struct asix_private *priv = dev_get_priv(dev);
  634. return asix_send_common(&priv->ueth, priv, packet, length);
  635. }
  636. int ax88179_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  637. {
  638. struct asix_private *priv = dev_get_priv(dev);
  639. struct ueth_data *ueth = &priv->ueth;
  640. int ret, len;
  641. u16 pkt_len;
  642. /* No packet left, get a new one */
  643. if (priv->pkt_cnt == 0) {
  644. uint8_t *ptr;
  645. u16 pkt_cnt;
  646. u16 hdr_off;
  647. u32 rx_hdr;
  648. len = usb_ether_get_rx_bytes(ueth, &ptr);
  649. debug("%s: first try, len=%d\n", __func__, len);
  650. if (!len) {
  651. if (!(flags & ETH_RECV_CHECK_DEVICE))
  652. return -EAGAIN;
  653. ret = usb_ether_receive(ueth, priv->rx_urb_size);
  654. if (ret < 0)
  655. return ret;
  656. len = usb_ether_get_rx_bytes(ueth, &ptr);
  657. debug("%s: second try, len=%d\n", __func__, len);
  658. }
  659. if (len < 4) {
  660. usb_ether_advance_rxbuf(ueth, -1);
  661. return -EMSGSIZE;
  662. }
  663. rx_hdr = *(u32 *)(ptr + len - 4);
  664. le32_to_cpus(&rx_hdr);
  665. pkt_cnt = (u16)rx_hdr;
  666. if (pkt_cnt == 0) {
  667. usb_ether_advance_rxbuf(ueth, -1);
  668. return 0;
  669. }
  670. hdr_off = (u16)(rx_hdr >> 16);
  671. if (hdr_off > len - 4) {
  672. usb_ether_advance_rxbuf(ueth, -1);
  673. return -EIO;
  674. }
  675. priv->pkt_cnt = pkt_cnt;
  676. priv->pkt_data = ptr;
  677. priv->pkt_hdr = (u32 *)(ptr + hdr_off);
  678. debug("%s: %d packets received, pkt header at %d\n",
  679. __func__, (int)priv->pkt_cnt, (int)hdr_off);
  680. }
  681. le32_to_cpus(priv->pkt_hdr);
  682. pkt_len = (*priv->pkt_hdr >> 16) & 0x1fff;
  683. *packetp = priv->pkt_data + 2;
  684. priv->pkt_data += (pkt_len + 7) & 0xFFF8;
  685. priv->pkt_cnt--;
  686. priv->pkt_hdr++;
  687. debug("%s: return packet of %d bytes (%d packets left)\n",
  688. __func__, (int)pkt_len, priv->pkt_cnt);
  689. return pkt_len;
  690. }
  691. static int ax88179_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
  692. {
  693. struct asix_private *priv = dev_get_priv(dev);
  694. struct ueth_data *ueth = &priv->ueth;
  695. if (priv->pkt_cnt == 0)
  696. usb_ether_advance_rxbuf(ueth, -1);
  697. return 0;
  698. }
  699. int ax88179_write_hwaddr(struct udevice *dev)
  700. {
  701. struct eth_pdata *pdata = dev_get_platdata(dev);
  702. struct asix_private *priv = dev_get_priv(dev);
  703. struct ueth_data *ueth = &priv->ueth;
  704. return asix_write_mac(ueth, pdata->enetaddr);
  705. }
  706. static int ax88179_eth_probe(struct udevice *dev)
  707. {
  708. struct eth_pdata *pdata = dev_get_platdata(dev);
  709. struct asix_private *priv = dev_get_priv(dev);
  710. struct usb_device *usb_dev;
  711. int ret;
  712. priv->flags = dev->driver_data;
  713. ret = usb_ether_register(dev, &priv->ueth, AX_RX_URB_SIZE);
  714. if (ret)
  715. return ret;
  716. usb_dev = priv->ueth.pusb_dev;
  717. priv->maxpacketsize = usb_dev->epmaxpacketout[AX_ENDPOINT_OUT];
  718. /* Get the MAC address */
  719. ret = asix_read_mac(&priv->ueth, pdata->enetaddr);
  720. if (ret)
  721. return ret;
  722. debug("MAC %pM\n", pdata->enetaddr);
  723. return 0;
  724. }
  725. static const struct eth_ops ax88179_eth_ops = {
  726. .start = ax88179_eth_start,
  727. .send = ax88179_eth_send,
  728. .recv = ax88179_eth_recv,
  729. .free_pkt = ax88179_free_pkt,
  730. .stop = ax88179_eth_stop,
  731. .write_hwaddr = ax88179_write_hwaddr,
  732. };
  733. U_BOOT_DRIVER(ax88179_eth) = {
  734. .name = "ax88179_eth",
  735. .id = UCLASS_ETH,
  736. .probe = ax88179_eth_probe,
  737. .ops = &ax88179_eth_ops,
  738. .priv_auto_alloc_size = sizeof(struct asix_private),
  739. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  740. };
  741. static const struct usb_device_id ax88179_eth_id_table[] = {
  742. { USB_DEVICE(0x0b95, 0x1790), .driver_info = FLAG_TYPE_AX88179 },
  743. { USB_DEVICE(0x0b95, 0x178a), .driver_info = FLAG_TYPE_AX88178a },
  744. { USB_DEVICE(0x2001, 0x4a00), .driver_info = FLAG_TYPE_DLINK_DUB1312 },
  745. { USB_DEVICE(0x0df6, 0x0072), .driver_info = FLAG_TYPE_SITECOM },
  746. { USB_DEVICE(0x04e8, 0xa100), .driver_info = FLAG_TYPE_SAMSUNG },
  747. { USB_DEVICE(0x17ef, 0x304b), .driver_info = FLAG_TYPE_LENOVO },
  748. { USB_DEVICE(0x04b4, 0x3610), .driver_info = FLAG_TYPE_GX3 },
  749. { } /* Terminating entry */
  750. };
  751. U_BOOT_USB_DEVICE(ax88179_eth, ax88179_eth_id_table);
  752. #endif /* !CONFIG_DM_ETH */