asix.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. *
  5. * Patched for AX88772B by Antmicro Ltd <www.antmicro.com>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <net.h>
  11. #include <usb.h>
  12. #include <malloc.h>
  13. #include <memalign.h>
  14. #include <linux/delay.h>
  15. #include <linux/mii.h>
  16. #include "usb_ether.h"
  17. /* ASIX AX8817X based USB 2.0 Ethernet Devices */
  18. #define AX_CMD_SET_SW_MII 0x06
  19. #define AX_CMD_READ_MII_REG 0x07
  20. #define AX_CMD_WRITE_MII_REG 0x08
  21. #define AX_CMD_SET_HW_MII 0x0a
  22. #define AX_CMD_READ_EEPROM 0x0b
  23. #define AX_CMD_READ_RX_CTL 0x0f
  24. #define AX_CMD_WRITE_RX_CTL 0x10
  25. #define AX_CMD_WRITE_IPG0 0x12
  26. #define AX_CMD_READ_NODE_ID 0x13
  27. #define AX_CMD_WRITE_NODE_ID 0x14
  28. #define AX_CMD_READ_PHY_ID 0x19
  29. #define AX_CMD_WRITE_MEDIUM_MODE 0x1b
  30. #define AX_CMD_WRITE_GPIOS 0x1f
  31. #define AX_CMD_SW_RESET 0x20
  32. #define AX_CMD_SW_PHY_SELECT 0x22
  33. #define AX_SWRESET_CLEAR 0x00
  34. #define AX_SWRESET_PRTE 0x04
  35. #define AX_SWRESET_PRL 0x08
  36. #define AX_SWRESET_IPRL 0x20
  37. #define AX_SWRESET_IPPD 0x40
  38. #define AX88772_IPG0_DEFAULT 0x15
  39. #define AX88772_IPG1_DEFAULT 0x0c
  40. #define AX88772_IPG2_DEFAULT 0x12
  41. /* AX88772 & AX88178 Medium Mode Register */
  42. #define AX_MEDIUM_PF 0x0080
  43. #define AX_MEDIUM_JFE 0x0040
  44. #define AX_MEDIUM_TFC 0x0020
  45. #define AX_MEDIUM_RFC 0x0010
  46. #define AX_MEDIUM_ENCK 0x0008
  47. #define AX_MEDIUM_AC 0x0004
  48. #define AX_MEDIUM_FD 0x0002
  49. #define AX_MEDIUM_GM 0x0001
  50. #define AX_MEDIUM_SM 0x1000
  51. #define AX_MEDIUM_SBP 0x0800
  52. #define AX_MEDIUM_PS 0x0200
  53. #define AX_MEDIUM_RE 0x0100
  54. #define AX88178_MEDIUM_DEFAULT \
  55. (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
  56. AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
  57. AX_MEDIUM_RE)
  58. #define AX88772_MEDIUM_DEFAULT \
  59. (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
  60. AX_MEDIUM_TFC | AX_MEDIUM_PS | \
  61. AX_MEDIUM_AC | AX_MEDIUM_RE)
  62. /* AX88772 & AX88178 RX_CTL values */
  63. #define AX_RX_CTL_SO 0x0080
  64. #define AX_RX_CTL_AB 0x0008
  65. #define AX_DEFAULT_RX_CTL \
  66. (AX_RX_CTL_SO | AX_RX_CTL_AB)
  67. /* GPIO 2 toggles */
  68. #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
  69. #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
  70. #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
  71. /* local defines */
  72. #define ASIX_BASE_NAME "asx"
  73. #define USB_CTRL_SET_TIMEOUT 5000
  74. #define USB_CTRL_GET_TIMEOUT 5000
  75. #define USB_BULK_SEND_TIMEOUT 5000
  76. #define USB_BULK_RECV_TIMEOUT 5000
  77. #define AX_RX_URB_SIZE 2048
  78. #define PHY_CONNECT_TIMEOUT 5000
  79. /* asix_flags defines */
  80. #define FLAG_NONE 0
  81. #define FLAG_TYPE_AX88172 (1U << 0)
  82. #define FLAG_TYPE_AX88772 (1U << 1)
  83. #define FLAG_TYPE_AX88772B (1U << 2)
  84. #define FLAG_EEPROM_MAC (1U << 3) /* initial mac address in eeprom */
  85. /* driver private */
  86. struct asix_private {
  87. int flags;
  88. #ifdef CONFIG_DM_ETH
  89. struct ueth_data ueth;
  90. #endif
  91. };
  92. #ifndef CONFIG_DM_ETH
  93. /* local vars */
  94. static int curr_eth_dev; /* index for name of next device detected */
  95. #endif
  96. /*
  97. * Asix infrastructure commands
  98. */
  99. static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
  100. u16 size, void *data)
  101. {
  102. int len;
  103. debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
  104. "size=%d\n", cmd, value, index, size);
  105. len = usb_control_msg(
  106. dev->pusb_dev,
  107. usb_sndctrlpipe(dev->pusb_dev, 0),
  108. cmd,
  109. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  110. value,
  111. index,
  112. data,
  113. size,
  114. USB_CTRL_SET_TIMEOUT);
  115. return len == size ? 0 : -1;
  116. }
  117. static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
  118. u16 size, void *data)
  119. {
  120. int len;
  121. debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
  122. cmd, value, index, size);
  123. len = usb_control_msg(
  124. dev->pusb_dev,
  125. usb_rcvctrlpipe(dev->pusb_dev, 0),
  126. cmd,
  127. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  128. value,
  129. index,
  130. data,
  131. size,
  132. USB_CTRL_GET_TIMEOUT);
  133. return len == size ? 0 : -1;
  134. }
  135. static inline int asix_set_sw_mii(struct ueth_data *dev)
  136. {
  137. int ret;
  138. ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
  139. if (ret < 0)
  140. debug("Failed to enable software MII access\n");
  141. return ret;
  142. }
  143. static inline int asix_set_hw_mii(struct ueth_data *dev)
  144. {
  145. int ret;
  146. ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
  147. if (ret < 0)
  148. debug("Failed to enable hardware MII access\n");
  149. return ret;
  150. }
  151. static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
  152. {
  153. ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
  154. asix_set_sw_mii(dev);
  155. asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res);
  156. asix_set_hw_mii(dev);
  157. debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
  158. phy_id, loc, le16_to_cpu(*res));
  159. return le16_to_cpu(*res);
  160. }
  161. static void
  162. asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
  163. {
  164. ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1);
  165. *res = cpu_to_le16(val);
  166. debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
  167. phy_id, loc, val);
  168. asix_set_sw_mii(dev);
  169. asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res);
  170. asix_set_hw_mii(dev);
  171. }
  172. /*
  173. * Asix "high level" commands
  174. */
  175. static int asix_sw_reset(struct ueth_data *dev, u8 flags)
  176. {
  177. int ret;
  178. ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
  179. if (ret < 0)
  180. debug("Failed to send software reset: %02x\n", ret);
  181. else
  182. udelay(150 * 1000);
  183. return ret;
  184. }
  185. static inline int asix_get_phy_addr(struct ueth_data *dev)
  186. {
  187. ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2);
  188. int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
  189. debug("asix_get_phy_addr()\n");
  190. if (ret < 0) {
  191. debug("Error reading PHYID register: %02x\n", ret);
  192. goto out;
  193. }
  194. debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]);
  195. ret = buf[1];
  196. out:
  197. return ret;
  198. }
  199. static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
  200. {
  201. int ret;
  202. debug("asix_write_medium_mode() - mode = 0x%04x\n", mode);
  203. ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode,
  204. 0, 0, NULL);
  205. if (ret < 0) {
  206. debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
  207. mode, ret);
  208. }
  209. return ret;
  210. }
  211. static u16 asix_read_rx_ctl(struct ueth_data *dev)
  212. {
  213. ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1);
  214. int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v);
  215. if (ret < 0)
  216. debug("Error reading RX_CTL register: %02x\n", ret);
  217. else
  218. ret = le16_to_cpu(*v);
  219. return ret;
  220. }
  221. static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode)
  222. {
  223. int ret;
  224. debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode);
  225. ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
  226. if (ret < 0) {
  227. debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
  228. mode, ret);
  229. }
  230. return ret;
  231. }
  232. static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep)
  233. {
  234. int ret;
  235. debug("asix_write_gpio() - value = 0x%04x\n", value);
  236. ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
  237. if (ret < 0) {
  238. debug("Failed to write GPIO value 0x%04x: %02x\n",
  239. value, ret);
  240. }
  241. if (sleep)
  242. udelay(sleep * 1000);
  243. return ret;
  244. }
  245. static int asix_write_hwaddr_common(struct ueth_data *dev, uint8_t *enetaddr)
  246. {
  247. int ret;
  248. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
  249. memcpy(buf, enetaddr, ETH_ALEN);
  250. ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, buf);
  251. if (ret < 0)
  252. debug("Failed to set MAC address: %02x\n", ret);
  253. return ret;
  254. }
  255. /*
  256. * mii commands
  257. */
  258. /*
  259. * mii_nway_restart - restart NWay (autonegotiation) for this interface
  260. *
  261. * Returns 0 on success, negative on error.
  262. */
  263. static int mii_nway_restart(struct ueth_data *dev)
  264. {
  265. int bmcr;
  266. int r = -1;
  267. /* if autoneg is off, it's an error */
  268. bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR);
  269. if (bmcr & BMCR_ANENABLE) {
  270. bmcr |= BMCR_ANRESTART;
  271. asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
  272. r = 0;
  273. }
  274. return r;
  275. }
  276. static int asix_read_mac_common(struct ueth_data *dev,
  277. struct asix_private *priv, uint8_t *enetaddr)
  278. {
  279. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN);
  280. int i;
  281. if (priv->flags & FLAG_EEPROM_MAC) {
  282. for (i = 0; i < (ETH_ALEN >> 1); i++) {
  283. if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
  284. 0x04 + i, 0, 2, buf) < 0) {
  285. debug("Failed to read SROM address 04h.\n");
  286. return -1;
  287. }
  288. memcpy(enetaddr + i * 2, buf, 2);
  289. }
  290. } else {
  291. if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf)
  292. < 0) {
  293. debug("Failed to read MAC address.\n");
  294. return -1;
  295. }
  296. memcpy(enetaddr, buf, ETH_ALEN);
  297. }
  298. return 0;
  299. }
  300. static int asix_basic_reset(struct ueth_data *dev)
  301. {
  302. int embd_phy;
  303. u16 rx_ctl;
  304. if (asix_write_gpio(dev,
  305. AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0)
  306. return -1;
  307. /* 0x10 is the phy id of the embedded 10/100 ethernet phy */
  308. embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
  309. if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
  310. embd_phy, 0, 0, NULL) < 0) {
  311. debug("Select PHY #1 failed\n");
  312. return -1;
  313. }
  314. if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0)
  315. return -1;
  316. if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0)
  317. return -1;
  318. if (embd_phy) {
  319. if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0)
  320. return -1;
  321. } else {
  322. if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0)
  323. return -1;
  324. }
  325. rx_ctl = asix_read_rx_ctl(dev);
  326. debug("RX_CTL is 0x%04x after software reset\n", rx_ctl);
  327. if (asix_write_rx_ctl(dev, 0x0000) < 0)
  328. return -1;
  329. rx_ctl = asix_read_rx_ctl(dev);
  330. debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
  331. dev->phy_id = asix_get_phy_addr(dev);
  332. if (dev->phy_id < 0)
  333. debug("Failed to read phy id\n");
  334. asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
  335. asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
  336. ADVERTISE_ALL | ADVERTISE_CSMA);
  337. mii_nway_restart(dev);
  338. if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
  339. return -1;
  340. if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
  341. AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
  342. AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
  343. debug("Write IPG,IPG1,IPG2 failed\n");
  344. return -1;
  345. }
  346. return 0;
  347. }
  348. static int asix_init_common(struct ueth_data *dev, uint8_t *enetaddr)
  349. {
  350. int timeout = 0;
  351. #define TIMEOUT_RESOLUTION 50 /* ms */
  352. int link_detected;
  353. debug("** %s()\n", __func__);
  354. if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
  355. goto out_err;
  356. if (asix_write_hwaddr_common(dev, enetaddr) < 0)
  357. goto out_err;
  358. do {
  359. link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) &
  360. BMSR_LSTATUS;
  361. if (!link_detected) {
  362. if (timeout == 0)
  363. printf("Waiting for Ethernet connection... ");
  364. udelay(TIMEOUT_RESOLUTION * 1000);
  365. timeout += TIMEOUT_RESOLUTION;
  366. }
  367. } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
  368. if (link_detected) {
  369. if (timeout != 0)
  370. printf("done.\n");
  371. } else {
  372. printf("unable to connect.\n");
  373. goto out_err;
  374. }
  375. /*
  376. * Wait some more to avoid timeout on first transfer
  377. * (e.g. EHCI timed out on TD - token=0x8008d80)
  378. */
  379. mdelay(25);
  380. return 0;
  381. out_err:
  382. return -1;
  383. }
  384. static int asix_send_common(struct ueth_data *dev, void *packet, int length)
  385. {
  386. int err;
  387. u32 packet_len;
  388. int actual_len;
  389. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
  390. PKTSIZE + sizeof(packet_len));
  391. debug("** %s(), len %d\n", __func__, length);
  392. packet_len = (((length) ^ 0x0000ffff) << 16) + (length);
  393. cpu_to_le32s(&packet_len);
  394. memcpy(msg, &packet_len, sizeof(packet_len));
  395. memcpy(msg + sizeof(packet_len), (void *)packet, length);
  396. err = usb_bulk_msg(dev->pusb_dev,
  397. usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
  398. (void *)msg,
  399. length + sizeof(packet_len),
  400. &actual_len,
  401. USB_BULK_SEND_TIMEOUT);
  402. debug("Tx: len = %zu, actual = %u, err = %d\n",
  403. length + sizeof(packet_len), actual_len, err);
  404. return err;
  405. }
  406. #ifndef CONFIG_DM_ETH
  407. /*
  408. * Asix callbacks
  409. */
  410. static int asix_init(struct eth_device *eth, struct bd_info *bd)
  411. {
  412. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  413. return asix_init_common(dev, eth->enetaddr);
  414. }
  415. static int asix_send(struct eth_device *eth, void *packet, int length)
  416. {
  417. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  418. return asix_send_common(dev, packet, length);
  419. }
  420. static int asix_recv(struct eth_device *eth)
  421. {
  422. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  423. ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
  424. unsigned char *buf_ptr;
  425. int err;
  426. int actual_len;
  427. u32 packet_len;
  428. debug("** %s()\n", __func__);
  429. err = usb_bulk_msg(dev->pusb_dev,
  430. usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
  431. (void *)recv_buf,
  432. AX_RX_URB_SIZE,
  433. &actual_len,
  434. USB_BULK_RECV_TIMEOUT);
  435. debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
  436. actual_len, err);
  437. if (err != 0) {
  438. debug("Rx: failed to receive\n");
  439. return -1;
  440. }
  441. if (actual_len > AX_RX_URB_SIZE) {
  442. debug("Rx: received too many bytes %d\n", actual_len);
  443. return -1;
  444. }
  445. buf_ptr = recv_buf;
  446. while (actual_len > 0) {
  447. /*
  448. * 1st 4 bytes contain the length of the actual data as two
  449. * complementary 16-bit words. Extract the length of the data.
  450. */
  451. if (actual_len < sizeof(packet_len)) {
  452. debug("Rx: incomplete packet length\n");
  453. return -1;
  454. }
  455. memcpy(&packet_len, buf_ptr, sizeof(packet_len));
  456. le32_to_cpus(&packet_len);
  457. if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
  458. debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
  459. packet_len, (~packet_len >> 16) & 0x7ff,
  460. packet_len & 0x7ff);
  461. return -1;
  462. }
  463. packet_len = packet_len & 0x7ff;
  464. if (packet_len > actual_len - sizeof(packet_len)) {
  465. debug("Rx: too large packet: %d\n", packet_len);
  466. return -1;
  467. }
  468. /* Notify net stack */
  469. net_process_received_packet(buf_ptr + sizeof(packet_len),
  470. packet_len);
  471. /* Adjust for next iteration. Packets are padded to 16-bits */
  472. if (packet_len & 1)
  473. packet_len++;
  474. actual_len -= sizeof(packet_len) + packet_len;
  475. buf_ptr += sizeof(packet_len) + packet_len;
  476. }
  477. return err;
  478. }
  479. static void asix_halt(struct eth_device *eth)
  480. {
  481. debug("** %s()\n", __func__);
  482. }
  483. static int asix_write_hwaddr(struct eth_device *eth)
  484. {
  485. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  486. return asix_write_hwaddr_common(dev, eth->enetaddr);
  487. }
  488. /*
  489. * Asix probing functions
  490. */
  491. void asix_eth_before_probe(void)
  492. {
  493. curr_eth_dev = 0;
  494. }
  495. struct asix_dongle {
  496. unsigned short vendor;
  497. unsigned short product;
  498. int flags;
  499. };
  500. static const struct asix_dongle asix_dongles[] = {
  501. { 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */
  502. { 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */
  503. { 0x2001, 0x1a02, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver C1 */
  504. /* Cables-to-Go USB Ethernet Adapter */
  505. { 0x0b95, 0x772a, FLAG_TYPE_AX88772 },
  506. { 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */
  507. { 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */
  508. { 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */
  509. { 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */
  510. { 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */
  511. /* DLink DUB-E100 H/W Ver B1 Alternate */
  512. { 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
  513. /* ASIX 88772B */
  514. { 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
  515. { 0x0b95, 0x7e2b, FLAG_TYPE_AX88772B },
  516. { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
  517. };
  518. /* Probe to see if a new device is actually an asix device */
  519. int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
  520. struct ueth_data *ss)
  521. {
  522. struct usb_interface *iface;
  523. struct usb_interface_descriptor *iface_desc;
  524. int ep_in_found = 0, ep_out_found = 0;
  525. int i;
  526. /* let's examine the device now */
  527. iface = &dev->config.if_desc[ifnum];
  528. iface_desc = &dev->config.if_desc[ifnum].desc;
  529. for (i = 0; asix_dongles[i].vendor != 0; i++) {
  530. if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
  531. dev->descriptor.idProduct == asix_dongles[i].product)
  532. /* Found a supported dongle */
  533. break;
  534. }
  535. if (asix_dongles[i].vendor == 0)
  536. return 0;
  537. memset(ss, 0, sizeof(struct ueth_data));
  538. /* At this point, we know we've got a live one */
  539. debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
  540. dev->descriptor.idVendor, dev->descriptor.idProduct);
  541. /* Initialize the ueth_data structure with some useful info */
  542. ss->ifnum = ifnum;
  543. ss->pusb_dev = dev;
  544. ss->subclass = iface_desc->bInterfaceSubClass;
  545. ss->protocol = iface_desc->bInterfaceProtocol;
  546. /* alloc driver private */
  547. ss->dev_priv = calloc(1, sizeof(struct asix_private));
  548. if (!ss->dev_priv)
  549. return 0;
  550. ((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags;
  551. /*
  552. * We are expecting a minimum of 3 endpoints - in, out (bulk), and
  553. * int. We will ignore any others.
  554. */
  555. for (i = 0; i < iface_desc->bNumEndpoints; i++) {
  556. /* is it an BULK endpoint? */
  557. if ((iface->ep_desc[i].bmAttributes &
  558. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
  559. u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
  560. if (ep_addr & USB_DIR_IN) {
  561. if (!ep_in_found) {
  562. ss->ep_in = ep_addr &
  563. USB_ENDPOINT_NUMBER_MASK;
  564. ep_in_found = 1;
  565. }
  566. } else {
  567. if (!ep_out_found) {
  568. ss->ep_out = ep_addr &
  569. USB_ENDPOINT_NUMBER_MASK;
  570. ep_out_found = 1;
  571. }
  572. }
  573. }
  574. /* is it an interrupt endpoint? */
  575. if ((iface->ep_desc[i].bmAttributes &
  576. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
  577. ss->ep_int = iface->ep_desc[i].bEndpointAddress &
  578. USB_ENDPOINT_NUMBER_MASK;
  579. ss->irqinterval = iface->ep_desc[i].bInterval;
  580. }
  581. }
  582. debug("Endpoints In %d Out %d Int %d\n",
  583. ss->ep_in, ss->ep_out, ss->ep_int);
  584. /* Do some basic sanity checks, and bail if we find a problem */
  585. if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
  586. !ss->ep_in || !ss->ep_out || !ss->ep_int) {
  587. debug("Problems with device\n");
  588. return 0;
  589. }
  590. dev->privptr = (void *)ss;
  591. return 1;
  592. }
  593. int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
  594. struct eth_device *eth)
  595. {
  596. struct asix_private *priv = (struct asix_private *)ss->dev_priv;
  597. if (!eth) {
  598. debug("%s: missing parameter.\n", __func__);
  599. return 0;
  600. }
  601. sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
  602. eth->init = asix_init;
  603. eth->send = asix_send;
  604. eth->recv = asix_recv;
  605. eth->halt = asix_halt;
  606. if (!(priv->flags & FLAG_TYPE_AX88172))
  607. eth->write_hwaddr = asix_write_hwaddr;
  608. eth->priv = ss;
  609. if (asix_basic_reset(ss))
  610. return 0;
  611. /* Get the MAC address */
  612. if (asix_read_mac_common(ss, priv, eth->enetaddr))
  613. return 0;
  614. debug("MAC %pM\n", eth->enetaddr);
  615. return 1;
  616. }
  617. #endif
  618. #ifdef CONFIG_DM_ETH
  619. static int asix_eth_start(struct udevice *dev)
  620. {
  621. struct eth_pdata *pdata = dev_get_platdata(dev);
  622. struct asix_private *priv = dev_get_priv(dev);
  623. return asix_init_common(&priv->ueth, pdata->enetaddr);
  624. }
  625. void asix_eth_stop(struct udevice *dev)
  626. {
  627. debug("** %s()\n", __func__);
  628. }
  629. int asix_eth_send(struct udevice *dev, void *packet, int length)
  630. {
  631. struct asix_private *priv = dev_get_priv(dev);
  632. return asix_send_common(&priv->ueth, packet, length);
  633. }
  634. int asix_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  635. {
  636. struct asix_private *priv = dev_get_priv(dev);
  637. struct ueth_data *ueth = &priv->ueth;
  638. uint8_t *ptr;
  639. int ret, len;
  640. u32 packet_len;
  641. len = usb_ether_get_rx_bytes(ueth, &ptr);
  642. debug("%s: first try, len=%d\n", __func__, len);
  643. if (!len) {
  644. if (!(flags & ETH_RECV_CHECK_DEVICE))
  645. return -EAGAIN;
  646. ret = usb_ether_receive(ueth, AX_RX_URB_SIZE);
  647. if (ret == -EAGAIN)
  648. return ret;
  649. len = usb_ether_get_rx_bytes(ueth, &ptr);
  650. debug("%s: second try, len=%d\n", __func__, len);
  651. }
  652. /*
  653. * 1st 4 bytes contain the length of the actual data as two
  654. * complementary 16-bit words. Extract the length of the data.
  655. */
  656. if (len < sizeof(packet_len)) {
  657. debug("Rx: incomplete packet length\n");
  658. goto err;
  659. }
  660. memcpy(&packet_len, ptr, sizeof(packet_len));
  661. le32_to_cpus(&packet_len);
  662. if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
  663. debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
  664. packet_len, (~packet_len >> 16) & 0x7ff,
  665. packet_len & 0x7ff);
  666. goto err;
  667. }
  668. packet_len = packet_len & 0x7ff;
  669. if (packet_len > len - sizeof(packet_len)) {
  670. debug("Rx: too large packet: %d\n", packet_len);
  671. goto err;
  672. }
  673. *packetp = ptr + sizeof(packet_len);
  674. return packet_len;
  675. err:
  676. usb_ether_advance_rxbuf(ueth, -1);
  677. return -EINVAL;
  678. }
  679. static int asix_free_pkt(struct udevice *dev, uchar *packet, int packet_len)
  680. {
  681. struct asix_private *priv = dev_get_priv(dev);
  682. if (packet_len & 1)
  683. packet_len++;
  684. usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len);
  685. return 0;
  686. }
  687. int asix_write_hwaddr(struct udevice *dev)
  688. {
  689. struct eth_pdata *pdata = dev_get_platdata(dev);
  690. struct asix_private *priv = dev_get_priv(dev);
  691. if (priv->flags & FLAG_TYPE_AX88172)
  692. return -ENOSYS;
  693. return asix_write_hwaddr_common(&priv->ueth, pdata->enetaddr);
  694. }
  695. static int asix_eth_probe(struct udevice *dev)
  696. {
  697. struct eth_pdata *pdata = dev_get_platdata(dev);
  698. struct asix_private *priv = dev_get_priv(dev);
  699. struct ueth_data *ss = &priv->ueth;
  700. int ret;
  701. priv->flags = dev->driver_data;
  702. ret = usb_ether_register(dev, ss, AX_RX_URB_SIZE);
  703. if (ret)
  704. return ret;
  705. ret = asix_basic_reset(ss);
  706. if (ret)
  707. goto err;
  708. /* Get the MAC address */
  709. ret = asix_read_mac_common(ss, priv, pdata->enetaddr);
  710. if (ret)
  711. goto err;
  712. debug("MAC %pM\n", pdata->enetaddr);
  713. return 0;
  714. err:
  715. return usb_ether_deregister(ss);
  716. }
  717. static const struct eth_ops asix_eth_ops = {
  718. .start = asix_eth_start,
  719. .send = asix_eth_send,
  720. .recv = asix_eth_recv,
  721. .free_pkt = asix_free_pkt,
  722. .stop = asix_eth_stop,
  723. .write_hwaddr = asix_write_hwaddr,
  724. };
  725. U_BOOT_DRIVER(asix_eth) = {
  726. .name = "asix_eth",
  727. .id = UCLASS_ETH,
  728. .probe = asix_eth_probe,
  729. .ops = &asix_eth_ops,
  730. .priv_auto_alloc_size = sizeof(struct asix_private),
  731. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  732. };
  733. static const struct usb_device_id asix_eth_id_table[] = {
  734. /* Apple USB Ethernet Adapter */
  735. { USB_DEVICE(0x05ac, 0x1402), .driver_info = FLAG_TYPE_AX88772 },
  736. /* D-Link DUB-E100 H/W Ver B1 */
  737. { USB_DEVICE(0x07d1, 0x3c05), .driver_info = FLAG_TYPE_AX88772 },
  738. /* D-Link DUB-E100 H/W Ver C1 */
  739. { USB_DEVICE(0x2001, 0x1a02), .driver_info = FLAG_TYPE_AX88772 },
  740. /* Cables-to-Go USB Ethernet Adapter */
  741. { USB_DEVICE(0x0b95, 0x772a), .driver_info = FLAG_TYPE_AX88772 },
  742. /* Trendnet TU2-ET100 V3.0R */
  743. { USB_DEVICE(0x0b95, 0x7720), .driver_info = FLAG_TYPE_AX88772 },
  744. /* SMC */
  745. { USB_DEVICE(0x0b95, 0x1720), .driver_info = FLAG_TYPE_AX88172 },
  746. /* MSI - ASIX 88772a */
  747. { USB_DEVICE(0x0db0, 0xa877), .driver_info = FLAG_TYPE_AX88772 },
  748. /* Linksys 200M v2.1 */
  749. { USB_DEVICE(0x13b1, 0x0018), .driver_info = FLAG_TYPE_AX88172 },
  750. /* 0Q0 cable ethernet */
  751. { USB_DEVICE(0x1557, 0x7720), .driver_info = FLAG_TYPE_AX88772 },
  752. /* DLink DUB-E100 H/W Ver B1 Alternate */
  753. { USB_DEVICE(0x2001, 0x3c05), .driver_info = FLAG_TYPE_AX88772 },
  754. /* ASIX 88772B */
  755. { USB_DEVICE(0x0b95, 0x772b),
  756. .driver_info = FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
  757. { USB_DEVICE(0x0b95, 0x7e2b), .driver_info = FLAG_TYPE_AX88772B },
  758. { } /* Terminating entry */
  759. };
  760. U_BOOT_USB_DEVICE(asix_eth, asix_eth_id_table);
  761. #endif