ufs.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. #ifndef __UFS_H
  3. #define __UFS_H
  4. #include "unipro.h"
  5. struct udevice;
  6. #define UFS_CDB_SIZE 16
  7. #define UPIU_TRANSACTION_UIC_CMD 0x1F
  8. #define UIC_CMD_SIZE (sizeof(u32) * 4)
  9. #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
  10. #define UFS_MAX_LUNS 0x7F
  11. enum {
  12. TASK_REQ_UPIU_SIZE_DWORDS = 8,
  13. TASK_RSP_UPIU_SIZE_DWORDS = 8,
  14. ALIGNED_UPIU_SIZE = 512,
  15. };
  16. /* UFS device power modes */
  17. enum ufs_dev_pwr_mode {
  18. UFS_ACTIVE_PWR_MODE = 1,
  19. UFS_SLEEP_PWR_MODE = 2,
  20. UFS_POWERDOWN_PWR_MODE = 3,
  21. };
  22. enum ufs_notify_change_status {
  23. PRE_CHANGE,
  24. POST_CHANGE,
  25. };
  26. struct ufs_pa_layer_attr {
  27. u32 gear_rx;
  28. u32 gear_tx;
  29. u32 lane_rx;
  30. u32 lane_tx;
  31. u32 pwr_rx;
  32. u32 pwr_tx;
  33. u32 hs_rate;
  34. };
  35. struct ufs_pwr_mode_info {
  36. bool is_valid;
  37. struct ufs_pa_layer_attr info;
  38. };
  39. enum ufs_desc_def_size {
  40. QUERY_DESC_DEVICE_DEF_SIZE = 0x40,
  41. QUERY_DESC_CONFIGURATION_DEF_SIZE = 0x90,
  42. QUERY_DESC_UNIT_DEF_SIZE = 0x23,
  43. QUERY_DESC_INTERCONNECT_DEF_SIZE = 0x06,
  44. QUERY_DESC_GEOMETRY_DEF_SIZE = 0x48,
  45. QUERY_DESC_POWER_DEF_SIZE = 0x62,
  46. QUERY_DESC_HEALTH_DEF_SIZE = 0x25,
  47. };
  48. struct ufs_desc_size {
  49. int dev_desc;
  50. int pwr_desc;
  51. int geom_desc;
  52. int interc_desc;
  53. int unit_desc;
  54. int conf_desc;
  55. int hlth_desc;
  56. };
  57. /*
  58. * Request Descriptor Definitions
  59. */
  60. /* Transfer request command type */
  61. enum {
  62. UTP_CMD_TYPE_SCSI = 0x0,
  63. UTP_CMD_TYPE_UFS = 0x1,
  64. UTP_CMD_TYPE_DEV_MANAGE = 0x2,
  65. };
  66. /* UTP Transfer Request Command Offset */
  67. #define UPIU_COMMAND_TYPE_OFFSET 28
  68. /* Offset of the response code in the UPIU header */
  69. #define UPIU_RSP_CODE_OFFSET 8
  70. /* To accommodate UFS2.0 required Command type */
  71. enum {
  72. UTP_CMD_TYPE_UFS_STORAGE = 0x1,
  73. };
  74. enum {
  75. UTP_SCSI_COMMAND = 0x00000000,
  76. UTP_NATIVE_UFS_COMMAND = 0x10000000,
  77. UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
  78. UTP_REQ_DESC_INT_CMD = 0x01000000,
  79. };
  80. /* UTP Transfer Request Data Direction (DD) */
  81. enum {
  82. UTP_NO_DATA_TRANSFER = 0x00000000,
  83. UTP_HOST_TO_DEVICE = 0x02000000,
  84. UTP_DEVICE_TO_HOST = 0x04000000,
  85. };
  86. /* Overall command status values */
  87. enum {
  88. OCS_SUCCESS = 0x0,
  89. OCS_INVALID_CMD_TABLE_ATTR = 0x1,
  90. OCS_INVALID_PRDT_ATTR = 0x2,
  91. OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
  92. OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
  93. OCS_PEER_COMM_FAILURE = 0x5,
  94. OCS_ABORTED = 0x6,
  95. OCS_FATAL_ERROR = 0x7,
  96. OCS_INVALID_COMMAND_STATUS = 0x0F,
  97. MASK_OCS = 0x0F,
  98. };
  99. /* The maximum length of the data byte count field in the PRDT is 256KB */
  100. #define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
  101. /* The granularity of the data byte count field in the PRDT is 32-bit */
  102. #define PRDT_DATA_BYTE_COUNT_PAD 4
  103. #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
  104. #define QUERY_DESC_MAX_SIZE 255
  105. #define QUERY_DESC_MIN_SIZE 2
  106. #define QUERY_DESC_HDR_SIZE 2
  107. #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
  108. (sizeof(struct utp_upiu_header)))
  109. #define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
  110. #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
  111. cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
  112. (byte1 << 8) | (byte0))
  113. /*
  114. * UFS Protocol Information Unit related definitions
  115. */
  116. /* Task management functions */
  117. enum {
  118. UFS_ABORT_TASK = 0x01,
  119. UFS_ABORT_TASK_SET = 0x02,
  120. UFS_CLEAR_TASK_SET = 0x04,
  121. UFS_LOGICAL_RESET = 0x08,
  122. UFS_QUERY_TASK = 0x80,
  123. UFS_QUERY_TASK_SET = 0x81,
  124. };
  125. /* UTP UPIU Transaction Codes Initiator to Target */
  126. enum {
  127. UPIU_TRANSACTION_NOP_OUT = 0x00,
  128. UPIU_TRANSACTION_COMMAND = 0x01,
  129. UPIU_TRANSACTION_DATA_OUT = 0x02,
  130. UPIU_TRANSACTION_TASK_REQ = 0x04,
  131. UPIU_TRANSACTION_QUERY_REQ = 0x16,
  132. };
  133. /* UTP UPIU Transaction Codes Target to Initiator */
  134. enum {
  135. UPIU_TRANSACTION_NOP_IN = 0x20,
  136. UPIU_TRANSACTION_RESPONSE = 0x21,
  137. UPIU_TRANSACTION_DATA_IN = 0x22,
  138. UPIU_TRANSACTION_TASK_RSP = 0x24,
  139. UPIU_TRANSACTION_READY_XFER = 0x31,
  140. UPIU_TRANSACTION_QUERY_RSP = 0x36,
  141. UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
  142. };
  143. /* UPIU Read/Write flags */
  144. enum {
  145. UPIU_CMD_FLAGS_NONE = 0x00,
  146. UPIU_CMD_FLAGS_WRITE = 0x20,
  147. UPIU_CMD_FLAGS_READ = 0x40,
  148. };
  149. /* UPIU Task Attributes */
  150. enum {
  151. UPIU_TASK_ATTR_SIMPLE = 0x00,
  152. UPIU_TASK_ATTR_ORDERED = 0x01,
  153. UPIU_TASK_ATTR_HEADQ = 0x02,
  154. UPIU_TASK_ATTR_ACA = 0x03,
  155. };
  156. /* UPIU Query request function */
  157. enum {
  158. UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
  159. UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
  160. };
  161. /* Offset of the response code in the UPIU header */
  162. #define UPIU_RSP_CODE_OFFSET 8
  163. enum {
  164. MASK_SCSI_STATUS = 0xFF,
  165. MASK_TASK_RESPONSE = 0xFF00,
  166. MASK_RSP_UPIU_RESULT = 0xFFFF,
  167. MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
  168. MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
  169. MASK_RSP_EXCEPTION_EVENT = 0x10000,
  170. MASK_TM_SERVICE_RESP = 0xFF,
  171. MASK_TM_FUNC = 0xFF,
  172. };
  173. /* UTP QUERY Transaction Specific Fields OpCode */
  174. enum query_opcode {
  175. UPIU_QUERY_OPCODE_NOP = 0x0,
  176. UPIU_QUERY_OPCODE_READ_DESC = 0x1,
  177. UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
  178. UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
  179. UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
  180. UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
  181. UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
  182. UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
  183. UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
  184. };
  185. /* Query response result code */
  186. enum {
  187. QUERY_RESULT_SUCCESS = 0x00,
  188. QUERY_RESULT_NOT_READABLE = 0xF6,
  189. QUERY_RESULT_NOT_WRITEABLE = 0xF7,
  190. QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
  191. QUERY_RESULT_INVALID_LENGTH = 0xF9,
  192. QUERY_RESULT_INVALID_VALUE = 0xFA,
  193. QUERY_RESULT_INVALID_SELECTOR = 0xFB,
  194. QUERY_RESULT_INVALID_INDEX = 0xFC,
  195. QUERY_RESULT_INVALID_IDN = 0xFD,
  196. QUERY_RESULT_INVALID_OPCODE = 0xFE,
  197. QUERY_RESULT_GENERAL_FAILURE = 0xFF,
  198. };
  199. enum {
  200. UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
  201. UPIU_COMMAND_SET_TYPE_UFS = 0x1,
  202. UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
  203. };
  204. /* Flag idn for Query Requests*/
  205. enum flag_idn {
  206. QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
  207. QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
  208. QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
  209. QUERY_FLAG_IDN_BKOPS_EN = 0x04,
  210. QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
  211. QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
  212. QUERY_FLAG_IDN_RESERVED2 = 0x07,
  213. QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
  214. QUERY_FLAG_IDN_BUSY_RTC = 0x09,
  215. QUERY_FLAG_IDN_RESERVED3 = 0x0A,
  216. QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
  217. };
  218. /* Attribute idn for Query requests */
  219. enum attr_idn {
  220. QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
  221. QUERY_ATTR_IDN_RESERVED = 0x01,
  222. QUERY_ATTR_IDN_POWER_MODE = 0x02,
  223. QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
  224. QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
  225. QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
  226. QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
  227. QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
  228. QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
  229. QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
  230. QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
  231. QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
  232. QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
  233. QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
  234. QUERY_ATTR_IDN_EE_STATUS = 0x0E,
  235. QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
  236. QUERY_ATTR_IDN_CNTX_CONF = 0x10,
  237. QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
  238. QUERY_ATTR_IDN_RESERVED2 = 0x12,
  239. QUERY_ATTR_IDN_RESERVED3 = 0x13,
  240. QUERY_ATTR_IDN_FFU_STATUS = 0x14,
  241. QUERY_ATTR_IDN_PSA_STATE = 0x15,
  242. QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
  243. };
  244. /* Descriptor idn for Query requests */
  245. enum desc_idn {
  246. QUERY_DESC_IDN_DEVICE = 0x0,
  247. QUERY_DESC_IDN_CONFIGURATION = 0x1,
  248. QUERY_DESC_IDN_UNIT = 0x2,
  249. QUERY_DESC_IDN_RFU_0 = 0x3,
  250. QUERY_DESC_IDN_INTERCONNECT = 0x4,
  251. QUERY_DESC_IDN_STRING = 0x5,
  252. QUERY_DESC_IDN_RFU_1 = 0x6,
  253. QUERY_DESC_IDN_GEOMETRY = 0x7,
  254. QUERY_DESC_IDN_POWER = 0x8,
  255. QUERY_DESC_IDN_HEALTH = 0x9,
  256. QUERY_DESC_IDN_MAX,
  257. };
  258. enum desc_header_offset {
  259. QUERY_DESC_LENGTH_OFFSET = 0x00,
  260. QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
  261. };
  262. struct ufshcd_sg_entry {
  263. __le32 base_addr;
  264. __le32 upper_addr;
  265. __le32 reserved;
  266. __le32 size;
  267. };
  268. #define MAX_BUFF 128
  269. /**
  270. * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
  271. * @command_upiu: Command UPIU Frame address
  272. * @response_upiu: Response UPIU Frame address
  273. * @prd_table: Physical Region Descriptor
  274. */
  275. struct utp_transfer_cmd_desc {
  276. u8 command_upiu[ALIGNED_UPIU_SIZE];
  277. u8 response_upiu[ALIGNED_UPIU_SIZE];
  278. struct ufshcd_sg_entry prd_table[MAX_BUFF];
  279. };
  280. /**
  281. * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
  282. * @dword0: Descriptor Header DW0
  283. * @dword1: Descriptor Header DW1
  284. * @dword2: Descriptor Header DW2
  285. * @dword3: Descriptor Header DW3
  286. */
  287. struct request_desc_header {
  288. __le32 dword_0;
  289. __le32 dword_1;
  290. __le32 dword_2;
  291. __le32 dword_3;
  292. };
  293. /**
  294. * struct utp_transfer_req_desc - UTRD structure
  295. * @header: UTRD header DW-0 to DW-3
  296. * @command_desc_base_addr_lo: UCD base address low DW-4
  297. * @command_desc_base_addr_hi: UCD base address high DW-5
  298. * @response_upiu_length: response UPIU length DW-6
  299. * @response_upiu_offset: response UPIU offset DW-6
  300. * @prd_table_length: Physical region descriptor length DW-7
  301. * @prd_table_offset: Physical region descriptor offset DW-7
  302. */
  303. struct utp_transfer_req_desc {
  304. /* DW 0-3 */
  305. struct request_desc_header header;
  306. /* DW 4-5*/
  307. __le32 command_desc_base_addr_lo;
  308. __le32 command_desc_base_addr_hi;
  309. /* DW 6 */
  310. __le16 response_upiu_length;
  311. __le16 response_upiu_offset;
  312. /* DW 7 */
  313. __le16 prd_table_length;
  314. __le16 prd_table_offset;
  315. };
  316. /**
  317. * struct utp_upiu_header - UPIU header structure
  318. * @dword_0: UPIU header DW-0
  319. * @dword_1: UPIU header DW-1
  320. * @dword_2: UPIU header DW-2
  321. */
  322. struct utp_upiu_header {
  323. __be32 dword_0;
  324. __be32 dword_1;
  325. __be32 dword_2;
  326. };
  327. /**
  328. * struct utp_upiu_query - upiu request buffer structure for
  329. * query request.
  330. * @opcode: command to perform B-0
  331. * @idn: a value that indicates the particular type of data B-1
  332. * @index: Index to further identify data B-2
  333. * @selector: Index to further identify data B-3
  334. * @reserved_osf: spec reserved field B-4,5
  335. * @length: number of descriptor bytes to read/write B-6,7
  336. * @value: Attribute value to be written DW-5
  337. * @reserved: spec reserved DW-6,7
  338. */
  339. struct utp_upiu_query {
  340. __u8 opcode;
  341. __u8 idn;
  342. __u8 index;
  343. __u8 selector;
  344. __be16 reserved_osf;
  345. __be16 length;
  346. __be32 value;
  347. __be32 reserved[2];
  348. };
  349. /**
  350. * struct utp_upiu_cmd - Command UPIU structure
  351. * @data_transfer_len: Data Transfer Length DW-3
  352. * @cdb: Command Descriptor Block CDB DW-4 to DW-7
  353. */
  354. struct utp_upiu_cmd {
  355. __be32 exp_data_transfer_len;
  356. u8 cdb[UFS_CDB_SIZE];
  357. };
  358. /*
  359. * UTMRD structure.
  360. */
  361. struct utp_task_req_desc {
  362. /* DW 0-3 */
  363. struct request_desc_header header;
  364. /* DW 4-11 - Task request UPIU structure */
  365. struct utp_upiu_header req_header;
  366. __be32 input_param1;
  367. __be32 input_param2;
  368. __be32 input_param3;
  369. __be32 __reserved1[2];
  370. /* DW 12-19 - Task Management Response UPIU structure */
  371. struct utp_upiu_header rsp_header;
  372. __be32 output_param1;
  373. __be32 output_param2;
  374. __be32 __reserved2[3];
  375. };
  376. /**
  377. * struct utp_upiu_req - general upiu request structure
  378. * @header:UPIU header structure DW-0 to DW-2
  379. * @sc: fields structure for scsi command DW-3 to DW-7
  380. * @qr: fields structure for query request DW-3 to DW-7
  381. */
  382. struct utp_upiu_req {
  383. struct utp_upiu_header header;
  384. union {
  385. struct utp_upiu_cmd sc;
  386. struct utp_upiu_query qr;
  387. struct utp_upiu_query tr;
  388. /* use utp_upiu_query to host the 4 dwords of uic command */
  389. struct utp_upiu_query uc;
  390. };
  391. };
  392. /**
  393. * struct utp_cmd_rsp - Response UPIU structure
  394. * @residual_transfer_count: Residual transfer count DW-3
  395. * @reserved: Reserved double words DW-4 to DW-7
  396. * @sense_data_len: Sense data length DW-8 U16
  397. * @sense_data: Sense data field DW-8 to DW-12
  398. */
  399. struct utp_cmd_rsp {
  400. __be32 residual_transfer_count;
  401. __be32 reserved[4];
  402. __be16 sense_data_len;
  403. u8 sense_data[RESPONSE_UPIU_SENSE_DATA_LENGTH];
  404. };
  405. /**
  406. * struct utp_upiu_rsp - general upiu response structure
  407. * @header: UPIU header structure DW-0 to DW-2
  408. * @sr: fields structure for scsi command DW-3 to DW-12
  409. * @qr: fields structure for query request DW-3 to DW-7
  410. */
  411. struct utp_upiu_rsp {
  412. struct utp_upiu_header header;
  413. union {
  414. struct utp_cmd_rsp sr;
  415. struct utp_upiu_query qr;
  416. };
  417. };
  418. #define MAX_MODEL_LEN 16
  419. /**
  420. * ufs_dev_desc - ufs device details from the device descriptor
  421. *
  422. * @wmanufacturerid: card details
  423. * @model: card model
  424. */
  425. struct ufs_dev_desc {
  426. u16 wmanufacturerid;
  427. char model[MAX_MODEL_LEN + 1];
  428. };
  429. /* Device descriptor parameters offsets in bytes*/
  430. enum device_desc_param {
  431. DEVICE_DESC_PARAM_LEN = 0x0,
  432. DEVICE_DESC_PARAM_TYPE = 0x1,
  433. DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
  434. DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
  435. DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
  436. DEVICE_DESC_PARAM_PRTCL = 0x5,
  437. DEVICE_DESC_PARAM_NUM_LU = 0x6,
  438. DEVICE_DESC_PARAM_NUM_WLU = 0x7,
  439. DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
  440. DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
  441. DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
  442. DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
  443. DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
  444. DEVICE_DESC_PARAM_SEC_LU = 0xD,
  445. DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
  446. DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
  447. DEVICE_DESC_PARAM_SPEC_VER = 0x10,
  448. DEVICE_DESC_PARAM_MANF_DATE = 0x12,
  449. DEVICE_DESC_PARAM_MANF_NAME = 0x14,
  450. DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
  451. DEVICE_DESC_PARAM_SN = 0x16,
  452. DEVICE_DESC_PARAM_OEM_ID = 0x17,
  453. DEVICE_DESC_PARAM_MANF_ID = 0x18,
  454. DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
  455. DEVICE_DESC_PARAM_UD_LEN = 0x1B,
  456. DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
  457. DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
  458. DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
  459. DEVICE_DESC_PARAM_FFU_TMT = 0x20,
  460. DEVICE_DESC_PARAM_Q_DPTH = 0x21,
  461. DEVICE_DESC_PARAM_DEV_VER = 0x22,
  462. DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
  463. DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
  464. DEVICE_DESC_PARAM_PSA_TMT = 0x29,
  465. DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
  466. };
  467. struct ufs_hba;
  468. enum {
  469. UFSHCD_MAX_CHANNEL = 0,
  470. UFSHCD_MAX_ID = 1,
  471. };
  472. enum dev_cmd_type {
  473. DEV_CMD_TYPE_NOP = 0x0,
  474. DEV_CMD_TYPE_QUERY = 0x1,
  475. };
  476. /**
  477. * struct uic_command - UIC command structure
  478. * @command: UIC command
  479. * @argument1: UIC command argument 1
  480. * @argument2: UIC command argument 2
  481. * @argument3: UIC command argument 3
  482. * @cmd_active: Indicate if UIC command is outstanding
  483. * @result: UIC command result
  484. * @done: UIC command completion
  485. */
  486. struct uic_command {
  487. u32 command;
  488. u32 argument1;
  489. u32 argument2;
  490. u32 argument3;
  491. int cmd_active;
  492. int result;
  493. };
  494. /* GenSelectorIndex calculation macros for M-PHY attributes */
  495. #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
  496. #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
  497. #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
  498. ((sel) & 0xFFFF))
  499. #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
  500. #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
  501. #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
  502. /* Link Status*/
  503. enum link_status {
  504. UFSHCD_LINK_IS_DOWN = 1,
  505. UFSHCD_LINK_IS_UP = 2,
  506. };
  507. #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
  508. ((sel) & 0xFFFF))
  509. #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
  510. #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
  511. #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
  512. /* UIC Commands */
  513. enum uic_cmd_dme {
  514. UIC_CMD_DME_GET = 0x01,
  515. UIC_CMD_DME_SET = 0x02,
  516. UIC_CMD_DME_PEER_GET = 0x03,
  517. UIC_CMD_DME_PEER_SET = 0x04,
  518. UIC_CMD_DME_POWERON = 0x10,
  519. UIC_CMD_DME_POWEROFF = 0x11,
  520. UIC_CMD_DME_ENABLE = 0x12,
  521. UIC_CMD_DME_RESET = 0x14,
  522. UIC_CMD_DME_END_PT_RST = 0x15,
  523. UIC_CMD_DME_LINK_STARTUP = 0x16,
  524. UIC_CMD_DME_HIBER_ENTER = 0x17,
  525. UIC_CMD_DME_HIBER_EXIT = 0x18,
  526. UIC_CMD_DME_TEST_MODE = 0x1A,
  527. };
  528. /* UIC Config result code / Generic error code */
  529. enum {
  530. UIC_CMD_RESULT_SUCCESS = 0x00,
  531. UIC_CMD_RESULT_INVALID_ATTR = 0x01,
  532. UIC_CMD_RESULT_FAILURE = 0x01,
  533. UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
  534. UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
  535. UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
  536. UIC_CMD_RESULT_BAD_INDEX = 0x05,
  537. UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
  538. UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
  539. UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
  540. UIC_CMD_RESULT_BUSY = 0x09,
  541. UIC_CMD_RESULT_DME_FAILURE = 0x0A,
  542. };
  543. #define MASK_UIC_COMMAND_RESULT 0xFF
  544. /* Host <-> Device UniPro Link state */
  545. enum uic_link_state {
  546. UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
  547. UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
  548. UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
  549. };
  550. /* UIC command interfaces for DME primitives */
  551. #define DME_LOCAL 0
  552. #define DME_PEER 1
  553. #define ATTR_SET_NOR 0 /* NORMAL */
  554. #define ATTR_SET_ST 1 /* STATIC */
  555. int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
  556. u8 attr_set, u32 mib_val, u8 peer);
  557. int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
  558. u32 *mib_val, u8 peer);
  559. static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
  560. u32 mib_val)
  561. {
  562. return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
  563. mib_val, DME_LOCAL);
  564. }
  565. static inline int ufshcd_dme_get(struct ufs_hba *hba,
  566. u32 attr_sel, u32 *mib_val)
  567. {
  568. return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
  569. }
  570. static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
  571. u32 attr_sel, u32 *mib_val)
  572. {
  573. return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
  574. }
  575. static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
  576. u32 mib_val)
  577. {
  578. return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
  579. mib_val, DME_PEER);
  580. }
  581. /**
  582. * struct ufs_query_req - parameters for building a query request
  583. * @query_func: UPIU header query function
  584. * @upiu_req: the query request data
  585. */
  586. struct ufs_query_req {
  587. u8 query_func;
  588. struct utp_upiu_query upiu_req;
  589. };
  590. /**
  591. * struct ufs_query_resp - UPIU QUERY
  592. * @response: device response code
  593. * @upiu_res: query response data
  594. */
  595. struct ufs_query_res {
  596. u8 response;
  597. struct utp_upiu_query upiu_res;
  598. };
  599. /**
  600. * struct ufs_query - holds relevant data structures for query request
  601. * @request: request upiu and function
  602. * @descriptor: buffer for sending/receiving descriptor
  603. * @response: response upiu and response
  604. */
  605. struct ufs_query {
  606. struct ufs_query_req request;
  607. u8 *descriptor;
  608. struct ufs_query_res response;
  609. };
  610. /**
  611. * struct ufs_dev_cmd - all assosiated fields with device management commands
  612. * @type: device management command type - Query, NOP OUT
  613. * @tag_wq: wait queue until free command slot is available
  614. */
  615. struct ufs_dev_cmd {
  616. enum dev_cmd_type type;
  617. struct ufs_query query;
  618. };
  619. struct ufs_hba_ops {
  620. int (*init)(struct ufs_hba *hba);
  621. int (*hce_enable_notify)(struct ufs_hba *hba,
  622. enum ufs_notify_change_status);
  623. int (*link_startup_notify)(struct ufs_hba *hba,
  624. enum ufs_notify_change_status);
  625. int (*phy_initialization)(struct ufs_hba *hba);
  626. };
  627. struct ufs_hba {
  628. struct udevice *dev;
  629. void __iomem *mmio_base;
  630. struct ufs_hba_ops *ops;
  631. struct ufs_desc_size desc_size;
  632. u32 capabilities;
  633. u32 version;
  634. u32 intr_mask;
  635. u32 quirks;
  636. /*
  637. * If UFS host controller is having issue in processing LCC (Line
  638. * Control Command) coming from device then enable this quirk.
  639. * When this quirk is enabled, host controller driver should disable
  640. * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
  641. * attribute of device to 0).
  642. */
  643. #define UFSHCD_QUIRK_BROKEN_LCC 0x1
  644. /* Virtual memory reference */
  645. struct utp_transfer_cmd_desc *ucdl;
  646. struct utp_transfer_req_desc *utrdl;
  647. /* TODO: Add Task Manegement Support */
  648. struct utp_task_req_desc *utmrdl;
  649. struct utp_upiu_req *ucd_req_ptr;
  650. struct utp_upiu_rsp *ucd_rsp_ptr;
  651. struct ufshcd_sg_entry *ucd_prdt_ptr;
  652. /* Power Mode information */
  653. enum ufs_dev_pwr_mode curr_dev_pwr_mode;
  654. struct ufs_pa_layer_attr pwr_info;
  655. struct ufs_pwr_mode_info max_pwr_info;
  656. struct ufs_dev_cmd dev_cmd;
  657. };
  658. static inline int ufshcd_ops_init(struct ufs_hba *hba)
  659. {
  660. if (hba->ops && hba->ops->init)
  661. return hba->ops->init(hba);
  662. return 0;
  663. }
  664. static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba,
  665. bool status)
  666. {
  667. if (hba->ops && hba->ops->hce_enable_notify)
  668. return hba->ops->hce_enable_notify(hba, status);
  669. return 0;
  670. }
  671. static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba,
  672. bool status)
  673. {
  674. if (hba->ops && hba->ops->link_startup_notify)
  675. return hba->ops->link_startup_notify(hba, status);
  676. return 0;
  677. }
  678. /* Controller UFSHCI version */
  679. enum {
  680. UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
  681. UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
  682. UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
  683. UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
  684. };
  685. /* Interrupt disable masks */
  686. enum {
  687. /* Interrupt disable mask for UFSHCI v1.0 */
  688. INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
  689. INTERRUPT_MASK_RW_VER_10 = 0x30000,
  690. /* Interrupt disable mask for UFSHCI v1.1 */
  691. INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
  692. /* Interrupt disable mask for UFSHCI v2.1 */
  693. INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
  694. };
  695. /* UFSHCI Registers */
  696. enum {
  697. REG_CONTROLLER_CAPABILITIES = 0x00,
  698. REG_UFS_VERSION = 0x08,
  699. REG_CONTROLLER_DEV_ID = 0x10,
  700. REG_CONTROLLER_PROD_ID = 0x14,
  701. REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
  702. REG_INTERRUPT_STATUS = 0x20,
  703. REG_INTERRUPT_ENABLE = 0x24,
  704. REG_CONTROLLER_STATUS = 0x30,
  705. REG_CONTROLLER_ENABLE = 0x34,
  706. REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
  707. REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
  708. REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
  709. REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
  710. REG_UIC_ERROR_CODE_DME = 0x48,
  711. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
  712. REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
  713. REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
  714. REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
  715. REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
  716. REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
  717. REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
  718. REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
  719. REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
  720. REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
  721. REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
  722. REG_UIC_COMMAND = 0x90,
  723. REG_UIC_COMMAND_ARG_1 = 0x94,
  724. REG_UIC_COMMAND_ARG_2 = 0x98,
  725. REG_UIC_COMMAND_ARG_3 = 0x9C,
  726. UFSHCI_REG_SPACE_SIZE = 0xA0,
  727. REG_UFS_CCAP = 0x100,
  728. REG_UFS_CRYPTOCAP = 0x104,
  729. UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
  730. };
  731. /* Controller capability masks */
  732. enum {
  733. MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
  734. MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
  735. MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
  736. MASK_64_ADDRESSING_SUPPORT = 0x01000000,
  737. MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
  738. MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
  739. };
  740. /* Interrupt Status 20h */
  741. #define UTP_TRANSFER_REQ_COMPL 0x1
  742. #define UIC_DME_END_PT_RESET 0x2
  743. #define UIC_ERROR 0x4
  744. #define UIC_TEST_MODE 0x8
  745. #define UIC_POWER_MODE 0x10
  746. #define UIC_HIBERNATE_EXIT 0x20
  747. #define UIC_HIBERNATE_ENTER 0x40
  748. #define UIC_LINK_LOST 0x80
  749. #define UIC_LINK_STARTUP 0x100
  750. #define UTP_TASK_REQ_COMPL 0x200
  751. #define UIC_COMMAND_COMPL 0x400
  752. #define DEVICE_FATAL_ERROR 0x800
  753. #define CONTROLLER_FATAL_ERROR 0x10000
  754. #define SYSTEM_BUS_FATAL_ERROR 0x20000
  755. #define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
  756. UIC_HIBERNATE_EXIT |\
  757. UIC_POWER_MODE)
  758. #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE)
  759. #define UFSHCD_ERROR_MASK (UIC_ERROR |\
  760. DEVICE_FATAL_ERROR |\
  761. CONTROLLER_FATAL_ERROR |\
  762. SYSTEM_BUS_FATAL_ERROR)
  763. #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
  764. CONTROLLER_FATAL_ERROR |\
  765. SYSTEM_BUS_FATAL_ERROR)
  766. /* Host Controller Enable 0x34h */
  767. #define CONTROLLER_ENABLE 0x1
  768. #define CONTROLLER_DISABLE 0x0
  769. /* HCS - Host Controller Status 30h */
  770. #define DEVICE_PRESENT 0x1
  771. #define UTP_TRANSFER_REQ_LIST_READY 0x2
  772. #define UTP_TASK_REQ_LIST_READY 0x4
  773. #define UIC_COMMAND_READY 0x8
  774. #define HOST_ERROR_INDICATOR 0x10
  775. #define DEVICE_ERROR_INDICATOR 0x20
  776. #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
  777. #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
  778. UTP_TASK_REQ_LIST_READY |\
  779. UIC_COMMAND_READY)
  780. enum {
  781. PWR_OK = 0x0,
  782. PWR_LOCAL = 0x01,
  783. PWR_REMOTE = 0x02,
  784. PWR_BUSY = 0x03,
  785. PWR_ERROR_CAP = 0x04,
  786. PWR_FATAL_ERROR = 0x05,
  787. };
  788. /* UICCMD - UIC Command */
  789. #define COMMAND_OPCODE_MASK 0xFF
  790. #define GEN_SELECTOR_INDEX_MASK 0xFFFF
  791. #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
  792. #define RESET_LEVEL 0xFF
  793. #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
  794. #define CONFIG_RESULT_CODE_MASK 0xFF
  795. #define GENERIC_ERROR_CODE_MASK 0xFF
  796. #define ufshcd_writel(hba, val, reg) \
  797. writel((val), (hba)->mmio_base + (reg))
  798. #define ufshcd_readl(hba, reg) \
  799. readl((hba)->mmio_base + (reg))
  800. /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
  801. #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
  802. /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
  803. #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
  804. int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops);
  805. #endif