stm32_timer.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <timer.h>
  11. #include <dm/device_compat.h>
  12. #include <linux/bitops.h>
  13. #include <asm/io.h>
  14. /* Timer control1 register */
  15. #define CR1_CEN BIT(0)
  16. #define CR1_ARPE BIT(7)
  17. /* Event Generation Register register */
  18. #define EGR_UG BIT(0)
  19. /* Auto reload register for free running config */
  20. #define GPT_FREE_RUNNING 0xFFFFFFFF
  21. struct stm32_timer_regs {
  22. u32 cr1;
  23. u32 cr2;
  24. u32 smcr;
  25. u32 dier;
  26. u32 sr;
  27. u32 egr;
  28. u32 ccmr1;
  29. u32 ccmr2;
  30. u32 ccer;
  31. u32 cnt;
  32. u32 psc;
  33. u32 arr;
  34. u32 reserved;
  35. u32 ccr1;
  36. u32 ccr2;
  37. u32 ccr3;
  38. u32 ccr4;
  39. u32 reserved1;
  40. u32 dcr;
  41. u32 dmar;
  42. u32 tim2_5_or;
  43. };
  44. struct stm32_timer_priv {
  45. struct stm32_timer_regs *base;
  46. };
  47. static u64 stm32_timer_get_count(struct udevice *dev)
  48. {
  49. struct stm32_timer_priv *priv = dev_get_priv(dev);
  50. struct stm32_timer_regs *regs = priv->base;
  51. return readl(&regs->cnt);
  52. }
  53. static int stm32_timer_probe(struct udevice *dev)
  54. {
  55. struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  56. struct stm32_timer_priv *priv = dev_get_priv(dev);
  57. struct stm32_timer_regs *regs;
  58. struct clk clk;
  59. fdt_addr_t addr;
  60. int ret;
  61. u32 rate, psc;
  62. addr = dev_read_addr(dev);
  63. if (addr == FDT_ADDR_T_NONE)
  64. return -EINVAL;
  65. priv->base = (struct stm32_timer_regs *)addr;
  66. ret = clk_get_by_index(dev, 0, &clk);
  67. if (ret < 0)
  68. return ret;
  69. ret = clk_enable(&clk);
  70. if (ret) {
  71. dev_err(dev, "failed to enable clock\n");
  72. return ret;
  73. }
  74. regs = priv->base;
  75. /* Stop the timer */
  76. clrbits_le32(&regs->cr1, CR1_CEN);
  77. /* get timer clock */
  78. rate = clk_get_rate(&clk);
  79. /* we set timer prescaler to obtain a 1MHz timer counter frequency */
  80. psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
  81. writel(psc, &regs->psc);
  82. /* Set timer frequency to 1MHz */
  83. uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
  84. /* Configure timer for auto-reload */
  85. setbits_le32(&regs->cr1, CR1_ARPE);
  86. /* load value for auto reload */
  87. writel(GPT_FREE_RUNNING, &regs->arr);
  88. /* start timer */
  89. setbits_le32(&regs->cr1, CR1_CEN);
  90. /* Update generation */
  91. setbits_le32(&regs->egr, EGR_UG);
  92. return 0;
  93. }
  94. static const struct timer_ops stm32_timer_ops = {
  95. .get_count = stm32_timer_get_count,
  96. };
  97. static const struct udevice_id stm32_timer_ids[] = {
  98. { .compatible = "st,stm32-timer" },
  99. {}
  100. };
  101. U_BOOT_DRIVER(stm32_timer) = {
  102. .name = "stm32_timer",
  103. .id = UCLASS_TIMER,
  104. .of_match = stm32_timer_ids,
  105. .priv_auto_alloc_size = sizeof(struct stm32_timer_priv),
  106. .probe = stm32_timer_probe,
  107. .ops = &stm32_timer_ops,
  108. };