mpc83xx_timer.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <dm.h>
  9. #include <irq_func.h>
  10. #include <log.h>
  11. #include <status_led.h>
  12. #include <sysinfo.h>
  13. #include <time.h>
  14. #include <timer.h>
  15. #include <watchdog.h>
  16. #include <asm/ptrace.h>
  17. #include <linux/bitops.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /**
  20. * struct mpc83xx_timer_priv - Private data structure for MPC83xx timer driver
  21. * @decrementer_count: Value to which the decrementer register should be re-set
  22. * to when a timer interrupt occurs, thus determines the
  23. * interrupt frequency (value for 1e6/HZ microseconds)
  24. * @timestamp: Counter for the number of timer interrupts that have
  25. * occurred (i.e. can be used to trigger events
  26. * periodically in the timer interrupt)
  27. */
  28. struct mpc83xx_timer_priv {
  29. uint decrementer_count;
  30. ulong timestamp;
  31. };
  32. /*
  33. * Bitmask for enabling the time base in the SPCR (System Priority
  34. * Configuration Register)
  35. */
  36. static const u32 SPCR_TBEN_MASK = BIT(31 - 9);
  37. /**
  38. * get_dec() - Get the value of the decrementer register
  39. *
  40. * Return: The value of the decrementer register
  41. */
  42. static inline unsigned long get_dec(void)
  43. {
  44. unsigned long val;
  45. asm volatile ("mfdec %0" : "=r" (val) : );
  46. return val;
  47. }
  48. /**
  49. * set_dec() - Set the value of the decrementer register
  50. * @val: The value of the decrementer register to be set
  51. */
  52. static inline void set_dec(unsigned long val)
  53. {
  54. if (val)
  55. asm volatile ("mtdec %0"::"r" (val));
  56. }
  57. /**
  58. * mftbu() - Get value of TBU (upper time base) register
  59. *
  60. * Return: Value of the TBU register
  61. */
  62. static inline u32 mftbu(void)
  63. {
  64. u32 rval;
  65. asm volatile("mftbu %0" : "=r" (rval));
  66. return rval;
  67. }
  68. /**
  69. * mftb() - Get value of TBL (lower time base) register
  70. *
  71. * Return: Value of the TBL register
  72. */
  73. static inline u32 mftb(void)
  74. {
  75. u32 rval;
  76. asm volatile("mftb %0" : "=r" (rval));
  77. return rval;
  78. }
  79. /*
  80. * TODO(mario.six@gdsys.cc): This should really be done by timer_init, and the
  81. * interrupt init should go into a interrupt driver.
  82. */
  83. int interrupt_init(void)
  84. {
  85. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  86. struct udevice *csb;
  87. struct udevice *sysinfo;
  88. struct udevice *timer;
  89. struct mpc83xx_timer_priv *timer_priv;
  90. struct clk clock;
  91. int ret;
  92. ret = uclass_first_device_err(UCLASS_TIMER, &timer);
  93. if (ret) {
  94. debug("%s: Could not find timer device (error: %d)",
  95. __func__, ret);
  96. return ret;
  97. }
  98. timer_priv = dev_get_priv(timer);
  99. if (sysinfo_get(&sysinfo)) {
  100. debug("%s: sysinfo device could not be fetched.\n", __func__);
  101. return -ENOENT;
  102. }
  103. ret = uclass_get_device_by_phandle(UCLASS_SIMPLE_BUS, sysinfo,
  104. "csb", &csb);
  105. if (ret) {
  106. debug("%s: Could not retrieve CSB device (error: %d)",
  107. __func__, ret);
  108. return ret;
  109. }
  110. ret = clk_get_by_index(csb, 0, &clock);
  111. if (ret) {
  112. debug("%s: Could not retrieve clock (error: %d)",
  113. __func__, ret);
  114. return ret;
  115. }
  116. timer_priv->decrementer_count = (clk_get_rate(&clock) / 4)
  117. / CONFIG_SYS_HZ;
  118. /* Enable e300 time base */
  119. setbits_be32(&immr->sysconf.spcr, SPCR_TBEN_MASK);
  120. set_dec(timer_priv->decrementer_count);
  121. /* Switch on interrupts */
  122. set_msr(get_msr() | MSR_EE);
  123. return 0;
  124. }
  125. /**
  126. * timer_interrupt() - Handler for the timer interrupt
  127. * @regs: Array of register values
  128. */
  129. void timer_interrupt(struct pt_regs *regs)
  130. {
  131. struct udevice *timer = gd->timer;
  132. struct mpc83xx_timer_priv *priv;
  133. /*
  134. * During initialization, gd->timer might not be set yet, but the timer
  135. * interrupt may already be enabled. In this case, wait for the
  136. * initialization to complete
  137. */
  138. if (!timer)
  139. return;
  140. priv = dev_get_priv(timer);
  141. /* Restore Decrementer Count */
  142. set_dec(priv->decrementer_count);
  143. priv->timestamp++;
  144. #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
  145. if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
  146. WATCHDOG_RESET();
  147. #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
  148. #ifdef CONFIG_LED_STATUS
  149. status_led_tick(priv->timestamp);
  150. #endif /* CONFIG_LED_STATUS */
  151. }
  152. void wait_ticks(ulong ticks)
  153. {
  154. ulong end = get_ticks() + ticks;
  155. while (end > get_ticks())
  156. WATCHDOG_RESET();
  157. }
  158. static u64 mpc83xx_timer_get_count(struct udevice *dev)
  159. {
  160. u32 tbu, tbl;
  161. /*
  162. * To make sure that no tbl overflow occurred between reading tbl and
  163. * tbu, read tbu again, and compare it with the previously read tbu
  164. * value: If they're different, a tbl overflow has occurred.
  165. */
  166. do {
  167. tbu = mftbu();
  168. tbl = mftb();
  169. } while (tbu != mftbu());
  170. return (tbu * 0x10000ULL) + tbl;
  171. }
  172. static int mpc83xx_timer_probe(struct udevice *dev)
  173. {
  174. struct timer_dev_priv *uc_priv = dev->uclass_priv;
  175. struct clk clock;
  176. int ret;
  177. ret = interrupt_init();
  178. if (ret) {
  179. debug("%s: interrupt_init failed (err = %d)\n",
  180. dev->name, ret);
  181. return ret;
  182. }
  183. ret = clk_get_by_index(dev, 0, &clock);
  184. if (ret) {
  185. debug("%s: Could not retrieve clock (err = %d)\n",
  186. dev->name, ret);
  187. return ret;
  188. }
  189. uc_priv->clock_rate = (clk_get_rate(&clock) + 3L) / 4L;
  190. return 0;
  191. }
  192. static const struct timer_ops mpc83xx_timer_ops = {
  193. .get_count = mpc83xx_timer_get_count,
  194. };
  195. static const struct udevice_id mpc83xx_timer_ids[] = {
  196. { .compatible = "fsl,mpc83xx-timer" },
  197. { /* sentinel */ }
  198. };
  199. U_BOOT_DRIVER(mpc83xx_timer) = {
  200. .name = "mpc83xx_timer",
  201. .id = UCLASS_TIMER,
  202. .of_match = mpc83xx_timer_ids,
  203. .probe = mpc83xx_timer_probe,
  204. .ops = &mpc83xx_timer_ops,
  205. .priv_auto_alloc_size = sizeof(struct mpc83xx_timer_priv),
  206. };