ag101p_timer.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Andestech ATFTMR010 timer driver
  4. *
  5. * (C) Copyright 2016
  6. * Rick Chen, NDS32 Software Engineering, rick@andestech.com
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <timer.h>
  12. #include <linux/io.h>
  13. /*
  14. * Timer Control Register
  15. */
  16. #define T3_UPDOWN (1 << 11)
  17. #define T2_UPDOWN (1 << 10)
  18. #define T1_UPDOWN (1 << 9)
  19. #define T3_OFENABLE (1 << 8)
  20. #define T3_CLOCK (1 << 7)
  21. #define T3_ENABLE (1 << 6)
  22. #define T2_OFENABLE (1 << 5)
  23. #define T2_CLOCK (1 << 4)
  24. #define T2_ENABLE (1 << 3)
  25. #define T1_OFENABLE (1 << 2)
  26. #define T1_CLOCK (1 << 1)
  27. #define T1_ENABLE (1 << 0)
  28. /*
  29. * Timer Interrupt State & Mask Registers
  30. */
  31. #define T3_OVERFLOW (1 << 8)
  32. #define T3_MATCH2 (1 << 7)
  33. #define T3_MATCH1 (1 << 6)
  34. #define T2_OVERFLOW (1 << 5)
  35. #define T2_MATCH2 (1 << 4)
  36. #define T2_MATCH1 (1 << 3)
  37. #define T1_OVERFLOW (1 << 2)
  38. #define T1_MATCH2 (1 << 1)
  39. #define T1_MATCH1 (1 << 0)
  40. struct atftmr_timer_regs {
  41. u32 t1_counter; /* 0x00 */
  42. u32 t1_load; /* 0x04 */
  43. u32 t1_match1; /* 0x08 */
  44. u32 t1_match2; /* 0x0c */
  45. u32 t2_counter; /* 0x10 */
  46. u32 t2_load; /* 0x14 */
  47. u32 t2_match1; /* 0x18 */
  48. u32 t2_match2; /* 0x1c */
  49. u32 t3_counter; /* 0x20 */
  50. u32 t3_load; /* 0x24 */
  51. u32 t3_match1; /* 0x28 */
  52. u32 t3_match2; /* 0x2c */
  53. u32 cr; /* 0x30 */
  54. u32 int_state; /* 0x34 */
  55. u32 int_mask; /* 0x38 */
  56. };
  57. struct atftmr_timer_platdata {
  58. struct atftmr_timer_regs *regs;
  59. };
  60. static u64 atftmr_timer_get_count(struct udevice *dev)
  61. {
  62. struct atftmr_timer_platdata *plat = dev->platdata;
  63. struct atftmr_timer_regs *const regs = plat->regs;
  64. u32 val;
  65. val = readl(&regs->t3_counter);
  66. return timer_conv_64(val);
  67. }
  68. static int atftmr_timer_probe(struct udevice *dev)
  69. {
  70. struct atftmr_timer_platdata *plat = dev->platdata;
  71. struct atftmr_timer_regs *const regs = plat->regs;
  72. u32 cr;
  73. writel(0, &regs->t3_load);
  74. writel(0, &regs->t3_counter);
  75. writel(TIMER_LOAD_VAL, &regs->t3_match1);
  76. writel(TIMER_LOAD_VAL, &regs->t3_match2);
  77. /* disable interrupts */
  78. writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , &regs->int_mask);
  79. cr = readl(&regs->cr);
  80. cr |= (T3_ENABLE|T3_UPDOWN);
  81. writel(cr, &regs->cr);
  82. return 0;
  83. }
  84. static int atftme_timer_ofdata_to_platdata(struct udevice *dev)
  85. {
  86. struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
  87. plat->regs = map_physmem(dev_read_addr(dev),
  88. sizeof(struct atftmr_timer_regs),
  89. MAP_NOCACHE);
  90. return 0;
  91. }
  92. static const struct timer_ops ag101p_timer_ops = {
  93. .get_count = atftmr_timer_get_count,
  94. };
  95. static const struct udevice_id ag101p_timer_ids[] = {
  96. { .compatible = "andestech,attmr010" },
  97. {}
  98. };
  99. U_BOOT_DRIVER(altera_timer) = {
  100. .name = "ag101p_timer",
  101. .id = UCLASS_TIMER,
  102. .of_match = ag101p_timer_ids,
  103. .ofdata_to_platdata = atftme_timer_ofdata_to_platdata,
  104. .platdata_auto_alloc_size = sizeof(struct atftmr_timer_platdata),
  105. .probe = atftmr_timer_probe,
  106. .ops = &ag101p_timer_ops,
  107. };