imx_tmu.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017~2020 NXP
  4. *
  5. */
  6. #include <config.h>
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <dm.h>
  12. #include <dm/device-internal.h>
  13. #include <dm/device.h>
  14. #include <errno.h>
  15. #include <fuse.h>
  16. #include <linux/delay.h>
  17. #include <malloc.h>
  18. #include <thermal.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define SITES_MAX 16
  21. #define FLAGS_VER2 0x1
  22. #define FLAGS_VER3 0x2
  23. #define TMR_DISABLE 0x0
  24. #define TMR_ME 0x80000000
  25. #define TMR_ALPF 0x0c000000
  26. #define TMTMIR_DEFAULT 0x00000002
  27. #define TIER_DISABLE 0x0
  28. #define TER_EN 0x80000000
  29. #define TER_ADC_PD 0x40000000
  30. #define TER_ALPF 0x3
  31. /*
  32. * i.MX TMU Registers
  33. */
  34. struct imx_tmu_site_regs {
  35. u32 tritsr; /* Immediate Temperature Site Register */
  36. u32 tratsr; /* Average Temperature Site Register */
  37. u8 res0[0x8];
  38. };
  39. struct imx_tmu_regs {
  40. u32 tmr; /* Mode Register */
  41. u32 tsr; /* Status Register */
  42. u32 tmtmir; /* Temperature measurement interval Register */
  43. u8 res0[0x14];
  44. u32 tier; /* Interrupt Enable Register */
  45. u32 tidr; /* Interrupt Detect Register */
  46. u32 tiscr; /* Interrupt Site Capture Register */
  47. u32 ticscr; /* Interrupt Critical Site Capture Register */
  48. u8 res1[0x10];
  49. u32 tmhtcrh; /* High Temperature Capture Register */
  50. u32 tmhtcrl; /* Low Temperature Capture Register */
  51. u8 res2[0x8];
  52. u32 tmhtitr; /* High Temperature Immediate Threshold */
  53. u32 tmhtatr; /* High Temperature Average Threshold */
  54. u32 tmhtactr; /* High Temperature Average Crit Threshold */
  55. u8 res3[0x24];
  56. u32 ttcfgr; /* Temperature Configuration Register */
  57. u32 tscfgr; /* Sensor Configuration Register */
  58. u8 res4[0x78];
  59. struct imx_tmu_site_regs site[SITES_MAX];
  60. u8 res5[0x9f8];
  61. u32 ipbrr0; /* IP Block Revision Register 0 */
  62. u32 ipbrr1; /* IP Block Revision Register 1 */
  63. u8 res6[0x310];
  64. u32 ttr0cr; /* Temperature Range 0 Control Register */
  65. u32 ttr1cr; /* Temperature Range 1 Control Register */
  66. u32 ttr2cr; /* Temperature Range 2 Control Register */
  67. u32 ttr3cr; /* Temperature Range 3 Control Register */
  68. };
  69. struct imx_tmu_regs_v2 {
  70. u32 ter; /* TMU enable Register */
  71. u32 tsr; /* Status Register */
  72. u32 tier; /* Interrupt enable register */
  73. u32 tidr; /* Interrupt detect register */
  74. u32 tmhtitr; /* Monitor high temperature immediate threshold register */
  75. u32 tmhtatr; /* Monitor high temperature average threshold register */
  76. u32 tmhtactr; /* TMU monitor high temperature average critical threshold register */
  77. u32 tscr; /* Sensor value capture register */
  78. u32 tritsr; /* Report immediate temperature site register 0 */
  79. u32 tratsr; /* Report average temperature site register 0 */
  80. u32 tasr; /* Amplifier setting register */
  81. u32 ttmc; /* Test MUX control */
  82. u32 tcaliv;
  83. };
  84. struct imx_tmu_regs_v3 {
  85. u32 ter; /* TMU enable Register */
  86. u32 tps; /* Status Register */
  87. u32 tier; /* Interrupt enable register */
  88. u32 tidr; /* Interrupt detect register */
  89. u32 tmhtitr; /* Monitor high temperature immediate threshold register */
  90. u32 tmhtatr; /* Monitor high temperature average threshold register */
  91. u32 tmhtactr; /* TMU monitor high temperature average critical threshold register */
  92. u32 tscr; /* Sensor value capture register */
  93. u32 tritsr; /* Report immediate temperature site register 0 */
  94. u32 tratsr; /* Report average temperature site register 0 */
  95. u32 tasr; /* Amplifier setting register */
  96. u32 ttmc; /* Test MUX control */
  97. u32 tcaliv0;
  98. u32 tcaliv1;
  99. u32 tcaliv_m40;
  100. u32 trim;
  101. };
  102. union tmu_regs {
  103. struct imx_tmu_regs regs_v1;
  104. struct imx_tmu_regs_v2 regs_v2;
  105. struct imx_tmu_regs_v3 regs_v3;
  106. };
  107. struct imx_tmu_plat {
  108. int critical;
  109. int alert;
  110. int polling_delay;
  111. int id;
  112. bool zone_node;
  113. union tmu_regs *regs;
  114. };
  115. static int read_temperature(struct udevice *dev, int *temp)
  116. {
  117. struct imx_tmu_plat *pdata = dev_get_platdata(dev);
  118. ulong drv_data = dev_get_driver_data(dev);
  119. u32 val;
  120. u32 retry = 10;
  121. u32 valid = 0;
  122. do {
  123. mdelay(100);
  124. retry--;
  125. if (drv_data & FLAGS_VER3) {
  126. val = readl(&pdata->regs->regs_v3.tritsr);
  127. valid = val & (1 << (30 + pdata->id));
  128. } else if (drv_data & FLAGS_VER2) {
  129. val = readl(&pdata->regs->regs_v2.tritsr);
  130. /*
  131. * Check if TEMP is in valid range, the V bit in TRITSR
  132. * only reflects the RAW uncalibrated data
  133. */
  134. valid = ((val & 0xff) < 10 || (val & 0xff) > 125) ? 0 : 1;
  135. } else {
  136. val = readl(&pdata->regs->regs_v1.site[pdata->id].tritsr);
  137. valid = val & 0x80000000;
  138. }
  139. } while (!valid && retry > 0);
  140. if (retry > 0) {
  141. if (drv_data & FLAGS_VER3) {
  142. val = (val >> (pdata->id * 16)) & 0xff;
  143. if (val & 0x80) /* Negative */
  144. val = (~(val & 0x7f) + 1);
  145. *temp = val;
  146. if (*temp < -40 || *temp > 125) /* Check the range */
  147. return -EINVAL;
  148. *temp *= 1000;
  149. } else {
  150. *temp = (val & 0xff) * 1000;
  151. }
  152. } else {
  153. return -EINVAL;
  154. }
  155. return 0;
  156. }
  157. int imx_tmu_get_temp(struct udevice *dev, int *temp)
  158. {
  159. struct imx_tmu_plat *pdata = dev_get_platdata(dev);
  160. int cpu_tmp = 0;
  161. int ret;
  162. ret = read_temperature(dev, &cpu_tmp);
  163. if (ret)
  164. return ret;
  165. while (cpu_tmp >= pdata->alert) {
  166. printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)", cpu_tmp, pdata->alert, pdata->critical);
  167. puts(" waiting...\n");
  168. mdelay(pdata->polling_delay);
  169. ret = read_temperature(dev, &cpu_tmp);
  170. if (ret)
  171. return ret;
  172. }
  173. *temp = cpu_tmp / 1000;
  174. return 0;
  175. }
  176. static const struct dm_thermal_ops imx_tmu_ops = {
  177. .get_temp = imx_tmu_get_temp,
  178. };
  179. static int imx_tmu_calibration(struct udevice *dev)
  180. {
  181. int i, val, len, ret;
  182. u32 range[4];
  183. const fdt32_t *calibration;
  184. struct imx_tmu_plat *pdata = dev_get_platdata(dev);
  185. ulong drv_data = dev_get_driver_data(dev);
  186. debug("%s\n", __func__);
  187. if (drv_data & (FLAGS_VER2 | FLAGS_VER3))
  188. return 0;
  189. ret = dev_read_u32_array(dev, "fsl,tmu-range", range, 4);
  190. if (ret) {
  191. printf("TMU: missing calibration range, ret = %d.\n", ret);
  192. return ret;
  193. }
  194. /* Init temperature range registers */
  195. writel(range[0], &pdata->regs->regs_v1.ttr0cr);
  196. writel(range[1], &pdata->regs->regs_v1.ttr1cr);
  197. writel(range[2], &pdata->regs->regs_v1.ttr2cr);
  198. writel(range[3], &pdata->regs->regs_v1.ttr3cr);
  199. calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len);
  200. if (!calibration || len % 8) {
  201. printf("TMU: invalid calibration data.\n");
  202. return -ENODEV;
  203. }
  204. for (i = 0; i < len; i += 8, calibration += 2) {
  205. val = fdt32_to_cpu(*calibration);
  206. writel(val, &pdata->regs->regs_v1.ttcfgr);
  207. val = fdt32_to_cpu(*(calibration + 1));
  208. writel(val, &pdata->regs->regs_v1.tscfgr);
  209. }
  210. return 0;
  211. }
  212. void __weak imx_tmu_arch_init(void *reg_base)
  213. {
  214. }
  215. static void imx_tmu_init(struct udevice *dev)
  216. {
  217. struct imx_tmu_plat *pdata = dev_get_platdata(dev);
  218. ulong drv_data = dev_get_driver_data(dev);
  219. debug("%s\n", __func__);
  220. if (drv_data & FLAGS_VER3) {
  221. /* Disable monitoring */
  222. writel(0x0, &pdata->regs->regs_v3.ter);
  223. /* Disable interrupt, using polling instead */
  224. writel(0x0, &pdata->regs->regs_v3.tier);
  225. } else if (drv_data & FLAGS_VER2) {
  226. /* Disable monitoring */
  227. writel(0x0, &pdata->regs->regs_v2.ter);
  228. /* Disable interrupt, using polling instead */
  229. writel(0x0, &pdata->regs->regs_v2.tier);
  230. } else {
  231. /* Disable monitoring */
  232. writel(TMR_DISABLE, &pdata->regs->regs_v1.tmr);
  233. /* Disable interrupt, using polling instead */
  234. writel(TIER_DISABLE, &pdata->regs->regs_v1.tier);
  235. /* Set update_interval */
  236. writel(TMTMIR_DEFAULT, &pdata->regs->regs_v1.tmtmir);
  237. }
  238. imx_tmu_arch_init((void *)pdata->regs);
  239. }
  240. static int imx_tmu_enable_msite(struct udevice *dev)
  241. {
  242. struct imx_tmu_plat *pdata = dev_get_platdata(dev);
  243. ulong drv_data = dev_get_driver_data(dev);
  244. u32 reg;
  245. debug("%s\n", __func__);
  246. if (!pdata->regs)
  247. return -EIO;
  248. if (drv_data & FLAGS_VER3) {
  249. reg = readl(&pdata->regs->regs_v3.ter);
  250. reg &= ~TER_EN;
  251. writel(reg, &pdata->regs->regs_v3.ter);
  252. writel(pdata->id << 30, &pdata->regs->regs_v3.tps);
  253. reg &= ~TER_ALPF;
  254. reg |= 0x1;
  255. reg &= ~TER_ADC_PD;
  256. writel(reg, &pdata->regs->regs_v3.ter);
  257. /* Enable monitor */
  258. reg |= TER_EN;
  259. writel(reg, &pdata->regs->regs_v3.ter);
  260. } else if (drv_data & FLAGS_VER2) {
  261. reg = readl(&pdata->regs->regs_v2.ter);
  262. reg &= ~TER_EN;
  263. writel(reg, &pdata->regs->regs_v2.ter);
  264. reg &= ~TER_ALPF;
  265. reg |= 0x1;
  266. writel(reg, &pdata->regs->regs_v2.ter);
  267. /* Enable monitor */
  268. reg |= TER_EN;
  269. writel(reg, &pdata->regs->regs_v2.ter);
  270. } else {
  271. /* Clear the ME before setting MSITE and ALPF*/
  272. reg = readl(&pdata->regs->regs_v1.tmr);
  273. reg &= ~TMR_ME;
  274. writel(reg, &pdata->regs->regs_v1.tmr);
  275. reg |= 1 << (15 - pdata->id);
  276. reg |= TMR_ALPF;
  277. writel(reg, &pdata->regs->regs_v1.tmr);
  278. /* Enable ME */
  279. reg |= TMR_ME;
  280. writel(reg, &pdata->regs->regs_v1.tmr);
  281. }
  282. return 0;
  283. }
  284. static int imx_tmu_bind(struct udevice *dev)
  285. {
  286. struct imx_tmu_plat *pdata = dev_get_platdata(dev);
  287. int ret;
  288. ofnode node, offset;
  289. const char *name;
  290. const void *prop;
  291. debug("%s dev name %s\n", __func__, dev->name);
  292. prop = dev_read_prop(dev, "compatible", NULL);
  293. if (!prop)
  294. return 0;
  295. pdata->zone_node = 1;
  296. node = ofnode_path("/thermal-zones");
  297. ofnode_for_each_subnode(offset, node) {
  298. /* Bind the subnode to this driver */
  299. name = ofnode_get_name(offset);
  300. ret = device_bind_with_driver_data(dev, dev->driver, name,
  301. dev->driver_data, offset,
  302. NULL);
  303. if (ret)
  304. printf("Error binding driver '%s': %d\n",
  305. dev->driver->name, ret);
  306. }
  307. return 0;
  308. }
  309. static int imx_tmu_parse_fdt(struct udevice *dev)
  310. {
  311. struct imx_tmu_plat *pdata = dev_get_platdata(dev), *p_parent_data;
  312. struct ofnode_phandle_args args;
  313. ofnode trips_np;
  314. int ret;
  315. debug("%s dev name %s\n", __func__, dev->name);
  316. if (pdata->zone_node) {
  317. pdata->regs = (union tmu_regs *)dev_read_addr_ptr(dev);
  318. if (!pdata->regs)
  319. return -EINVAL;
  320. return 0;
  321. }
  322. p_parent_data = dev_get_platdata(dev->parent);
  323. if (p_parent_data->zone_node)
  324. pdata->regs = p_parent_data->regs;
  325. ret = dev_read_phandle_with_args(dev, "thermal-sensors",
  326. "#thermal-sensor-cells",
  327. 0, 0, &args);
  328. if (ret)
  329. return ret;
  330. if (!ofnode_equal(args.node, dev_ofnode(dev->parent)))
  331. return -EFAULT;
  332. if (args.args_count >= 1)
  333. pdata->id = args.args[0];
  334. else
  335. pdata->id = 0;
  336. debug("args.args_count %d, id %d\n", args.args_count, pdata->id);
  337. pdata->polling_delay = dev_read_u32_default(dev, "polling-delay", 1000);
  338. trips_np = ofnode_path("/thermal-zones/cpu-thermal/trips");
  339. ofnode_for_each_subnode(trips_np, trips_np) {
  340. const char *type;
  341. type = ofnode_get_property(trips_np, "type", NULL);
  342. if (!type)
  343. continue;
  344. if (!strcmp(type, "critical"))
  345. pdata->critical = ofnode_read_u32_default(trips_np, "temperature", 85);
  346. else if (strcmp(type, "passive") == 0)
  347. pdata->alert = ofnode_read_u32_default(trips_np, "temperature", 80);
  348. else
  349. continue;
  350. }
  351. debug("id %d polling_delay %d, critical %d, alert %d\n",
  352. pdata->id, pdata->polling_delay, pdata->critical, pdata->alert);
  353. return 0;
  354. }
  355. static int imx_tmu_probe(struct udevice *dev)
  356. {
  357. struct imx_tmu_plat *pdata = dev_get_platdata(dev);
  358. int ret;
  359. ret = imx_tmu_parse_fdt(dev);
  360. if (ret) {
  361. printf("Error in parsing TMU FDT %d\n", ret);
  362. return ret;
  363. }
  364. if (pdata->zone_node) {
  365. imx_tmu_init(dev);
  366. imx_tmu_calibration(dev);
  367. } else {
  368. imx_tmu_enable_msite(dev);
  369. }
  370. return 0;
  371. }
  372. static const struct udevice_id imx_tmu_ids[] = {
  373. { .compatible = "fsl,imx8mq-tmu", },
  374. { .compatible = "fsl,imx8mm-tmu", .data = FLAGS_VER2, },
  375. { .compatible = "fsl,imx8mp-tmu", .data = FLAGS_VER3, },
  376. { }
  377. };
  378. U_BOOT_DRIVER(imx_tmu) = {
  379. .name = "imx_tmu",
  380. .id = UCLASS_THERMAL,
  381. .ops = &imx_tmu_ops,
  382. .of_match = imx_tmu_ids,
  383. .bind = imx_tmu_bind,
  384. .probe = imx_tmu_probe,
  385. .platdata_auto_alloc_size = sizeof(struct imx_tmu_plat),
  386. .flags = DM_FLAG_PRE_RELOC,
  387. };