spmi-msm.c 5.0 KB

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  1. // SPDX-License-Identifier: BSD-3-Clause
  2. /*
  3. * Qualcomm SPMI bus driver
  4. *
  5. * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
  6. *
  7. * Loosely based on Little Kernel driver
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <fdtdec.h>
  13. #include <asm/io.h>
  14. #include <dm/device_compat.h>
  15. #include <spmi/spmi.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /* PMIC Arbiter configuration registers */
  18. #define PMIC_ARB_VERSION 0x0000
  19. #define PMIC_ARB_VERSION_V2_MIN 0x20010000
  20. #define ARB_CHANNEL_OFFSET(n) (0x4 * (n))
  21. #define SPMI_CH_OFFSET(chnl) ((chnl) * 0x8000)
  22. #define SPMI_REG_CMD0 0x0
  23. #define SPMI_REG_CONFIG 0x4
  24. #define SPMI_REG_STATUS 0x8
  25. #define SPMI_REG_WDATA 0x10
  26. #define SPMI_REG_RDATA 0x18
  27. #define SPMI_CMD_OPCODE_SHIFT 27
  28. #define SPMI_CMD_SLAVE_ID_SHIFT 20
  29. #define SPMI_CMD_ADDR_SHIFT 12
  30. #define SPMI_CMD_ADDR_OFFSET_SHIFT 4
  31. #define SPMI_CMD_BYTE_CNT_SHIFT 0
  32. #define SPMI_CMD_EXT_REG_WRITE_LONG 0x00
  33. #define SPMI_CMD_EXT_REG_READ_LONG 0x01
  34. #define SPMI_STATUS_DONE 0x1
  35. #define SPMI_MAX_CHANNELS 128
  36. #define SPMI_MAX_SLAVES 16
  37. #define SPMI_MAX_PERIPH 256
  38. struct msm_spmi_priv {
  39. phys_addr_t arb_chnl; /* ARB channel mapping base */
  40. phys_addr_t spmi_core; /* SPMI core */
  41. phys_addr_t spmi_obs; /* SPMI observer */
  42. /* SPMI channel map */
  43. uint8_t channel_map[SPMI_MAX_SLAVES][SPMI_MAX_PERIPH];
  44. };
  45. static int msm_spmi_write(struct udevice *dev, int usid, int pid, int off,
  46. uint8_t val)
  47. {
  48. struct msm_spmi_priv *priv = dev_get_priv(dev);
  49. unsigned channel;
  50. uint32_t reg = 0;
  51. if (usid >= SPMI_MAX_SLAVES)
  52. return -EIO;
  53. if (pid >= SPMI_MAX_PERIPH)
  54. return -EIO;
  55. channel = priv->channel_map[usid][pid];
  56. /* Disable IRQ mode for the current channel*/
  57. writel(0x0, priv->spmi_core + SPMI_CH_OFFSET(channel) +
  58. SPMI_REG_CONFIG);
  59. /* Write single byte */
  60. writel(val, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_WDATA);
  61. /* Prepare write command */
  62. reg |= SPMI_CMD_EXT_REG_WRITE_LONG << SPMI_CMD_OPCODE_SHIFT;
  63. reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
  64. reg |= (pid << SPMI_CMD_ADDR_SHIFT);
  65. reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
  66. reg |= 1; /* byte count */
  67. /* Send write command */
  68. writel(reg, priv->spmi_core + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
  69. /* Wait till CMD DONE status */
  70. reg = 0;
  71. while (!reg) {
  72. reg = readl(priv->spmi_core + SPMI_CH_OFFSET(channel) +
  73. SPMI_REG_STATUS);
  74. }
  75. if (reg ^ SPMI_STATUS_DONE) {
  76. printf("SPMI write failure.\n");
  77. return -EIO;
  78. }
  79. return 0;
  80. }
  81. static int msm_spmi_read(struct udevice *dev, int usid, int pid, int off)
  82. {
  83. struct msm_spmi_priv *priv = dev_get_priv(dev);
  84. unsigned channel;
  85. uint32_t reg = 0;
  86. if (usid >= SPMI_MAX_SLAVES)
  87. return -EIO;
  88. if (pid >= SPMI_MAX_PERIPH)
  89. return -EIO;
  90. channel = priv->channel_map[usid][pid];
  91. /* Disable IRQ mode for the current channel*/
  92. writel(0x0, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CONFIG);
  93. /* Prepare read command */
  94. reg |= SPMI_CMD_EXT_REG_READ_LONG << SPMI_CMD_OPCODE_SHIFT;
  95. reg |= (usid << SPMI_CMD_SLAVE_ID_SHIFT);
  96. reg |= (pid << SPMI_CMD_ADDR_SHIFT);
  97. reg |= (off << SPMI_CMD_ADDR_OFFSET_SHIFT);
  98. reg |= 1; /* byte count */
  99. /* Request read */
  100. writel(reg, priv->spmi_obs + SPMI_CH_OFFSET(channel) + SPMI_REG_CMD0);
  101. /* Wait till CMD DONE status */
  102. reg = 0;
  103. while (!reg) {
  104. reg = readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
  105. SPMI_REG_STATUS);
  106. }
  107. if (reg ^ SPMI_STATUS_DONE) {
  108. printf("SPMI read failure.\n");
  109. return -EIO;
  110. }
  111. /* Read the data */
  112. return readl(priv->spmi_obs + SPMI_CH_OFFSET(channel) +
  113. SPMI_REG_RDATA) & 0xFF;
  114. }
  115. static struct dm_spmi_ops msm_spmi_ops = {
  116. .read = msm_spmi_read,
  117. .write = msm_spmi_write,
  118. };
  119. static int msm_spmi_probe(struct udevice *dev)
  120. {
  121. struct udevice *parent = dev->parent;
  122. struct msm_spmi_priv *priv = dev_get_priv(dev);
  123. int node = dev_of_offset(dev);
  124. u32 hw_ver;
  125. bool is_v1;
  126. int i;
  127. priv->arb_chnl = dev_read_addr(dev);
  128. priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
  129. dev_of_offset(parent), node, "reg", 1, NULL, false);
  130. priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
  131. dev_of_offset(parent), node, "reg", 2, NULL, false);
  132. hw_ver = readl(priv->arb_chnl + PMIC_ARB_VERSION - 0x800);
  133. is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN);
  134. dev_dbg(dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), hw_ver);
  135. if (priv->arb_chnl == FDT_ADDR_T_NONE ||
  136. priv->spmi_core == FDT_ADDR_T_NONE ||
  137. priv->spmi_obs == FDT_ADDR_T_NONE)
  138. return -EINVAL;
  139. /* Scan peripherals connected to each SPMI channel */
  140. for (i = 0; i < SPMI_MAX_PERIPH ; i++) {
  141. uint32_t periph = readl(priv->arb_chnl + ARB_CHANNEL_OFFSET(i));
  142. uint8_t slave_id = (periph & 0xf0000) >> 16;
  143. uint8_t pid = (periph & 0xff00) >> 8;
  144. priv->channel_map[slave_id][pid] = i;
  145. }
  146. return 0;
  147. }
  148. static const struct udevice_id msm_spmi_ids[] = {
  149. { .compatible = "qcom,spmi-pmic-arb" },
  150. { }
  151. };
  152. U_BOOT_DRIVER(msm_spmi) = {
  153. .name = "msm_spmi",
  154. .id = UCLASS_SPMI,
  155. .of_match = msm_spmi_ids,
  156. .ops = &msm_spmi_ops,
  157. .probe = msm_spmi_probe,
  158. .priv_auto_alloc_size = sizeof(struct msm_spmi_priv),
  159. };