zynq_spi.c 9.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Xilinx, Inc.
  4. * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
  5. *
  6. * Xilinx Zynq PS SPI controller driver (master mode only)
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <dm/device_compat.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <spi.h>
  14. #include <time.h>
  15. #include <clk.h>
  16. #include <asm/io.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
  21. #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
  22. #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
  23. #define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
  24. #define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
  25. #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
  26. #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
  27. #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
  28. #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
  29. #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
  30. #define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
  31. #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
  32. #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
  33. #define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
  34. #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
  35. #define ZYNQ_SPI_FIFO_DEPTH 128
  36. #define ZYNQ_SPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
  37. /* zynq spi register set */
  38. struct zynq_spi_regs {
  39. u32 cr; /* 0x00 */
  40. u32 isr; /* 0x04 */
  41. u32 ier; /* 0x08 */
  42. u32 idr; /* 0x0C */
  43. u32 imr; /* 0x10 */
  44. u32 enr; /* 0x14 */
  45. u32 dr; /* 0x18 */
  46. u32 txdr; /* 0x1C */
  47. u32 rxdr; /* 0x20 */
  48. };
  49. /* zynq spi platform data */
  50. struct zynq_spi_platdata {
  51. struct zynq_spi_regs *regs;
  52. u32 frequency; /* input frequency */
  53. u32 speed_hz;
  54. uint deactivate_delay_us; /* Delay to wait after deactivate */
  55. uint activate_delay_us; /* Delay to wait after activate */
  56. };
  57. /* zynq spi priv */
  58. struct zynq_spi_priv {
  59. struct zynq_spi_regs *regs;
  60. u8 cs;
  61. u8 mode;
  62. ulong last_transaction_us; /* Time of last transaction end */
  63. u8 fifo_depth;
  64. u32 freq; /* required frequency */
  65. };
  66. static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
  67. {
  68. struct zynq_spi_platdata *plat = bus->platdata;
  69. const void *blob = gd->fdt_blob;
  70. int node = dev_of_offset(bus);
  71. plat->regs = dev_read_addr_ptr(bus);
  72. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  73. "spi-deactivate-delay", 0);
  74. plat->activate_delay_us = fdtdec_get_int(blob, node,
  75. "spi-activate-delay", 0);
  76. return 0;
  77. }
  78. static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
  79. {
  80. struct zynq_spi_regs *regs = priv->regs;
  81. u32 confr;
  82. /* Disable SPI */
  83. confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
  84. writel(~confr, &regs->enr);
  85. /* Disable Interrupts */
  86. writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
  87. /* Clear RX FIFO */
  88. while (readl(&regs->isr) &
  89. ZYNQ_SPI_IXR_RXNEMPTY_MASK)
  90. readl(&regs->rxdr);
  91. /* Clear Interrupts */
  92. writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
  93. /* Manual slave select and Auto start */
  94. confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
  95. ZYNQ_SPI_CR_MSTREN_MASK;
  96. confr &= ~ZYNQ_SPI_CR_MSA_MASK;
  97. writel(confr, &regs->cr);
  98. /* Enable SPI */
  99. writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
  100. }
  101. static int zynq_spi_probe(struct udevice *bus)
  102. {
  103. struct zynq_spi_platdata *plat = dev_get_platdata(bus);
  104. struct zynq_spi_priv *priv = dev_get_priv(bus);
  105. struct clk clk;
  106. unsigned long clock;
  107. int ret;
  108. priv->regs = plat->regs;
  109. priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
  110. ret = clk_get_by_name(bus, "ref_clk", &clk);
  111. if (ret < 0) {
  112. dev_err(bus, "failed to get clock\n");
  113. return ret;
  114. }
  115. clock = clk_get_rate(&clk);
  116. if (IS_ERR_VALUE(clock)) {
  117. dev_err(bus, "failed to get rate\n");
  118. return clock;
  119. }
  120. ret = clk_enable(&clk);
  121. if (ret && ret != -ENOSYS) {
  122. dev_err(bus, "failed to enable clock\n");
  123. return ret;
  124. }
  125. /* init the zynq spi hw */
  126. zynq_spi_init_hw(priv);
  127. plat->frequency = clock;
  128. plat->speed_hz = plat->frequency / 2;
  129. debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
  130. return 0;
  131. }
  132. static void spi_cs_activate(struct udevice *dev)
  133. {
  134. struct udevice *bus = dev->parent;
  135. struct zynq_spi_platdata *plat = bus->platdata;
  136. struct zynq_spi_priv *priv = dev_get_priv(bus);
  137. struct zynq_spi_regs *regs = priv->regs;
  138. u32 cr;
  139. /* If it's too soon to do another transaction, wait */
  140. if (plat->deactivate_delay_us && priv->last_transaction_us) {
  141. ulong delay_us; /* The delay completed so far */
  142. delay_us = timer_get_us() - priv->last_transaction_us;
  143. if (delay_us < plat->deactivate_delay_us)
  144. udelay(plat->deactivate_delay_us - delay_us);
  145. }
  146. clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
  147. cr = readl(&regs->cr);
  148. /*
  149. * CS cal logic: CS[13:10]
  150. * xxx0 - cs0
  151. * xx01 - cs1
  152. * x011 - cs2
  153. */
  154. cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
  155. writel(cr, &regs->cr);
  156. if (plat->activate_delay_us)
  157. udelay(plat->activate_delay_us);
  158. }
  159. static void spi_cs_deactivate(struct udevice *dev)
  160. {
  161. struct udevice *bus = dev->parent;
  162. struct zynq_spi_platdata *plat = bus->platdata;
  163. struct zynq_spi_priv *priv = dev_get_priv(bus);
  164. struct zynq_spi_regs *regs = priv->regs;
  165. setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
  166. /* Remember time of this transaction so we can honour the bus delay */
  167. if (plat->deactivate_delay_us)
  168. priv->last_transaction_us = timer_get_us();
  169. }
  170. static int zynq_spi_claim_bus(struct udevice *dev)
  171. {
  172. struct udevice *bus = dev->parent;
  173. struct zynq_spi_priv *priv = dev_get_priv(bus);
  174. struct zynq_spi_regs *regs = priv->regs;
  175. writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
  176. return 0;
  177. }
  178. static int zynq_spi_release_bus(struct udevice *dev)
  179. {
  180. struct udevice *bus = dev->parent;
  181. struct zynq_spi_priv *priv = dev_get_priv(bus);
  182. struct zynq_spi_regs *regs = priv->regs;
  183. u32 confr;
  184. confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
  185. writel(~confr, &regs->enr);
  186. return 0;
  187. }
  188. static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
  189. const void *dout, void *din, unsigned long flags)
  190. {
  191. struct udevice *bus = dev->parent;
  192. struct zynq_spi_priv *priv = dev_get_priv(bus);
  193. struct zynq_spi_regs *regs = priv->regs;
  194. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  195. u32 len = bitlen / 8;
  196. u32 tx_len = len, rx_len = len, tx_tvl;
  197. const u8 *tx_buf = dout;
  198. u8 *rx_buf = din, buf;
  199. u32 ts, status;
  200. debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
  201. bus->seq, slave_plat->cs, bitlen, len, flags);
  202. if (bitlen % 8) {
  203. debug("spi_xfer: Non byte aligned SPI transfer\n");
  204. return -1;
  205. }
  206. priv->cs = slave_plat->cs;
  207. if (flags & SPI_XFER_BEGIN)
  208. spi_cs_activate(dev);
  209. while (rx_len > 0) {
  210. /* Write the data into TX FIFO - tx threshold is fifo_depth */
  211. tx_tvl = 0;
  212. while ((tx_tvl < priv->fifo_depth) && tx_len) {
  213. if (tx_buf)
  214. buf = *tx_buf++;
  215. else
  216. buf = 0;
  217. writel(buf, &regs->txdr);
  218. tx_len--;
  219. tx_tvl++;
  220. }
  221. /* Check TX FIFO completion */
  222. ts = get_timer(0);
  223. status = readl(&regs->isr);
  224. while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
  225. if (get_timer(ts) > ZYNQ_SPI_WAIT) {
  226. printf("spi_xfer: Timeout! TX FIFO not full\n");
  227. return -1;
  228. }
  229. status = readl(&regs->isr);
  230. }
  231. /* Read the data from RX FIFO */
  232. status = readl(&regs->isr);
  233. while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
  234. buf = readl(&regs->rxdr);
  235. if (rx_buf)
  236. *rx_buf++ = buf;
  237. status = readl(&regs->isr);
  238. rx_len--;
  239. }
  240. }
  241. if (flags & SPI_XFER_END)
  242. spi_cs_deactivate(dev);
  243. return 0;
  244. }
  245. static int zynq_spi_set_speed(struct udevice *bus, uint speed)
  246. {
  247. struct zynq_spi_platdata *plat = bus->platdata;
  248. struct zynq_spi_priv *priv = dev_get_priv(bus);
  249. struct zynq_spi_regs *regs = priv->regs;
  250. uint32_t confr;
  251. u8 baud_rate_val = 0;
  252. if (speed > plat->frequency)
  253. speed = plat->frequency;
  254. /* Set the clock frequency */
  255. confr = readl(&regs->cr);
  256. if (speed == 0) {
  257. /* Set baudrate x8, if the freq is 0 */
  258. baud_rate_val = 0x2;
  259. } else if (plat->speed_hz != speed) {
  260. while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
  261. ((plat->frequency /
  262. (2 << baud_rate_val)) > speed))
  263. baud_rate_val++;
  264. plat->speed_hz = speed / (2 << baud_rate_val);
  265. }
  266. confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
  267. confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
  268. writel(confr, &regs->cr);
  269. priv->freq = speed;
  270. debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
  271. priv->regs, priv->freq);
  272. return 0;
  273. }
  274. static int zynq_spi_set_mode(struct udevice *bus, uint mode)
  275. {
  276. struct zynq_spi_priv *priv = dev_get_priv(bus);
  277. struct zynq_spi_regs *regs = priv->regs;
  278. uint32_t confr;
  279. /* Set the SPI Clock phase and polarities */
  280. confr = readl(&regs->cr);
  281. confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
  282. if (mode & SPI_CPHA)
  283. confr |= ZYNQ_SPI_CR_CPHA_MASK;
  284. if (mode & SPI_CPOL)
  285. confr |= ZYNQ_SPI_CR_CPOL_MASK;
  286. writel(confr, &regs->cr);
  287. priv->mode = mode;
  288. debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
  289. return 0;
  290. }
  291. static const struct dm_spi_ops zynq_spi_ops = {
  292. .claim_bus = zynq_spi_claim_bus,
  293. .release_bus = zynq_spi_release_bus,
  294. .xfer = zynq_spi_xfer,
  295. .set_speed = zynq_spi_set_speed,
  296. .set_mode = zynq_spi_set_mode,
  297. };
  298. static const struct udevice_id zynq_spi_ids[] = {
  299. { .compatible = "xlnx,zynq-spi-r1p6" },
  300. { .compatible = "cdns,spi-r1p6" },
  301. { }
  302. };
  303. U_BOOT_DRIVER(zynq_spi) = {
  304. .name = "zynq_spi",
  305. .id = UCLASS_SPI,
  306. .of_match = zynq_spi_ids,
  307. .ops = &zynq_spi_ops,
  308. .ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
  309. .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
  310. .priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
  311. .probe = zynq_spi_probe,
  312. };