xilinx_spi.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Xilinx SPI driver
  4. *
  5. * Supports 8 bit SPI transfers only, with or w/o FIFO
  6. *
  7. * Based on bfin_spi.c, by way of altera_spi.c
  8. * Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
  9. * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
  10. * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
  11. * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
  12. * Copyright (c) 2005-2008 Analog Devices Inc.
  13. */
  14. #include <config.h>
  15. #include <common.h>
  16. #include <dm.h>
  17. #include <errno.h>
  18. #include <log.h>
  19. #include <malloc.h>
  20. #include <spi.h>
  21. #include <asm/io.h>
  22. #include <wait_bit.h>
  23. #include <linux/bitops.h>
  24. /*
  25. * [0]: http://www.xilinx.com/support/documentation
  26. *
  27. * Xilinx SPI Register Definitions
  28. * [1]: [0]/ip_documentation/xps_spi.pdf
  29. * page 8, Register Descriptions
  30. * [2]: [0]/ip_documentation/axi_spi_ds742.pdf
  31. * page 7, Register Overview Table
  32. */
  33. /* SPI Control Register (spicr), [1] p9, [2] p8 */
  34. #define SPICR_LSB_FIRST BIT(9)
  35. #define SPICR_MASTER_INHIBIT BIT(8)
  36. #define SPICR_MANUAL_SS BIT(7)
  37. #define SPICR_RXFIFO_RESEST BIT(6)
  38. #define SPICR_TXFIFO_RESEST BIT(5)
  39. #define SPICR_CPHA BIT(4)
  40. #define SPICR_CPOL BIT(3)
  41. #define SPICR_MASTER_MODE BIT(2)
  42. #define SPICR_SPE BIT(1)
  43. #define SPICR_LOOP BIT(0)
  44. /* SPI Status Register (spisr), [1] p11, [2] p10 */
  45. #define SPISR_SLAVE_MODE_SELECT BIT(5)
  46. #define SPISR_MODF BIT(4)
  47. #define SPISR_TX_FULL BIT(3)
  48. #define SPISR_TX_EMPTY BIT(2)
  49. #define SPISR_RX_FULL BIT(1)
  50. #define SPISR_RX_EMPTY BIT(0)
  51. /* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
  52. #define SPIDTR_8BIT_MASK GENMASK(7, 0)
  53. #define SPIDTR_16BIT_MASK GENMASK(15, 0)
  54. #define SPIDTR_32BIT_MASK GENMASK(31, 0)
  55. /* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
  56. #define SPIDRR_8BIT_MASK GENMASK(7, 0)
  57. #define SPIDRR_16BIT_MASK GENMASK(15, 0)
  58. #define SPIDRR_32BIT_MASK GENMASK(31, 0)
  59. /* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
  60. #define SPISSR_MASK(cs) (1 << (cs))
  61. #define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
  62. #define SPISSR_OFF ~0UL
  63. /* SPI Software Reset Register (ssr) */
  64. #define SPISSR_RESET_VALUE 0x0a
  65. #define XILSPI_MAX_XFER_BITS 8
  66. #define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
  67. SPICR_SPE)
  68. #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
  69. #define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
  70. #define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */
  71. /* xilinx spi register set */
  72. struct xilinx_spi_regs {
  73. u32 __space0__[7];
  74. u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
  75. u32 ipisr; /* IP Interrupt Status Register (IPISR) */
  76. u32 __space1__;
  77. u32 ipier; /* IP Interrupt Enable Register (IPIER) */
  78. u32 __space2__[5];
  79. u32 srr; /* Softare Reset Register (SRR) */
  80. u32 __space3__[7];
  81. u32 spicr; /* SPI Control Register (SPICR) */
  82. u32 spisr; /* SPI Status Register (SPISR) */
  83. u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
  84. u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
  85. u32 spissr; /* SPI Slave Select Register (SPISSR) */
  86. u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
  87. u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
  88. };
  89. /* xilinx spi priv */
  90. struct xilinx_spi_priv {
  91. struct xilinx_spi_regs *regs;
  92. unsigned int freq;
  93. unsigned int mode;
  94. unsigned int fifo_depth;
  95. u8 startup;
  96. };
  97. static int xilinx_spi_probe(struct udevice *bus)
  98. {
  99. struct xilinx_spi_priv *priv = dev_get_priv(bus);
  100. struct xilinx_spi_regs *regs = priv->regs;
  101. priv->regs = (struct xilinx_spi_regs *)dev_read_addr(bus);
  102. priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
  103. writel(SPISSR_RESET_VALUE, &regs->srr);
  104. return 0;
  105. }
  106. static void spi_cs_activate(struct udevice *dev, uint cs)
  107. {
  108. struct udevice *bus = dev_get_parent(dev);
  109. struct xilinx_spi_priv *priv = dev_get_priv(bus);
  110. struct xilinx_spi_regs *regs = priv->regs;
  111. writel(SPISSR_ACT(cs), &regs->spissr);
  112. }
  113. static void spi_cs_deactivate(struct udevice *dev)
  114. {
  115. struct udevice *bus = dev_get_parent(dev);
  116. struct xilinx_spi_priv *priv = dev_get_priv(bus);
  117. struct xilinx_spi_regs *regs = priv->regs;
  118. writel(SPISSR_OFF, &regs->spissr);
  119. }
  120. static int xilinx_spi_claim_bus(struct udevice *dev)
  121. {
  122. struct udevice *bus = dev_get_parent(dev);
  123. struct xilinx_spi_priv *priv = dev_get_priv(bus);
  124. struct xilinx_spi_regs *regs = priv->regs;
  125. writel(SPISSR_OFF, &regs->spissr);
  126. writel(XILSPI_SPICR_DFLT_ON, &regs->spicr);
  127. return 0;
  128. }
  129. static int xilinx_spi_release_bus(struct udevice *dev)
  130. {
  131. struct udevice *bus = dev_get_parent(dev);
  132. struct xilinx_spi_priv *priv = dev_get_priv(bus);
  133. struct xilinx_spi_regs *regs = priv->regs;
  134. writel(SPISSR_OFF, &regs->spissr);
  135. writel(XILSPI_SPICR_DFLT_OFF, &regs->spicr);
  136. return 0;
  137. }
  138. static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
  139. u32 txbytes)
  140. {
  141. struct xilinx_spi_priv *priv = dev_get_priv(bus);
  142. struct xilinx_spi_regs *regs = priv->regs;
  143. unsigned char d;
  144. u32 i = 0;
  145. while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) &&
  146. i < priv->fifo_depth) {
  147. d = txp ? *txp++ : XILINX_SPI_IDLE_VAL;
  148. debug("spi_xfer: tx:%x ", d);
  149. /* write out and wait for processing (receive data) */
  150. writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);
  151. txbytes--;
  152. i++;
  153. }
  154. return i;
  155. }
  156. static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
  157. {
  158. struct xilinx_spi_priv *priv = dev_get_priv(bus);
  159. struct xilinx_spi_regs *regs = priv->regs;
  160. unsigned char d;
  161. unsigned int i = 0;
  162. while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) {
  163. d = readl(&regs->spidrr) & SPIDRR_8BIT_MASK;
  164. if (rxp)
  165. *rxp++ = d;
  166. debug("spi_xfer: rx:%x\n", d);
  167. rxbytes--;
  168. i++;
  169. }
  170. debug("Rx_done\n");
  171. return i;
  172. }
  173. static void xilinx_spi_startup_block(struct udevice *dev, unsigned int bytes,
  174. const void *dout, void *din)
  175. {
  176. struct udevice *bus = dev_get_parent(dev);
  177. struct xilinx_spi_priv *priv = dev_get_priv(bus);
  178. struct xilinx_spi_regs *regs = priv->regs;
  179. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  180. const unsigned char *txp = dout;
  181. unsigned char *rxp = din;
  182. u32 reg;
  183. u32 txbytes = bytes;
  184. u32 rxbytes = bytes;
  185. /*
  186. * This loop runs two times. First time to send the command.
  187. * Second time to transfer data. After transferring data,
  188. * it sets txp to the initial value for the normal operation.
  189. */
  190. for ( ; priv->startup < 2; priv->startup++) {
  191. xilinx_spi_fill_txfifo(bus, txp, txbytes);
  192. reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
  193. writel(reg, &regs->spicr);
  194. xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
  195. txp = din;
  196. if (priv->startup) {
  197. spi_cs_deactivate(dev);
  198. spi_cs_activate(dev, slave_plat->cs);
  199. txp = dout;
  200. }
  201. }
  202. }
  203. static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
  204. const void *dout, void *din, unsigned long flags)
  205. {
  206. struct udevice *bus = dev_get_parent(dev);
  207. struct xilinx_spi_priv *priv = dev_get_priv(bus);
  208. struct xilinx_spi_regs *regs = priv->regs;
  209. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  210. /* assume spi core configured to do 8 bit transfers */
  211. unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
  212. const unsigned char *txp = dout;
  213. unsigned char *rxp = din;
  214. u32 txbytes = bytes;
  215. u32 rxbytes = bytes;
  216. u32 reg, count;
  217. int ret;
  218. debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
  219. bus->seq, slave_plat->cs, bitlen, bytes, flags);
  220. if (bitlen == 0)
  221. goto done;
  222. if (bitlen % XILSPI_MAX_XFER_BITS) {
  223. printf("XILSPI warning: Not a multiple of %d bits\n",
  224. XILSPI_MAX_XFER_BITS);
  225. flags |= SPI_XFER_END;
  226. goto done;
  227. }
  228. if (flags & SPI_XFER_BEGIN)
  229. spi_cs_activate(dev, slave_plat->cs);
  230. /*
  231. * This is the work around for the startup block issue in
  232. * the spi controller. SPI clock is passing through STARTUP
  233. * block to FLASH. STARTUP block don't provide clock as soon
  234. * as QSPI provides command. So first command fails.
  235. */
  236. xilinx_spi_startup_block(dev, bytes, dout, din);
  237. while (txbytes && rxbytes) {
  238. count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
  239. reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
  240. writel(reg, &regs->spicr);
  241. txbytes -= count;
  242. if (txp)
  243. txp += count;
  244. ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true,
  245. XILINX_SPISR_TIMEOUT, false);
  246. if (ret < 0) {
  247. printf("XILSPI error: Xfer timeout\n");
  248. return ret;
  249. }
  250. debug("txbytes:0x%x,txp:0x%p\n", txbytes, txp);
  251. count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
  252. rxbytes -= count;
  253. if (rxp)
  254. rxp += count;
  255. debug("rxbytes:0x%x rxp:0x%p\n", rxbytes, rxp);
  256. }
  257. done:
  258. if (flags & SPI_XFER_END)
  259. spi_cs_deactivate(dev);
  260. return 0;
  261. }
  262. static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
  263. {
  264. struct xilinx_spi_priv *priv = dev_get_priv(bus);
  265. priv->freq = speed;
  266. debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
  267. priv->freq);
  268. return 0;
  269. }
  270. static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
  271. {
  272. struct xilinx_spi_priv *priv = dev_get_priv(bus);
  273. struct xilinx_spi_regs *regs = priv->regs;
  274. uint32_t spicr;
  275. spicr = readl(&regs->spicr);
  276. if (mode & SPI_LSB_FIRST)
  277. spicr |= SPICR_LSB_FIRST;
  278. if (mode & SPI_CPHA)
  279. spicr |= SPICR_CPHA;
  280. if (mode & SPI_CPOL)
  281. spicr |= SPICR_CPOL;
  282. if (mode & SPI_LOOP)
  283. spicr |= SPICR_LOOP;
  284. writel(spicr, &regs->spicr);
  285. priv->mode = mode;
  286. debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
  287. priv->mode);
  288. return 0;
  289. }
  290. static const struct dm_spi_ops xilinx_spi_ops = {
  291. .claim_bus = xilinx_spi_claim_bus,
  292. .release_bus = xilinx_spi_release_bus,
  293. .xfer = xilinx_spi_xfer,
  294. .set_speed = xilinx_spi_set_speed,
  295. .set_mode = xilinx_spi_set_mode,
  296. };
  297. static const struct udevice_id xilinx_spi_ids[] = {
  298. { .compatible = "xlnx,xps-spi-2.00.a" },
  299. { .compatible = "xlnx,xps-spi-2.00.b" },
  300. { }
  301. };
  302. U_BOOT_DRIVER(xilinx_spi) = {
  303. .name = "xilinx_spi",
  304. .id = UCLASS_SPI,
  305. .of_match = xilinx_spi_ids,
  306. .ops = &xilinx_spi_ops,
  307. .priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
  308. .probe = xilinx_spi_probe,
  309. };