uniphier_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * uniphier_spi.c - Socionext UniPhier SPI driver
  4. * Copyright 2019 Socionext, Inc.
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <time.h>
  11. #include <dm/device_compat.h>
  12. #include <linux/bitfield.h>
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. #include <linux/io.h>
  16. #include <spi.h>
  17. #include <wait_bit.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define SSI_CTL 0x00
  20. #define SSI_CTL_EN BIT(0)
  21. #define SSI_CKS 0x04
  22. #define SSI_CKS_CKRAT_MASK GENMASK(7, 0)
  23. #define SSI_CKS_CKPHS BIT(14)
  24. #define SSI_CKS_CKINIT BIT(13)
  25. #define SSI_CKS_CKDLY BIT(12)
  26. #define SSI_TXWDS 0x08
  27. #define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8)
  28. #define SSI_TXWDS_TDTF_MASK GENMASK(7, 6)
  29. #define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0)
  30. #define SSI_RXWDS 0x0c
  31. #define SSI_RXWDS_RDTF_MASK GENMASK(7, 6)
  32. #define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0)
  33. #define SSI_FPS 0x10
  34. #define SSI_FPS_FSPOL BIT(15)
  35. #define SSI_FPS_FSTRT BIT(14)
  36. #define SSI_SR 0x14
  37. #define SSI_SR_BUSY BIT(7)
  38. #define SSI_SR_TNF BIT(5)
  39. #define SSI_SR_RNE BIT(0)
  40. #define SSI_IE 0x18
  41. #define SSI_IC 0x1c
  42. #define SSI_IC_TCIC BIT(4)
  43. #define SSI_IC_RCIC BIT(3)
  44. #define SSI_IC_RORIC BIT(0)
  45. #define SSI_FC 0x20
  46. #define SSI_FC_TXFFL BIT(12)
  47. #define SSI_FC_TXFTH_MASK GENMASK(11, 8)
  48. #define SSI_FC_RXFFL BIT(4)
  49. #define SSI_FC_RXFTH_MASK GENMASK(3, 0)
  50. #define SSI_XDR 0x24 /* TXDR for write, RXDR for read */
  51. #define SSI_FIFO_DEPTH 8U
  52. #define SSI_REG_TIMEOUT (CONFIG_SYS_HZ / 100) /* 10 ms */
  53. #define SSI_XFER_TIMEOUT (CONFIG_SYS_HZ) /* 1 sec */
  54. #define SSI_CLK 50000000 /* internal I/O clock: 50MHz */
  55. struct uniphier_spi_platdata {
  56. void __iomem *base;
  57. u32 frequency; /* input frequency */
  58. u32 speed_hz;
  59. uint deactivate_delay_us; /* Delay to wait after deactivate */
  60. uint activate_delay_us; /* Delay to wait after activate */
  61. };
  62. struct uniphier_spi_priv {
  63. void __iomem *base;
  64. u8 mode;
  65. u8 fifo_depth;
  66. u8 bits_per_word;
  67. ulong last_transaction_us; /* Time of last transaction end */
  68. };
  69. static void uniphier_spi_enable(struct uniphier_spi_priv *priv, int enable)
  70. {
  71. u32 val;
  72. val = readl(priv->base + SSI_CTL);
  73. if (enable)
  74. val |= SSI_CTL_EN;
  75. else
  76. val &= ~SSI_CTL_EN;
  77. writel(val, priv->base + SSI_CTL);
  78. }
  79. static void uniphier_spi_regdump(struct uniphier_spi_priv *priv)
  80. {
  81. pr_debug("CTL %08x\n", readl(priv->base + SSI_CTL));
  82. pr_debug("CKS %08x\n", readl(priv->base + SSI_CKS));
  83. pr_debug("TXWDS %08x\n", readl(priv->base + SSI_TXWDS));
  84. pr_debug("RXWDS %08x\n", readl(priv->base + SSI_RXWDS));
  85. pr_debug("FPS %08x\n", readl(priv->base + SSI_FPS));
  86. pr_debug("SR %08x\n", readl(priv->base + SSI_SR));
  87. pr_debug("IE %08x\n", readl(priv->base + SSI_IE));
  88. pr_debug("IC %08x\n", readl(priv->base + SSI_IC));
  89. pr_debug("FC %08x\n", readl(priv->base + SSI_FC));
  90. pr_debug("XDR %08x\n", readl(priv->base + SSI_XDR));
  91. }
  92. static void spi_cs_activate(struct udevice *dev)
  93. {
  94. struct udevice *bus = dev->parent;
  95. struct uniphier_spi_platdata *plat = bus->platdata;
  96. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  97. ulong delay_us; /* The delay completed so far */
  98. u32 val;
  99. /* If it's too soon to do another transaction, wait */
  100. if (plat->deactivate_delay_us && priv->last_transaction_us) {
  101. delay_us = timer_get_us() - priv->last_transaction_us;
  102. if (delay_us < plat->deactivate_delay_us)
  103. udelay(plat->deactivate_delay_us - delay_us);
  104. }
  105. val = readl(priv->base + SSI_FPS);
  106. if (priv->mode & SPI_CS_HIGH)
  107. val |= SSI_FPS_FSPOL;
  108. else
  109. val &= ~SSI_FPS_FSPOL;
  110. writel(val, priv->base + SSI_FPS);
  111. if (plat->activate_delay_us)
  112. udelay(plat->activate_delay_us);
  113. }
  114. static void spi_cs_deactivate(struct udevice *dev)
  115. {
  116. struct udevice *bus = dev->parent;
  117. struct uniphier_spi_platdata *plat = bus->platdata;
  118. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  119. u32 val;
  120. val = readl(priv->base + SSI_FPS);
  121. if (priv->mode & SPI_CS_HIGH)
  122. val &= ~SSI_FPS_FSPOL;
  123. else
  124. val |= SSI_FPS_FSPOL;
  125. writel(val, priv->base + SSI_FPS);
  126. /* Remember time of this transaction so we can honour the bus delay */
  127. if (plat->deactivate_delay_us)
  128. priv->last_transaction_us = timer_get_us();
  129. }
  130. static int uniphier_spi_claim_bus(struct udevice *dev)
  131. {
  132. struct udevice *bus = dev->parent;
  133. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  134. u32 val, size;
  135. uniphier_spi_enable(priv, false);
  136. /* disable interrupts */
  137. writel(0, priv->base + SSI_IE);
  138. /* bits_per_word */
  139. size = priv->bits_per_word;
  140. val = readl(priv->base + SSI_TXWDS);
  141. val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK);
  142. val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size);
  143. val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size);
  144. writel(val, priv->base + SSI_TXWDS);
  145. val = readl(priv->base + SSI_RXWDS);
  146. val &= ~SSI_RXWDS_DTLEN_MASK;
  147. val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size);
  148. writel(val, priv->base + SSI_RXWDS);
  149. /* reset FIFOs */
  150. val = SSI_FC_TXFFL | SSI_FC_RXFFL;
  151. writel(val, priv->base + SSI_FC);
  152. /* FIFO threthold */
  153. val = readl(priv->base + SSI_FC);
  154. val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);
  155. val |= FIELD_PREP(SSI_FC_TXFTH_MASK, priv->fifo_depth);
  156. val |= FIELD_PREP(SSI_FC_RXFTH_MASK, priv->fifo_depth);
  157. writel(val, priv->base + SSI_FC);
  158. /* clear interrupts */
  159. writel(SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC,
  160. priv->base + SSI_IC);
  161. uniphier_spi_enable(priv, true);
  162. return 0;
  163. }
  164. static int uniphier_spi_release_bus(struct udevice *dev)
  165. {
  166. struct udevice *bus = dev->parent;
  167. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  168. uniphier_spi_enable(priv, false);
  169. return 0;
  170. }
  171. static int uniphier_spi_xfer(struct udevice *dev, unsigned int bitlen,
  172. const void *dout, void *din, unsigned long flags)
  173. {
  174. struct udevice *bus = dev->parent;
  175. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  176. const u8 *tx_buf = dout;
  177. u8 *rx_buf = din, buf;
  178. u32 len = bitlen / 8;
  179. u32 tx_len, rx_len;
  180. u32 ts, status;
  181. int ret = 0;
  182. if (bitlen % 8) {
  183. dev_err(dev, "Non byte aligned SPI transfer\n");
  184. return -EINVAL;
  185. }
  186. if (flags & SPI_XFER_BEGIN)
  187. spi_cs_activate(dev);
  188. uniphier_spi_enable(priv, true);
  189. ts = get_timer(0);
  190. tx_len = len;
  191. rx_len = len;
  192. uniphier_spi_regdump(priv);
  193. while (tx_len || rx_len) {
  194. ret = wait_for_bit_le32(priv->base + SSI_SR, SSI_SR_BUSY, false,
  195. SSI_REG_TIMEOUT * 1000, false);
  196. if (ret) {
  197. if (ret == -ETIMEDOUT)
  198. dev_err(dev, "access timeout\n");
  199. break;
  200. }
  201. status = readl(priv->base + SSI_SR);
  202. /* write the data into TX */
  203. if (tx_len && (status & SSI_SR_TNF)) {
  204. buf = tx_buf ? *tx_buf++ : 0;
  205. writel(buf, priv->base + SSI_XDR);
  206. tx_len--;
  207. }
  208. /* read the data from RX */
  209. if (rx_len && (status & SSI_SR_RNE)) {
  210. buf = readl(priv->base + SSI_XDR);
  211. if (rx_buf)
  212. *rx_buf++ = buf;
  213. rx_len--;
  214. }
  215. if (get_timer(ts) >= SSI_XFER_TIMEOUT) {
  216. dev_err(dev, "transfer timeout\n");
  217. ret = -ETIMEDOUT;
  218. break;
  219. }
  220. }
  221. if (flags & SPI_XFER_END)
  222. spi_cs_deactivate(dev);
  223. uniphier_spi_enable(priv, false);
  224. return ret;
  225. }
  226. static int uniphier_spi_set_speed(struct udevice *bus, uint speed)
  227. {
  228. struct uniphier_spi_platdata *plat = bus->platdata;
  229. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  230. u32 val, ckdiv;
  231. if (speed > plat->frequency)
  232. speed = plat->frequency;
  233. /* baudrate */
  234. ckdiv = DIV_ROUND_UP(SSI_CLK, speed);
  235. ckdiv = round_up(ckdiv, 2);
  236. val = readl(priv->base + SSI_CKS);
  237. val &= ~SSI_CKS_CKRAT_MASK;
  238. val |= ckdiv & SSI_CKS_CKRAT_MASK;
  239. writel(val, priv->base + SSI_CKS);
  240. return 0;
  241. }
  242. static int uniphier_spi_set_mode(struct udevice *bus, uint mode)
  243. {
  244. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  245. u32 val1, val2;
  246. /*
  247. * clock setting
  248. * CKPHS capture timing. 0:rising edge, 1:falling edge
  249. * CKINIT clock initial level. 0:low, 1:high
  250. * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT
  251. * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock)
  252. *
  253. * frame setting
  254. * FSPOL frame signal porarity. 0: low, 1: high
  255. * FSTRT start frame timing
  256. * 0: rising edge of clock, 1: falling edge of clock
  257. */
  258. val1 = readl(priv->base + SSI_CKS);
  259. val2 = readl(priv->base + SSI_FPS);
  260. switch (mode & (SPI_CPOL | SPI_CPHA)) {
  261. case SPI_MODE_0:
  262. /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */
  263. val1 |= SSI_CKS_CKPHS | SSI_CKS_CKDLY;
  264. val1 &= ~SSI_CKS_CKINIT;
  265. val2 &= ~SSI_FPS_FSTRT;
  266. break;
  267. case SPI_MODE_1:
  268. /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */
  269. val1 &= ~(SSI_CKS_CKPHS | SSI_CKS_CKINIT | SSI_CKS_CKDLY);
  270. val2 |= SSI_FPS_FSTRT;
  271. break;
  272. case SPI_MODE_2:
  273. /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */
  274. val1 |= SSI_CKS_CKINIT | SSI_CKS_CKDLY;
  275. val1 &= ~SSI_CKS_CKPHS;
  276. val2 |= SSI_FPS_FSTRT;
  277. break;
  278. case SPI_MODE_3:
  279. /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */
  280. val1 |= SSI_CKS_CKPHS | SSI_CKS_CKINIT;
  281. val1 &= ~SSI_CKS_CKDLY;
  282. val2 &= ~SSI_FPS_FSTRT;
  283. break;
  284. }
  285. writel(val1, priv->base + SSI_CKS);
  286. writel(val2, priv->base + SSI_FPS);
  287. /* format */
  288. val1 = readl(priv->base + SSI_TXWDS);
  289. val2 = readl(priv->base + SSI_RXWDS);
  290. if (mode & SPI_LSB_FIRST) {
  291. val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1);
  292. val2 |= FIELD_PREP(SSI_RXWDS_RDTF_MASK, 1);
  293. }
  294. writel(val1, priv->base + SSI_TXWDS);
  295. writel(val2, priv->base + SSI_RXWDS);
  296. priv->mode = mode;
  297. return 0;
  298. }
  299. static int uniphier_spi_ofdata_to_platdata(struct udevice *bus)
  300. {
  301. struct uniphier_spi_platdata *plat = bus->platdata;
  302. const void *blob = gd->fdt_blob;
  303. int node = dev_of_offset(bus);
  304. plat->base = dev_read_addr_ptr(bus);
  305. plat->frequency =
  306. fdtdec_get_int(blob, node, "spi-max-frequency", 12500000);
  307. plat->deactivate_delay_us =
  308. fdtdec_get_int(blob, node, "spi-deactivate-delay", 0);
  309. plat->activate_delay_us =
  310. fdtdec_get_int(blob, node, "spi-activate-delay", 0);
  311. plat->speed_hz = plat->frequency / 2;
  312. return 0;
  313. }
  314. static int uniphier_spi_probe(struct udevice *bus)
  315. {
  316. struct uniphier_spi_platdata *plat = dev_get_platdata(bus);
  317. struct uniphier_spi_priv *priv = dev_get_priv(bus);
  318. priv->base = plat->base;
  319. priv->fifo_depth = SSI_FIFO_DEPTH;
  320. priv->bits_per_word = 8;
  321. return 0;
  322. }
  323. static const struct dm_spi_ops uniphier_spi_ops = {
  324. .claim_bus = uniphier_spi_claim_bus,
  325. .release_bus = uniphier_spi_release_bus,
  326. .xfer = uniphier_spi_xfer,
  327. .set_speed = uniphier_spi_set_speed,
  328. .set_mode = uniphier_spi_set_mode,
  329. };
  330. static const struct udevice_id uniphier_spi_ids[] = {
  331. { .compatible = "socionext,uniphier-scssi" },
  332. { /* Sentinel */ }
  333. };
  334. U_BOOT_DRIVER(uniphier_spi) = {
  335. .name = "uniphier_spi",
  336. .id = UCLASS_SPI,
  337. .of_match = uniphier_spi_ids,
  338. .ops = &uniphier_spi_ops,
  339. .ofdata_to_platdata = uniphier_spi_ofdata_to_platdata,
  340. .platdata_auto_alloc_size = sizeof(struct uniphier_spi_platdata),
  341. .priv_auto_alloc_size = sizeof(struct uniphier_spi_priv),
  342. .probe = uniphier_spi_probe,
  343. };