tegra20_slink.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * NVIDIA Tegra SPI-SLINK controller
  4. *
  5. * Copyright (c) 2010-2013 NVIDIA Corporation
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <time.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch-tegra/clk_rst.h>
  14. #include <spi.h>
  15. #include <fdtdec.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include "tegra_spi.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /* COMMAND */
  21. #define SLINK_CMD_ENB BIT(31)
  22. #define SLINK_CMD_GO BIT(30)
  23. #define SLINK_CMD_M_S BIT(28)
  24. #define SLINK_CMD_IDLE_SCLK_DRIVE_LOW (0 << 24)
  25. #define SLINK_CMD_IDLE_SCLK_DRIVE_HIGH BIT(24)
  26. #define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24)
  27. #define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24)
  28. #define SLINK_CMD_IDLE_SCLK_MASK (3 << 24)
  29. #define SLINK_CMD_CK_SDA BIT(21)
  30. #define SLINK_CMD_CS_POL BIT(13)
  31. #define SLINK_CMD_CS_VAL BIT(12)
  32. #define SLINK_CMD_CS_SOFT BIT(11)
  33. #define SLINK_CMD_BIT_LENGTH BIT(4)
  34. #define SLINK_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
  35. /* COMMAND2 */
  36. #define SLINK_CMD2_TXEN BIT(30)
  37. #define SLINK_CMD2_RXEN BIT(31)
  38. #define SLINK_CMD2_SS_EN BIT(18)
  39. #define SLINK_CMD2_SS_EN_SHIFT 18
  40. #define SLINK_CMD2_SS_EN_MASK GENMASK(19, 18)
  41. #define SLINK_CMD2_CS_ACTIVE_BETWEEN BIT(17)
  42. /* STATUS */
  43. #define SLINK_STAT_BSY BIT(31)
  44. #define SLINK_STAT_RDY BIT(30)
  45. #define SLINK_STAT_ERR BIT(29)
  46. #define SLINK_STAT_RXF_FLUSH BIT(27)
  47. #define SLINK_STAT_TXF_FLUSH BIT(26)
  48. #define SLINK_STAT_RXF_OVF BIT(25)
  49. #define SLINK_STAT_TXF_UNR BIT(24)
  50. #define SLINK_STAT_RXF_EMPTY BIT(23)
  51. #define SLINK_STAT_RXF_FULL BIT(22)
  52. #define SLINK_STAT_TXF_EMPTY BIT(21)
  53. #define SLINK_STAT_TXF_FULL BIT(20)
  54. #define SLINK_STAT_TXF_OVF BIT(19)
  55. #define SLINK_STAT_RXF_UNR BIT(18)
  56. #define SLINK_STAT_CUR_BLKCNT BIT(15)
  57. /* STATUS2 */
  58. #define SLINK_STAT2_RXF_FULL_CNT BIT(16)
  59. #define SLINK_STAT2_TXF_FULL_CNT BIT(0)
  60. #define SPI_TIMEOUT 1000
  61. #define TEGRA_SPI_MAX_FREQ 52000000
  62. struct spi_regs {
  63. u32 command; /* SLINK_COMMAND_0 register */
  64. u32 command2; /* SLINK_COMMAND2_0 reg */
  65. u32 status; /* SLINK_STATUS_0 register */
  66. u32 reserved; /* Reserved offset 0C */
  67. u32 mas_data; /* SLINK_MAS_DATA_0 reg */
  68. u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
  69. u32 dma_ctl; /* SLINK_DMA_CTL_0 register */
  70. u32 status2; /* SLINK_STATUS2_0 reg */
  71. u32 rsvd[56]; /* 0x20 to 0xFF reserved */
  72. u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */
  73. u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
  74. u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
  75. };
  76. struct tegra30_spi_priv {
  77. struct spi_regs *regs;
  78. unsigned int freq;
  79. unsigned int mode;
  80. int periph_id;
  81. int valid;
  82. int last_transaction_us;
  83. };
  84. struct tegra_spi_slave {
  85. struct spi_slave slave;
  86. struct tegra30_spi_priv *ctrl;
  87. };
  88. static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
  89. {
  90. struct tegra_spi_platdata *plat = bus->platdata;
  91. const void *blob = gd->fdt_blob;
  92. int node = dev_of_offset(bus);
  93. plat->base = dev_read_addr(bus);
  94. plat->periph_id = clock_decode_periph_id(bus);
  95. if (plat->periph_id == PERIPH_ID_NONE) {
  96. debug("%s: could not decode periph id %d\n", __func__,
  97. plat->periph_id);
  98. return -FDT_ERR_NOTFOUND;
  99. }
  100. /* Use 500KHz as a suitable default */
  101. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  102. 500000);
  103. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  104. "spi-deactivate-delay", 0);
  105. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  106. __func__, plat->base, plat->periph_id, plat->frequency,
  107. plat->deactivate_delay_us);
  108. return 0;
  109. }
  110. static int tegra30_spi_probe(struct udevice *bus)
  111. {
  112. struct tegra_spi_platdata *plat = dev_get_platdata(bus);
  113. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  114. priv->regs = (struct spi_regs *)plat->base;
  115. priv->last_transaction_us = timer_get_us();
  116. priv->freq = plat->frequency;
  117. priv->periph_id = plat->periph_id;
  118. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  119. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  120. priv->freq);
  121. return 0;
  122. }
  123. static int tegra30_spi_claim_bus(struct udevice *dev)
  124. {
  125. struct udevice *bus = dev->parent;
  126. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  127. struct spi_regs *regs = priv->regs;
  128. u32 reg;
  129. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  130. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  131. priv->freq);
  132. /* Clear stale status here */
  133. reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
  134. SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
  135. writel(reg, &regs->status);
  136. debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
  137. /* Set master mode and sw controlled CS */
  138. reg = readl(&regs->command);
  139. reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
  140. writel(reg, &regs->command);
  141. debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
  142. return 0;
  143. }
  144. static void spi_cs_activate(struct udevice *dev)
  145. {
  146. struct udevice *bus = dev->parent;
  147. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  148. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  149. /* If it's too soon to do another transaction, wait */
  150. if (pdata->deactivate_delay_us &&
  151. priv->last_transaction_us) {
  152. ulong delay_us; /* The delay completed so far */
  153. delay_us = timer_get_us() - priv->last_transaction_us;
  154. if (delay_us < pdata->deactivate_delay_us)
  155. udelay(pdata->deactivate_delay_us - delay_us);
  156. }
  157. /* CS is negated on Tegra, so drive a 1 to get a 0 */
  158. setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
  159. }
  160. static void spi_cs_deactivate(struct udevice *dev)
  161. {
  162. struct udevice *bus = dev->parent;
  163. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  164. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  165. /* CS is negated on Tegra, so drive a 0 to get a 1 */
  166. clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
  167. /* Remember time of this transaction so we can honour the bus delay */
  168. if (pdata->deactivate_delay_us)
  169. priv->last_transaction_us = timer_get_us();
  170. }
  171. static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
  172. const void *data_out, void *data_in,
  173. unsigned long flags)
  174. {
  175. struct udevice *bus = dev->parent;
  176. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  177. struct spi_regs *regs = priv->regs;
  178. u32 reg, tmpdout, tmpdin = 0;
  179. const u8 *dout = data_out;
  180. u8 *din = data_in;
  181. int num_bytes;
  182. int ret;
  183. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  184. __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
  185. if (bitlen % 8)
  186. return -1;
  187. num_bytes = bitlen / 8;
  188. ret = 0;
  189. reg = readl(&regs->status);
  190. writel(reg, &regs->status); /* Clear all SPI events via R/W */
  191. debug("%s entry: STATUS = %08x\n", __func__, reg);
  192. reg = readl(&regs->status2);
  193. writel(reg, &regs->status2); /* Clear all STATUS2 events via R/W */
  194. debug("%s entry: STATUS2 = %08x\n", __func__, reg);
  195. debug("%s entry: COMMAND = %08x\n", __func__, readl(&regs->command));
  196. clrsetbits_le32(&regs->command2, SLINK_CMD2_SS_EN_MASK,
  197. SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
  198. (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT));
  199. debug("%s entry: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
  200. if (flags & SPI_XFER_BEGIN)
  201. spi_cs_activate(dev);
  202. /* handle data in 32-bit chunks */
  203. while (num_bytes > 0) {
  204. int bytes;
  205. int is_read = 0;
  206. int tm, i;
  207. tmpdout = 0;
  208. bytes = (num_bytes > 4) ? 4 : num_bytes;
  209. if (dout != NULL) {
  210. for (i = 0; i < bytes; ++i)
  211. tmpdout = (tmpdout << 8) | dout[i];
  212. dout += bytes;
  213. }
  214. num_bytes -= bytes;
  215. clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
  216. bytes * 8 - 1);
  217. writel(tmpdout, &regs->tx_fifo);
  218. setbits_le32(&regs->command, SLINK_CMD_GO);
  219. /*
  220. * Wait for SPI transmit FIFO to empty, or to time out.
  221. * The RX FIFO status will be read and cleared last
  222. */
  223. for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
  224. u32 status;
  225. status = readl(&regs->status);
  226. /* We can exit when we've had both RX and TX activity */
  227. if (is_read && (status & SLINK_STAT_TXF_EMPTY))
  228. break;
  229. if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
  230. SLINK_STAT_RDY)
  231. tm++;
  232. else if (!(status & SLINK_STAT_RXF_EMPTY)) {
  233. tmpdin = readl(&regs->rx_fifo);
  234. is_read = 1;
  235. /* swap bytes read in */
  236. if (din != NULL) {
  237. for (i = bytes - 1; i >= 0; --i) {
  238. din[i] = tmpdin & 0xff;
  239. tmpdin >>= 8;
  240. }
  241. din += bytes;
  242. }
  243. }
  244. }
  245. if (tm >= SPI_TIMEOUT)
  246. ret = tm;
  247. /* clear ACK RDY, etc. bits */
  248. writel(readl(&regs->status), &regs->status);
  249. }
  250. if (flags & SPI_XFER_END)
  251. spi_cs_deactivate(dev);
  252. debug("%s: transfer ended. Value=%08x, status = %08x\n",
  253. __func__, tmpdin, readl(&regs->status));
  254. if (ret) {
  255. printf("%s: timeout during SPI transfer, tm %d\n",
  256. __func__, ret);
  257. return -1;
  258. }
  259. return 0;
  260. }
  261. static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
  262. {
  263. struct tegra_spi_platdata *plat = bus->platdata;
  264. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  265. if (speed > plat->frequency)
  266. speed = plat->frequency;
  267. priv->freq = speed;
  268. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  269. return 0;
  270. }
  271. static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
  272. {
  273. struct tegra30_spi_priv *priv = dev_get_priv(bus);
  274. struct spi_regs *regs = priv->regs;
  275. u32 reg;
  276. reg = readl(&regs->command);
  277. /* Set CPOL and CPHA */
  278. reg &= ~(SLINK_CMD_IDLE_SCLK_MASK | SLINK_CMD_CK_SDA);
  279. if (mode & SPI_CPHA)
  280. reg |= SLINK_CMD_CK_SDA;
  281. if (mode & SPI_CPOL)
  282. reg |= SLINK_CMD_IDLE_SCLK_DRIVE_HIGH;
  283. else
  284. reg |= SLINK_CMD_IDLE_SCLK_DRIVE_LOW;
  285. writel(reg, &regs->command);
  286. priv->mode = mode;
  287. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  288. return 0;
  289. }
  290. static const struct dm_spi_ops tegra30_spi_ops = {
  291. .claim_bus = tegra30_spi_claim_bus,
  292. .xfer = tegra30_spi_xfer,
  293. .set_speed = tegra30_spi_set_speed,
  294. .set_mode = tegra30_spi_set_mode,
  295. /*
  296. * cs_info is not needed, since we require all chip selects to be
  297. * in the device tree explicitly
  298. */
  299. };
  300. static const struct udevice_id tegra30_spi_ids[] = {
  301. { .compatible = "nvidia,tegra20-slink" },
  302. { }
  303. };
  304. U_BOOT_DRIVER(tegra30_spi) = {
  305. .name = "tegra20_slink",
  306. .id = UCLASS_SPI,
  307. .of_match = tegra30_spi_ids,
  308. .ops = &tegra30_spi_ops,
  309. .ofdata_to_platdata = tegra30_spi_ofdata_to_platdata,
  310. .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
  311. .priv_auto_alloc_size = sizeof(struct tegra30_spi_priv),
  312. .probe = tegra30_spi_probe,
  313. };