tegra20_sflash.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2010-2013 NVIDIA Corporation
  4. * With help from the mpc8xxx SPI driver
  5. * With more help from omap3_spi SPI driver
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <log.h>
  11. #include <time.h>
  12. #include <asm/io.h>
  13. #include <asm/gpio.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/pinmux.h>
  16. #include <asm/arch-tegra/clk_rst.h>
  17. #include <spi.h>
  18. #include <fdtdec.h>
  19. #include <linux/bitops.h>
  20. #include <linux/delay.h>
  21. #include "tegra_spi.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define SPI_CMD_GO BIT(30)
  24. #define SPI_CMD_ACTIVE_SCLK_SHIFT 26
  25. #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
  26. #define SPI_CMD_CK_SDA BIT(21)
  27. #define SPI_CMD_ACTIVE_SDA_SHIFT 18
  28. #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
  29. #define SPI_CMD_CS_POL BIT(16)
  30. #define SPI_CMD_TXEN BIT(15)
  31. #define SPI_CMD_RXEN BIT(14)
  32. #define SPI_CMD_CS_VAL BIT(13)
  33. #define SPI_CMD_CS_SOFT BIT(12)
  34. #define SPI_CMD_CS_DELAY BIT(9)
  35. #define SPI_CMD_CS3_EN BIT(8)
  36. #define SPI_CMD_CS2_EN BIT(7)
  37. #define SPI_CMD_CS1_EN BIT(6)
  38. #define SPI_CMD_CS0_EN BIT(5)
  39. #define SPI_CMD_BIT_LENGTH BIT(4)
  40. #define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
  41. #define SPI_STAT_BSY BIT(31)
  42. #define SPI_STAT_RDY BIT(30)
  43. #define SPI_STAT_RXF_FLUSH BIT(29)
  44. #define SPI_STAT_TXF_FLUSH BIT(28)
  45. #define SPI_STAT_RXF_UNR BIT(27)
  46. #define SPI_STAT_TXF_OVF BIT(26)
  47. #define SPI_STAT_RXF_EMPTY BIT(25)
  48. #define SPI_STAT_RXF_FULL BIT(24)
  49. #define SPI_STAT_TXF_EMPTY BIT(23)
  50. #define SPI_STAT_TXF_FULL BIT(22)
  51. #define SPI_STAT_SEL_TXRX_N BIT(16)
  52. #define SPI_STAT_CUR_BLKCNT BIT(15)
  53. #define SPI_TIMEOUT 1000
  54. #define TEGRA_SPI_MAX_FREQ 52000000
  55. struct spi_regs {
  56. u32 command; /* SPI_COMMAND_0 register */
  57. u32 status; /* SPI_STATUS_0 register */
  58. u32 rx_cmp; /* SPI_RX_CMP_0 register */
  59. u32 dma_ctl; /* SPI_DMA_CTL_0 register */
  60. u32 tx_fifo; /* SPI_TX_FIFO_0 register */
  61. u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
  62. u32 rx_fifo; /* SPI_RX_FIFO_0 register */
  63. };
  64. struct tegra20_sflash_priv {
  65. struct spi_regs *regs;
  66. unsigned int freq;
  67. unsigned int mode;
  68. int periph_id;
  69. int valid;
  70. int last_transaction_us;
  71. };
  72. int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
  73. struct spi_cs_info *info)
  74. {
  75. /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
  76. if (cs != 0)
  77. return -EINVAL;
  78. else
  79. return 0;
  80. }
  81. static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
  82. {
  83. struct tegra_spi_platdata *plat = bus->platdata;
  84. const void *blob = gd->fdt_blob;
  85. int node = dev_of_offset(bus);
  86. plat->base = dev_read_addr(bus);
  87. plat->periph_id = clock_decode_periph_id(bus);
  88. if (plat->periph_id == PERIPH_ID_NONE) {
  89. debug("%s: could not decode periph id %d\n", __func__,
  90. plat->periph_id);
  91. return -FDT_ERR_NOTFOUND;
  92. }
  93. /* Use 500KHz as a suitable default */
  94. plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
  95. 500000);
  96. plat->deactivate_delay_us = fdtdec_get_int(blob, node,
  97. "spi-deactivate-delay", 0);
  98. debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
  99. __func__, plat->base, plat->periph_id, plat->frequency,
  100. plat->deactivate_delay_us);
  101. return 0;
  102. }
  103. static int tegra20_sflash_probe(struct udevice *bus)
  104. {
  105. struct tegra_spi_platdata *plat = dev_get_platdata(bus);
  106. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  107. priv->regs = (struct spi_regs *)plat->base;
  108. priv->last_transaction_us = timer_get_us();
  109. priv->freq = plat->frequency;
  110. priv->periph_id = plat->periph_id;
  111. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  112. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  113. priv->freq);
  114. return 0;
  115. }
  116. static int tegra20_sflash_claim_bus(struct udevice *dev)
  117. {
  118. struct udevice *bus = dev->parent;
  119. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  120. struct spi_regs *regs = priv->regs;
  121. u32 reg;
  122. /* Change SPI clock to correct frequency, PLLP_OUT0 source */
  123. clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
  124. priv->freq);
  125. /* Clear stale status here */
  126. reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
  127. SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
  128. writel(reg, &regs->status);
  129. debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
  130. /*
  131. * Use sw-controlled CS, so we can clock in data after ReadID, etc.
  132. */
  133. reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
  134. if (priv->mode & 2)
  135. reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
  136. clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
  137. SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
  138. debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
  139. /*
  140. * SPI pins on Tegra20 are muxed - change pinmux later due to UART
  141. * issue.
  142. */
  143. pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
  144. pinmux_tristate_disable(PMUX_PINGRP_LSPI);
  145. pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
  146. return 0;
  147. }
  148. static void spi_cs_activate(struct udevice *dev)
  149. {
  150. struct udevice *bus = dev->parent;
  151. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  152. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  153. /* If it's too soon to do another transaction, wait */
  154. if (pdata->deactivate_delay_us &&
  155. priv->last_transaction_us) {
  156. ulong delay_us; /* The delay completed so far */
  157. delay_us = timer_get_us() - priv->last_transaction_us;
  158. if (delay_us < pdata->deactivate_delay_us)
  159. udelay(pdata->deactivate_delay_us - delay_us);
  160. }
  161. /* CS is negated on Tegra, so drive a 1 to get a 0 */
  162. setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
  163. }
  164. static void spi_cs_deactivate(struct udevice *dev)
  165. {
  166. struct udevice *bus = dev->parent;
  167. struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
  168. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  169. /* CS is negated on Tegra, so drive a 0 to get a 1 */
  170. clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
  171. /* Remember time of this transaction so we can honour the bus delay */
  172. if (pdata->deactivate_delay_us)
  173. priv->last_transaction_us = timer_get_us();
  174. }
  175. static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
  176. const void *data_out, void *data_in,
  177. unsigned long flags)
  178. {
  179. struct udevice *bus = dev->parent;
  180. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  181. struct spi_regs *regs = priv->regs;
  182. u32 reg, tmpdout, tmpdin = 0;
  183. const u8 *dout = data_out;
  184. u8 *din = data_in;
  185. int num_bytes;
  186. int ret;
  187. debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
  188. __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
  189. if (bitlen % 8)
  190. return -1;
  191. num_bytes = bitlen / 8;
  192. ret = 0;
  193. reg = readl(&regs->status);
  194. writel(reg, &regs->status); /* Clear all SPI events via R/W */
  195. debug("spi_xfer entry: STATUS = %08x\n", reg);
  196. reg = readl(&regs->command);
  197. reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
  198. writel(reg, &regs->command);
  199. debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
  200. if (flags & SPI_XFER_BEGIN)
  201. spi_cs_activate(dev);
  202. /* handle data in 32-bit chunks */
  203. while (num_bytes > 0) {
  204. int bytes;
  205. int is_read = 0;
  206. int tm, i;
  207. tmpdout = 0;
  208. bytes = (num_bytes > 4) ? 4 : num_bytes;
  209. if (dout != NULL) {
  210. for (i = 0; i < bytes; ++i)
  211. tmpdout = (tmpdout << 8) | dout[i];
  212. }
  213. num_bytes -= bytes;
  214. if (dout)
  215. dout += bytes;
  216. clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
  217. bytes * 8 - 1);
  218. writel(tmpdout, &regs->tx_fifo);
  219. setbits_le32(&regs->command, SPI_CMD_GO);
  220. /*
  221. * Wait for SPI transmit FIFO to empty, or to time out.
  222. * The RX FIFO status will be read and cleared last
  223. */
  224. for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
  225. u32 status;
  226. status = readl(&regs->status);
  227. /* We can exit when we've had both RX and TX activity */
  228. if (is_read && (status & SPI_STAT_TXF_EMPTY))
  229. break;
  230. if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
  231. SPI_STAT_RDY)
  232. tm++;
  233. else if (!(status & SPI_STAT_RXF_EMPTY)) {
  234. tmpdin = readl(&regs->rx_fifo);
  235. is_read = 1;
  236. /* swap bytes read in */
  237. if (din != NULL) {
  238. for (i = bytes - 1; i >= 0; --i) {
  239. din[i] = tmpdin & 0xff;
  240. tmpdin >>= 8;
  241. }
  242. din += bytes;
  243. }
  244. }
  245. }
  246. if (tm >= SPI_TIMEOUT)
  247. ret = tm;
  248. /* clear ACK RDY, etc. bits */
  249. writel(readl(&regs->status), &regs->status);
  250. }
  251. if (flags & SPI_XFER_END)
  252. spi_cs_deactivate(dev);
  253. debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
  254. tmpdin, readl(&regs->status));
  255. if (ret) {
  256. printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
  257. return -1;
  258. }
  259. return 0;
  260. }
  261. static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
  262. {
  263. struct tegra_spi_platdata *plat = bus->platdata;
  264. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  265. if (speed > plat->frequency)
  266. speed = plat->frequency;
  267. priv->freq = speed;
  268. debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
  269. return 0;
  270. }
  271. static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
  272. {
  273. struct tegra20_sflash_priv *priv = dev_get_priv(bus);
  274. priv->mode = mode;
  275. debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
  276. return 0;
  277. }
  278. static const struct dm_spi_ops tegra20_sflash_ops = {
  279. .claim_bus = tegra20_sflash_claim_bus,
  280. .xfer = tegra20_sflash_xfer,
  281. .set_speed = tegra20_sflash_set_speed,
  282. .set_mode = tegra20_sflash_set_mode,
  283. .cs_info = tegra20_sflash_cs_info,
  284. };
  285. static const struct udevice_id tegra20_sflash_ids[] = {
  286. { .compatible = "nvidia,tegra20-sflash" },
  287. { }
  288. };
  289. U_BOOT_DRIVER(tegra20_sflash) = {
  290. .name = "tegra20_sflash",
  291. .id = UCLASS_SPI,
  292. .of_match = tegra20_sflash_ids,
  293. .ops = &tegra20_sflash_ops,
  294. .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
  295. .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
  296. .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
  297. .probe = tegra20_sflash_probe,
  298. };