stm32_spi.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
  4. *
  5. * Driver for STMicroelectronics Serial peripheral interface (SPI)
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <reset.h>
  14. #include <spi.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include <asm/io.h>
  19. #include <asm/gpio.h>
  20. #include <linux/bitfield.h>
  21. #include <linux/iopoll.h>
  22. /* STM32 SPI registers */
  23. #define STM32_SPI_CR1 0x00
  24. #define STM32_SPI_CR2 0x04
  25. #define STM32_SPI_CFG1 0x08
  26. #define STM32_SPI_CFG2 0x0C
  27. #define STM32_SPI_SR 0x14
  28. #define STM32_SPI_IFCR 0x18
  29. #define STM32_SPI_TXDR 0x20
  30. #define STM32_SPI_RXDR 0x30
  31. #define STM32_SPI_I2SCFGR 0x50
  32. /* STM32_SPI_CR1 bit fields */
  33. #define SPI_CR1_SPE BIT(0)
  34. #define SPI_CR1_MASRX BIT(8)
  35. #define SPI_CR1_CSTART BIT(9)
  36. #define SPI_CR1_CSUSP BIT(10)
  37. #define SPI_CR1_HDDIR BIT(11)
  38. #define SPI_CR1_SSI BIT(12)
  39. /* STM32_SPI_CR2 bit fields */
  40. #define SPI_CR2_TSIZE GENMASK(15, 0)
  41. /* STM32_SPI_CFG1 bit fields */
  42. #define SPI_CFG1_DSIZE GENMASK(4, 0)
  43. #define SPI_CFG1_DSIZE_MIN 3
  44. #define SPI_CFG1_FTHLV_SHIFT 5
  45. #define SPI_CFG1_FTHLV GENMASK(8, 5)
  46. #define SPI_CFG1_MBR_SHIFT 28
  47. #define SPI_CFG1_MBR GENMASK(30, 28)
  48. #define SPI_CFG1_MBR_MIN 0
  49. #define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
  50. /* STM32_SPI_CFG2 bit fields */
  51. #define SPI_CFG2_COMM_SHIFT 17
  52. #define SPI_CFG2_COMM GENMASK(18, 17)
  53. #define SPI_CFG2_MASTER BIT(22)
  54. #define SPI_CFG2_LSBFRST BIT(23)
  55. #define SPI_CFG2_CPHA BIT(24)
  56. #define SPI_CFG2_CPOL BIT(25)
  57. #define SPI_CFG2_SSM BIT(26)
  58. #define SPI_CFG2_AFCNTR BIT(31)
  59. /* STM32_SPI_SR bit fields */
  60. #define SPI_SR_RXP BIT(0)
  61. #define SPI_SR_TXP BIT(1)
  62. #define SPI_SR_EOT BIT(3)
  63. #define SPI_SR_TXTF BIT(4)
  64. #define SPI_SR_OVR BIT(6)
  65. #define SPI_SR_SUSP BIT(11)
  66. #define SPI_SR_RXPLVL_SHIFT 13
  67. #define SPI_SR_RXPLVL GENMASK(14, 13)
  68. #define SPI_SR_RXWNE BIT(15)
  69. /* STM32_SPI_IFCR bit fields */
  70. #define SPI_IFCR_ALL GENMASK(11, 3)
  71. /* STM32_SPI_I2SCFGR bit fields */
  72. #define SPI_I2SCFGR_I2SMOD BIT(0)
  73. #define MAX_CS_COUNT 4
  74. /* SPI Master Baud Rate min/max divisor */
  75. #define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
  76. #define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
  77. #define STM32_SPI_TIMEOUT_US 100000
  78. /* SPI Communication mode */
  79. #define SPI_FULL_DUPLEX 0
  80. #define SPI_SIMPLEX_TX 1
  81. #define SPI_SIMPLEX_RX 2
  82. #define SPI_HALF_DUPLEX 3
  83. struct stm32_spi_priv {
  84. void __iomem *base;
  85. struct clk clk;
  86. struct reset_ctl rst_ctl;
  87. struct gpio_desc cs_gpios[MAX_CS_COUNT];
  88. ulong bus_clk_rate;
  89. unsigned int fifo_size;
  90. unsigned int cur_bpw;
  91. unsigned int cur_hz;
  92. unsigned int cur_xferlen; /* current transfer length in bytes */
  93. unsigned int tx_len; /* number of data to be written in bytes */
  94. unsigned int rx_len; /* number of data to be read in bytes */
  95. const void *tx_buf; /* data to be written, or NULL */
  96. void *rx_buf; /* data to be read, or NULL */
  97. u32 cur_mode;
  98. bool cs_high;
  99. };
  100. static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
  101. {
  102. while ((priv->tx_len > 0) &&
  103. (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
  104. u32 offs = priv->cur_xferlen - priv->tx_len;
  105. if (priv->tx_len >= sizeof(u32) &&
  106. IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
  107. const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
  108. writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
  109. priv->tx_len -= sizeof(u32);
  110. } else if (priv->tx_len >= sizeof(u16) &&
  111. IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
  112. const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
  113. writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
  114. priv->tx_len -= sizeof(u16);
  115. } else {
  116. const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
  117. writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
  118. priv->tx_len -= sizeof(u8);
  119. }
  120. }
  121. debug("%s: %d bytes left\n", __func__, priv->tx_len);
  122. }
  123. static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
  124. {
  125. u32 sr = readl(priv->base + STM32_SPI_SR);
  126. u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
  127. while ((priv->rx_len > 0) &&
  128. ((sr & SPI_SR_RXP) ||
  129. ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
  130. u32 offs = priv->cur_xferlen - priv->rx_len;
  131. if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
  132. (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
  133. u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
  134. *rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
  135. priv->rx_len -= sizeof(u32);
  136. } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
  137. (priv->rx_len >= sizeof(u16) ||
  138. (!(sr & SPI_SR_RXWNE) &&
  139. (rxplvl >= 2 || priv->cur_bpw > 8)))) {
  140. u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
  141. *rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
  142. priv->rx_len -= sizeof(u16);
  143. } else {
  144. u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
  145. *rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
  146. priv->rx_len -= sizeof(u8);
  147. }
  148. sr = readl(priv->base + STM32_SPI_SR);
  149. rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
  150. }
  151. debug("%s: %d bytes left\n", __func__, priv->rx_len);
  152. }
  153. static int stm32_spi_enable(struct stm32_spi_priv *priv)
  154. {
  155. debug("%s\n", __func__);
  156. /* Enable the SPI hardware */
  157. setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
  158. return 0;
  159. }
  160. static int stm32_spi_disable(struct stm32_spi_priv *priv)
  161. {
  162. debug("%s\n", __func__);
  163. /* Disable the SPI hardware */
  164. clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
  165. return 0;
  166. }
  167. static int stm32_spi_claim_bus(struct udevice *slave)
  168. {
  169. struct udevice *bus = dev_get_parent(slave);
  170. struct stm32_spi_priv *priv = dev_get_priv(bus);
  171. debug("%s\n", __func__);
  172. /* Enable the SPI hardware */
  173. return stm32_spi_enable(priv);
  174. }
  175. static int stm32_spi_release_bus(struct udevice *slave)
  176. {
  177. struct udevice *bus = dev_get_parent(slave);
  178. struct stm32_spi_priv *priv = dev_get_priv(bus);
  179. debug("%s\n", __func__);
  180. /* Disable the SPI hardware */
  181. return stm32_spi_disable(priv);
  182. }
  183. static void stm32_spi_stopxfer(struct udevice *dev)
  184. {
  185. struct stm32_spi_priv *priv = dev_get_priv(dev);
  186. u32 cr1, sr;
  187. int ret;
  188. debug("%s\n", __func__);
  189. cr1 = readl(priv->base + STM32_SPI_CR1);
  190. if (!(cr1 & SPI_CR1_SPE))
  191. return;
  192. /* Wait on EOT or suspend the flow */
  193. ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
  194. !(sr & SPI_SR_EOT), 100000);
  195. if (ret < 0) {
  196. if (cr1 & SPI_CR1_CSTART) {
  197. writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
  198. if (readl_poll_timeout(priv->base + STM32_SPI_SR,
  199. sr, !(sr & SPI_SR_SUSP),
  200. 100000) < 0)
  201. dev_err(dev, "Suspend request timeout\n");
  202. }
  203. }
  204. /* clear status flags */
  205. setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
  206. }
  207. static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
  208. {
  209. struct stm32_spi_priv *priv = dev_get_priv(dev);
  210. debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
  211. if (cs >= MAX_CS_COUNT)
  212. return -ENODEV;
  213. if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
  214. return -EINVAL;
  215. if (priv->cs_high)
  216. enable = !enable;
  217. return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
  218. }
  219. static int stm32_spi_set_mode(struct udevice *bus, uint mode)
  220. {
  221. struct stm32_spi_priv *priv = dev_get_priv(bus);
  222. u32 cfg2_clrb = 0, cfg2_setb = 0;
  223. debug("%s: mode=%d\n", __func__, mode);
  224. if (mode & SPI_CPOL)
  225. cfg2_setb |= SPI_CFG2_CPOL;
  226. else
  227. cfg2_clrb |= SPI_CFG2_CPOL;
  228. if (mode & SPI_CPHA)
  229. cfg2_setb |= SPI_CFG2_CPHA;
  230. else
  231. cfg2_clrb |= SPI_CFG2_CPHA;
  232. if (mode & SPI_LSB_FIRST)
  233. cfg2_setb |= SPI_CFG2_LSBFRST;
  234. else
  235. cfg2_clrb |= SPI_CFG2_LSBFRST;
  236. if (cfg2_clrb || cfg2_setb)
  237. clrsetbits_le32(priv->base + STM32_SPI_CFG2,
  238. cfg2_clrb, cfg2_setb);
  239. if (mode & SPI_CS_HIGH)
  240. priv->cs_high = true;
  241. else
  242. priv->cs_high = false;
  243. return 0;
  244. }
  245. static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
  246. {
  247. struct stm32_spi_priv *priv = dev_get_priv(dev);
  248. u32 fthlv, half_fifo;
  249. /* data packet should not exceed 1/2 of fifo space */
  250. half_fifo = (priv->fifo_size / 2);
  251. /* data_packet should not exceed transfer length */
  252. fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
  253. /* align packet size with data registers access */
  254. fthlv -= (fthlv % 4);
  255. if (!fthlv)
  256. fthlv = 1;
  257. clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
  258. (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
  259. return 0;
  260. }
  261. static int stm32_spi_set_speed(struct udevice *bus, uint hz)
  262. {
  263. struct stm32_spi_priv *priv = dev_get_priv(bus);
  264. u32 mbrdiv;
  265. long div;
  266. debug("%s: hz=%d\n", __func__, hz);
  267. if (priv->cur_hz == hz)
  268. return 0;
  269. div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
  270. if (div < STM32_MBR_DIV_MIN ||
  271. div > STM32_MBR_DIV_MAX)
  272. return -EINVAL;
  273. /* Determine the first power of 2 greater than or equal to div */
  274. if (div & (div - 1))
  275. mbrdiv = fls(div);
  276. else
  277. mbrdiv = fls(div) - 1;
  278. if (!mbrdiv)
  279. return -EINVAL;
  280. clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
  281. (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
  282. priv->cur_hz = hz;
  283. return 0;
  284. }
  285. static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
  286. const void *dout, void *din, unsigned long flags)
  287. {
  288. struct udevice *bus = dev_get_parent(slave);
  289. struct dm_spi_slave_platdata *slave_plat;
  290. struct stm32_spi_priv *priv = dev_get_priv(bus);
  291. u32 sr;
  292. u32 ifcr = 0;
  293. u32 xferlen;
  294. u32 mode;
  295. int xfer_status = 0;
  296. xferlen = bitlen / 8;
  297. if (xferlen <= SPI_CR2_TSIZE)
  298. writel(xferlen, priv->base + STM32_SPI_CR2);
  299. else
  300. return -EMSGSIZE;
  301. priv->tx_buf = dout;
  302. priv->rx_buf = din;
  303. priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
  304. priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
  305. mode = SPI_FULL_DUPLEX;
  306. if (!priv->tx_buf)
  307. mode = SPI_SIMPLEX_RX;
  308. else if (!priv->rx_buf)
  309. mode = SPI_SIMPLEX_TX;
  310. if (priv->cur_xferlen != xferlen || priv->cur_mode != mode) {
  311. priv->cur_mode = mode;
  312. priv->cur_xferlen = xferlen;
  313. /* Disable the SPI hardware to unlock CFG1/CFG2 registers */
  314. stm32_spi_disable(priv);
  315. clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
  316. mode << SPI_CFG2_COMM_SHIFT);
  317. stm32_spi_set_fthlv(bus, xferlen);
  318. /* Enable the SPI hardware */
  319. stm32_spi_enable(priv);
  320. }
  321. debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
  322. priv->tx_len, priv->rx_len);
  323. slave_plat = dev_get_parent_platdata(slave);
  324. if (flags & SPI_XFER_BEGIN)
  325. stm32_spi_set_cs(bus, slave_plat->cs, false);
  326. /* Be sure to have data in fifo before starting data transfer */
  327. if (priv->tx_buf)
  328. stm32_spi_write_txfifo(priv);
  329. setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
  330. while (1) {
  331. sr = readl(priv->base + STM32_SPI_SR);
  332. if (sr & SPI_SR_OVR) {
  333. dev_err(bus, "Overrun: RX data lost\n");
  334. xfer_status = -EIO;
  335. break;
  336. }
  337. if (sr & SPI_SR_SUSP) {
  338. dev_warn(bus, "System too slow is limiting data throughput\n");
  339. if (priv->rx_buf && priv->rx_len > 0)
  340. stm32_spi_read_rxfifo(priv);
  341. ifcr |= SPI_SR_SUSP;
  342. }
  343. if (sr & SPI_SR_TXTF)
  344. ifcr |= SPI_SR_TXTF;
  345. if (sr & SPI_SR_TXP)
  346. if (priv->tx_buf && priv->tx_len > 0)
  347. stm32_spi_write_txfifo(priv);
  348. if (sr & SPI_SR_RXP)
  349. if (priv->rx_buf && priv->rx_len > 0)
  350. stm32_spi_read_rxfifo(priv);
  351. if (sr & SPI_SR_EOT) {
  352. if (priv->rx_buf && priv->rx_len > 0)
  353. stm32_spi_read_rxfifo(priv);
  354. break;
  355. }
  356. writel(ifcr, priv->base + STM32_SPI_IFCR);
  357. }
  358. /* clear status flags */
  359. setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
  360. stm32_spi_stopxfer(bus);
  361. if (flags & SPI_XFER_END)
  362. stm32_spi_set_cs(bus, slave_plat->cs, true);
  363. return xfer_status;
  364. }
  365. static int stm32_spi_get_fifo_size(struct udevice *dev)
  366. {
  367. struct stm32_spi_priv *priv = dev_get_priv(dev);
  368. u32 count = 0;
  369. stm32_spi_enable(priv);
  370. while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
  371. writeb(++count, priv->base + STM32_SPI_TXDR);
  372. stm32_spi_disable(priv);
  373. debug("%s %d x 8-bit fifo size\n", __func__, count);
  374. return count;
  375. }
  376. static int stm32_spi_probe(struct udevice *dev)
  377. {
  378. struct stm32_spi_priv *priv = dev_get_priv(dev);
  379. unsigned long clk_rate;
  380. int ret;
  381. unsigned int i;
  382. priv->base = dev_remap_addr(dev);
  383. if (!priv->base)
  384. return -EINVAL;
  385. /* enable clock */
  386. ret = clk_get_by_index(dev, 0, &priv->clk);
  387. if (ret < 0)
  388. return ret;
  389. ret = clk_enable(&priv->clk);
  390. if (ret < 0)
  391. return ret;
  392. clk_rate = clk_get_rate(&priv->clk);
  393. if (!clk_rate) {
  394. ret = -EINVAL;
  395. goto clk_err;
  396. }
  397. priv->bus_clk_rate = clk_rate;
  398. /* perform reset */
  399. ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
  400. if (ret < 0)
  401. goto clk_err;
  402. reset_assert(&priv->rst_ctl);
  403. udelay(2);
  404. reset_deassert(&priv->rst_ctl);
  405. ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
  406. ARRAY_SIZE(priv->cs_gpios), 0);
  407. if (ret < 0) {
  408. pr_err("Can't get %s cs gpios: %d", dev->name, ret);
  409. goto reset_err;
  410. }
  411. priv->fifo_size = stm32_spi_get_fifo_size(dev);
  412. priv->cur_mode = SPI_FULL_DUPLEX;
  413. priv->cur_xferlen = 0;
  414. priv->cur_bpw = SPI_DEFAULT_WORDLEN;
  415. clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
  416. priv->cur_bpw - 1);
  417. for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
  418. if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
  419. continue;
  420. dm_gpio_set_dir_flags(&priv->cs_gpios[i],
  421. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  422. }
  423. /* Ensure I2SMOD bit is kept cleared */
  424. clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
  425. /*
  426. * - SS input value high
  427. * - transmitter half duplex direction
  428. * - automatic communication suspend when RX-Fifo is full
  429. */
  430. setbits_le32(priv->base + STM32_SPI_CR1,
  431. SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
  432. /*
  433. * - Set the master mode (default Motorola mode)
  434. * - Consider 1 master/n slaves configuration and
  435. * SS input value is determined by the SSI bit
  436. * - keep control of all associated GPIOs
  437. */
  438. setbits_le32(priv->base + STM32_SPI_CFG2,
  439. SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
  440. return 0;
  441. reset_err:
  442. reset_free(&priv->rst_ctl);
  443. clk_err:
  444. clk_disable(&priv->clk);
  445. clk_free(&priv->clk);
  446. return ret;
  447. };
  448. static int stm32_spi_remove(struct udevice *dev)
  449. {
  450. struct stm32_spi_priv *priv = dev_get_priv(dev);
  451. int ret;
  452. stm32_spi_stopxfer(dev);
  453. stm32_spi_disable(priv);
  454. ret = reset_assert(&priv->rst_ctl);
  455. if (ret < 0)
  456. return ret;
  457. reset_free(&priv->rst_ctl);
  458. ret = clk_disable(&priv->clk);
  459. if (ret < 0)
  460. return ret;
  461. clk_free(&priv->clk);
  462. return ret;
  463. };
  464. static const struct dm_spi_ops stm32_spi_ops = {
  465. .claim_bus = stm32_spi_claim_bus,
  466. .release_bus = stm32_spi_release_bus,
  467. .set_mode = stm32_spi_set_mode,
  468. .set_speed = stm32_spi_set_speed,
  469. .xfer = stm32_spi_xfer,
  470. };
  471. static const struct udevice_id stm32_spi_ids[] = {
  472. { .compatible = "st,stm32h7-spi", },
  473. { }
  474. };
  475. U_BOOT_DRIVER(stm32_spi) = {
  476. .name = "stm32_spi",
  477. .id = UCLASS_SPI,
  478. .of_match = stm32_spi_ids,
  479. .ops = &stm32_spi_ops,
  480. .priv_auto_alloc_size = sizeof(struct stm32_spi_priv),
  481. .probe = stm32_spi_probe,
  482. .remove = stm32_spi_remove,
  483. };