spi-sunxi.c 15 KB

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  1. /*
  2. * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V.
  3. * S.J.R. van Schaik <stephan@whiteboxsystems.nl>
  4. * M.B.W. Wajer <merlijn@whiteboxsystems.nl>
  5. *
  6. * (C) Copyright 2017 Olimex Ltd..
  7. * Stefan Mavrodiev <stefan@olimex.com>
  8. *
  9. * Based on linux spi driver. Original copyright follows:
  10. * linux/drivers/spi/spi-sun4i.c
  11. *
  12. * Copyright (C) 2012 - 2014 Allwinner Tech
  13. * Pan Nan <pannan@allwinnertech.com>
  14. *
  15. * Copyright (C) 2014 Maxime Ripard
  16. * Maxime Ripard <maxime.ripard@free-electrons.com>
  17. *
  18. * SPDX-License-Identifier: GPL-2.0+
  19. */
  20. #include <common.h>
  21. #include <clk.h>
  22. #include <dm.h>
  23. #include <log.h>
  24. #include <spi.h>
  25. #include <errno.h>
  26. #include <fdt_support.h>
  27. #include <reset.h>
  28. #include <wait_bit.h>
  29. #include <dm/device_compat.h>
  30. #include <linux/bitops.h>
  31. #include <asm/bitops.h>
  32. #include <asm/gpio.h>
  33. #include <asm/io.h>
  34. #include <linux/iopoll.h>
  35. DECLARE_GLOBAL_DATA_PTR;
  36. /* sun4i spi registers */
  37. #define SUN4I_RXDATA_REG 0x00
  38. #define SUN4I_TXDATA_REG 0x04
  39. #define SUN4I_CTL_REG 0x08
  40. #define SUN4I_CLK_CTL_REG 0x1c
  41. #define SUN4I_BURST_CNT_REG 0x20
  42. #define SUN4I_XMIT_CNT_REG 0x24
  43. #define SUN4I_FIFO_STA_REG 0x28
  44. /* sun6i spi registers */
  45. #define SUN6I_GBL_CTL_REG 0x04
  46. #define SUN6I_TFR_CTL_REG 0x08
  47. #define SUN6I_FIFO_CTL_REG 0x18
  48. #define SUN6I_FIFO_STA_REG 0x1c
  49. #define SUN6I_CLK_CTL_REG 0x24
  50. #define SUN6I_BURST_CNT_REG 0x30
  51. #define SUN6I_XMIT_CNT_REG 0x34
  52. #define SUN6I_BURST_CTL_REG 0x38
  53. #define SUN6I_TXDATA_REG 0x200
  54. #define SUN6I_RXDATA_REG 0x300
  55. /* sun spi bits */
  56. #define SUN4I_CTL_ENABLE BIT(0)
  57. #define SUN4I_CTL_MASTER BIT(1)
  58. #define SUN4I_CLK_CTL_CDR2_MASK 0xff
  59. #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
  60. #define SUN4I_CLK_CTL_CDR1_MASK 0xf
  61. #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
  62. #define SUN4I_CLK_CTL_DRS BIT(12)
  63. #define SUN4I_MAX_XFER_SIZE 0xffffff
  64. #define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
  65. #define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
  66. #define SUN4I_FIFO_STA_RF_CNT_BITS 0
  67. #define SUN4I_SPI_MAX_RATE 24000000
  68. #define SUN4I_SPI_MIN_RATE 3000
  69. #define SUN4I_SPI_DEFAULT_RATE 1000000
  70. #define SUN4I_SPI_TIMEOUT_US 1000000
  71. #define SPI_REG(priv, reg) ((priv)->base + \
  72. (priv)->variant->regs[reg])
  73. #define SPI_BIT(priv, bit) ((priv)->variant->bits[bit])
  74. #define SPI_CS(priv, cs) (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \
  75. SPI_BIT(priv, SPI_TCR_CS_MASK))
  76. /* sun spi register set */
  77. enum sun4i_spi_regs {
  78. SPI_GCR,
  79. SPI_TCR,
  80. SPI_FCR,
  81. SPI_FSR,
  82. SPI_CCR,
  83. SPI_BC,
  84. SPI_TC,
  85. SPI_BCTL,
  86. SPI_TXD,
  87. SPI_RXD,
  88. };
  89. /* sun spi register bits */
  90. enum sun4i_spi_bits {
  91. SPI_GCR_TP,
  92. SPI_GCR_SRST,
  93. SPI_TCR_CPHA,
  94. SPI_TCR_CPOL,
  95. SPI_TCR_CS_ACTIVE_LOW,
  96. SPI_TCR_CS_SEL,
  97. SPI_TCR_CS_MASK,
  98. SPI_TCR_XCH,
  99. SPI_TCR_CS_MANUAL,
  100. SPI_TCR_CS_LEVEL,
  101. SPI_FCR_TF_RST,
  102. SPI_FCR_RF_RST,
  103. SPI_FSR_RF_CNT_MASK,
  104. };
  105. struct sun4i_spi_variant {
  106. const unsigned long *regs;
  107. const u32 *bits;
  108. u32 fifo_depth;
  109. bool has_soft_reset;
  110. bool has_burst_ctl;
  111. };
  112. struct sun4i_spi_platdata {
  113. struct sun4i_spi_variant *variant;
  114. u32 base;
  115. u32 max_hz;
  116. };
  117. struct sun4i_spi_priv {
  118. struct sun4i_spi_variant *variant;
  119. struct clk clk_ahb, clk_mod;
  120. struct reset_ctl reset;
  121. u32 base;
  122. u32 freq;
  123. u32 mode;
  124. const u8 *tx_buf;
  125. u8 *rx_buf;
  126. };
  127. static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
  128. {
  129. u8 byte;
  130. while (len--) {
  131. byte = readb(SPI_REG(priv, SPI_RXD));
  132. if (priv->rx_buf)
  133. *priv->rx_buf++ = byte;
  134. }
  135. }
  136. static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len)
  137. {
  138. u8 byte;
  139. while (len--) {
  140. byte = priv->tx_buf ? *priv->tx_buf++ : 0;
  141. writeb(byte, SPI_REG(priv, SPI_TXD));
  142. }
  143. }
  144. static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
  145. {
  146. struct sun4i_spi_priv *priv = dev_get_priv(bus);
  147. u32 reg;
  148. reg = readl(SPI_REG(priv, SPI_TCR));
  149. reg &= ~SPI_BIT(priv, SPI_TCR_CS_MASK);
  150. reg |= SPI_CS(priv, cs);
  151. if (enable)
  152. reg &= ~SPI_BIT(priv, SPI_TCR_CS_LEVEL);
  153. else
  154. reg |= SPI_BIT(priv, SPI_TCR_CS_LEVEL);
  155. writel(reg, SPI_REG(priv, SPI_TCR));
  156. }
  157. static int sun4i_spi_parse_pins(struct udevice *dev)
  158. {
  159. const void *fdt = gd->fdt_blob;
  160. const char *pin_name;
  161. const fdt32_t *list;
  162. u32 phandle;
  163. int drive, pull = 0, pin, i;
  164. int offset;
  165. int size;
  166. list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size);
  167. if (!list) {
  168. printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n");
  169. return -EINVAL;
  170. }
  171. while (size) {
  172. phandle = fdt32_to_cpu(*list++);
  173. size -= sizeof(*list);
  174. offset = fdt_node_offset_by_phandle(fdt, phandle);
  175. if (offset < 0)
  176. return offset;
  177. drive = fdt_getprop_u32_default_node(fdt, offset, 0,
  178. "drive-strength", 0);
  179. if (drive) {
  180. if (drive <= 10)
  181. drive = 0;
  182. else if (drive <= 20)
  183. drive = 1;
  184. else if (drive <= 30)
  185. drive = 2;
  186. else
  187. drive = 3;
  188. } else {
  189. drive = fdt_getprop_u32_default_node(fdt, offset, 0,
  190. "allwinner,drive",
  191. 0);
  192. drive = min(drive, 3);
  193. }
  194. if (fdt_get_property(fdt, offset, "bias-disable", NULL))
  195. pull = 0;
  196. else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL))
  197. pull = 1;
  198. else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL))
  199. pull = 2;
  200. else
  201. pull = fdt_getprop_u32_default_node(fdt, offset, 0,
  202. "allwinner,pull",
  203. 0);
  204. pull = min(pull, 2);
  205. for (i = 0; ; i++) {
  206. pin_name = fdt_stringlist_get(fdt, offset,
  207. "pins", i, NULL);
  208. if (!pin_name) {
  209. pin_name = fdt_stringlist_get(fdt, offset,
  210. "allwinner,pins",
  211. i, NULL);
  212. if (!pin_name)
  213. break;
  214. }
  215. pin = name_to_gpio(pin_name);
  216. if (pin < 0)
  217. break;
  218. if (IS_ENABLED(CONFIG_MACH_SUN50I))
  219. sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0);
  220. else
  221. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0);
  222. sunxi_gpio_set_drv(pin, drive);
  223. sunxi_gpio_set_pull(pin, pull);
  224. }
  225. }
  226. return 0;
  227. }
  228. static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable)
  229. {
  230. struct sun4i_spi_priv *priv = dev_get_priv(dev);
  231. int ret;
  232. if (!enable) {
  233. clk_disable(&priv->clk_ahb);
  234. clk_disable(&priv->clk_mod);
  235. if (reset_valid(&priv->reset))
  236. reset_assert(&priv->reset);
  237. return 0;
  238. }
  239. ret = clk_enable(&priv->clk_ahb);
  240. if (ret) {
  241. dev_err(dev, "failed to enable ahb clock (ret=%d)\n", ret);
  242. return ret;
  243. }
  244. ret = clk_enable(&priv->clk_mod);
  245. if (ret) {
  246. dev_err(dev, "failed to enable mod clock (ret=%d)\n", ret);
  247. goto err_ahb;
  248. }
  249. if (reset_valid(&priv->reset)) {
  250. ret = reset_deassert(&priv->reset);
  251. if (ret) {
  252. dev_err(dev, "failed to deassert reset\n");
  253. goto err_mod;
  254. }
  255. }
  256. return 0;
  257. err_mod:
  258. clk_disable(&priv->clk_mod);
  259. err_ahb:
  260. clk_disable(&priv->clk_ahb);
  261. return ret;
  262. }
  263. static int sun4i_spi_claim_bus(struct udevice *dev)
  264. {
  265. struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
  266. int ret;
  267. ret = sun4i_spi_set_clock(dev->parent, true);
  268. if (ret)
  269. return ret;
  270. setbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE |
  271. SUN4I_CTL_MASTER | SPI_BIT(priv, SPI_GCR_TP));
  272. if (priv->variant->has_soft_reset)
  273. setbits_le32(SPI_REG(priv, SPI_GCR),
  274. SPI_BIT(priv, SPI_GCR_SRST));
  275. setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
  276. SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
  277. return 0;
  278. }
  279. static int sun4i_spi_release_bus(struct udevice *dev)
  280. {
  281. struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
  282. clrbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE);
  283. sun4i_spi_set_clock(dev->parent, false);
  284. return 0;
  285. }
  286. static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen,
  287. const void *dout, void *din, unsigned long flags)
  288. {
  289. struct udevice *bus = dev->parent;
  290. struct sun4i_spi_priv *priv = dev_get_priv(bus);
  291. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  292. u32 len = bitlen / 8;
  293. u32 rx_fifocnt;
  294. u8 nbytes;
  295. int ret;
  296. priv->tx_buf = dout;
  297. priv->rx_buf = din;
  298. if (bitlen % 8) {
  299. debug("%s: non byte-aligned SPI transfer.\n", __func__);
  300. return -ENAVAIL;
  301. }
  302. if (flags & SPI_XFER_BEGIN)
  303. sun4i_spi_set_cs(bus, slave_plat->cs, true);
  304. /* Reset FIFOs */
  305. setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) |
  306. SPI_BIT(priv, SPI_FCR_TF_RST));
  307. while (len) {
  308. /* Setup the transfer now... */
  309. nbytes = min(len, (priv->variant->fifo_depth - 1));
  310. /* Setup the counters */
  311. writel(SUN4I_BURST_CNT(nbytes), SPI_REG(priv, SPI_BC));
  312. writel(SUN4I_XMIT_CNT(nbytes), SPI_REG(priv, SPI_TC));
  313. if (priv->variant->has_burst_ctl)
  314. writel(SUN4I_BURST_CNT(nbytes),
  315. SPI_REG(priv, SPI_BCTL));
  316. /* Fill the TX FIFO */
  317. sun4i_spi_fill_fifo(priv, nbytes);
  318. /* Start the transfer */
  319. setbits_le32(SPI_REG(priv, SPI_TCR),
  320. SPI_BIT(priv, SPI_TCR_XCH));
  321. /* Wait till RX FIFO to be empty */
  322. ret = readl_poll_timeout(SPI_REG(priv, SPI_FSR),
  323. rx_fifocnt,
  324. (((rx_fifocnt &
  325. SPI_BIT(priv, SPI_FSR_RF_CNT_MASK)) >>
  326. SUN4I_FIFO_STA_RF_CNT_BITS) >= nbytes),
  327. SUN4I_SPI_TIMEOUT_US);
  328. if (ret < 0) {
  329. printf("ERROR: sun4i_spi: Timeout transferring data\n");
  330. sun4i_spi_set_cs(bus, slave_plat->cs, false);
  331. return ret;
  332. }
  333. /* Drain the RX FIFO */
  334. sun4i_spi_drain_fifo(priv, nbytes);
  335. len -= nbytes;
  336. }
  337. if (flags & SPI_XFER_END)
  338. sun4i_spi_set_cs(bus, slave_plat->cs, false);
  339. return 0;
  340. }
  341. static int sun4i_spi_set_speed(struct udevice *dev, uint speed)
  342. {
  343. struct sun4i_spi_platdata *plat = dev_get_platdata(dev);
  344. struct sun4i_spi_priv *priv = dev_get_priv(dev);
  345. unsigned int div;
  346. u32 reg;
  347. if (speed > plat->max_hz)
  348. speed = plat->max_hz;
  349. if (speed < SUN4I_SPI_MIN_RATE)
  350. speed = SUN4I_SPI_MIN_RATE;
  351. /*
  352. * Setup clock divider.
  353. *
  354. * We have two choices there. Either we can use the clock
  355. * divide rate 1, which is calculated thanks to this formula:
  356. * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1))
  357. * Or we can use CDR2, which is calculated with the formula:
  358. * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
  359. * Whether we use the former or the latter is set through the
  360. * DRS bit.
  361. *
  362. * First try CDR2, and if we can't reach the expected
  363. * frequency, fall back to CDR1.
  364. */
  365. div = SUN4I_SPI_MAX_RATE / (2 * speed);
  366. reg = readl(SPI_REG(priv, SPI_CCR));
  367. if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
  368. if (div > 0)
  369. div--;
  370. reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS);
  371. reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
  372. } else {
  373. div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed);
  374. reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS);
  375. reg |= SUN4I_CLK_CTL_CDR1(div);
  376. }
  377. priv->freq = speed;
  378. writel(reg, SPI_REG(priv, SPI_CCR));
  379. return 0;
  380. }
  381. static int sun4i_spi_set_mode(struct udevice *dev, uint mode)
  382. {
  383. struct sun4i_spi_priv *priv = dev_get_priv(dev);
  384. u32 reg;
  385. reg = readl(SPI_REG(priv, SPI_TCR));
  386. reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA));
  387. if (mode & SPI_CPOL)
  388. reg |= SPI_BIT(priv, SPI_TCR_CPOL);
  389. if (mode & SPI_CPHA)
  390. reg |= SPI_BIT(priv, SPI_TCR_CPHA);
  391. priv->mode = mode;
  392. writel(reg, SPI_REG(priv, SPI_TCR));
  393. return 0;
  394. }
  395. static const struct dm_spi_ops sun4i_spi_ops = {
  396. .claim_bus = sun4i_spi_claim_bus,
  397. .release_bus = sun4i_spi_release_bus,
  398. .xfer = sun4i_spi_xfer,
  399. .set_speed = sun4i_spi_set_speed,
  400. .set_mode = sun4i_spi_set_mode,
  401. };
  402. static int sun4i_spi_probe(struct udevice *bus)
  403. {
  404. struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
  405. struct sun4i_spi_priv *priv = dev_get_priv(bus);
  406. int ret;
  407. ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb);
  408. if (ret) {
  409. dev_err(bus, "failed to get ahb clock\n");
  410. return ret;
  411. }
  412. ret = clk_get_by_name(bus, "mod", &priv->clk_mod);
  413. if (ret) {
  414. dev_err(bus, "failed to get mod clock\n");
  415. return ret;
  416. }
  417. ret = reset_get_by_index(bus, 0, &priv->reset);
  418. if (ret && ret != -ENOENT) {
  419. dev_err(bus, "failed to get reset\n");
  420. return ret;
  421. }
  422. sun4i_spi_parse_pins(bus);
  423. priv->variant = plat->variant;
  424. priv->base = plat->base;
  425. priv->freq = plat->max_hz;
  426. return 0;
  427. }
  428. static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
  429. {
  430. struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
  431. int node = dev_of_offset(bus);
  432. plat->base = dev_read_addr(bus);
  433. plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
  434. plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
  435. "spi-max-frequency",
  436. SUN4I_SPI_DEFAULT_RATE);
  437. if (plat->max_hz > SUN4I_SPI_MAX_RATE)
  438. plat->max_hz = SUN4I_SPI_MAX_RATE;
  439. return 0;
  440. }
  441. static const unsigned long sun4i_spi_regs[] = {
  442. [SPI_GCR] = SUN4I_CTL_REG,
  443. [SPI_TCR] = SUN4I_CTL_REG,
  444. [SPI_FCR] = SUN4I_CTL_REG,
  445. [SPI_FSR] = SUN4I_FIFO_STA_REG,
  446. [SPI_CCR] = SUN4I_CLK_CTL_REG,
  447. [SPI_BC] = SUN4I_BURST_CNT_REG,
  448. [SPI_TC] = SUN4I_XMIT_CNT_REG,
  449. [SPI_TXD] = SUN4I_TXDATA_REG,
  450. [SPI_RXD] = SUN4I_RXDATA_REG,
  451. };
  452. static const u32 sun4i_spi_bits[] = {
  453. [SPI_GCR_TP] = BIT(18),
  454. [SPI_TCR_CPHA] = BIT(2),
  455. [SPI_TCR_CPOL] = BIT(3),
  456. [SPI_TCR_CS_ACTIVE_LOW] = BIT(4),
  457. [SPI_TCR_XCH] = BIT(10),
  458. [SPI_TCR_CS_SEL] = 12,
  459. [SPI_TCR_CS_MASK] = 0x3000,
  460. [SPI_TCR_CS_MANUAL] = BIT(16),
  461. [SPI_TCR_CS_LEVEL] = BIT(17),
  462. [SPI_FCR_TF_RST] = BIT(8),
  463. [SPI_FCR_RF_RST] = BIT(9),
  464. [SPI_FSR_RF_CNT_MASK] = GENMASK(6, 0),
  465. };
  466. static const unsigned long sun6i_spi_regs[] = {
  467. [SPI_GCR] = SUN6I_GBL_CTL_REG,
  468. [SPI_TCR] = SUN6I_TFR_CTL_REG,
  469. [SPI_FCR] = SUN6I_FIFO_CTL_REG,
  470. [SPI_FSR] = SUN6I_FIFO_STA_REG,
  471. [SPI_CCR] = SUN6I_CLK_CTL_REG,
  472. [SPI_BC] = SUN6I_BURST_CNT_REG,
  473. [SPI_TC] = SUN6I_XMIT_CNT_REG,
  474. [SPI_BCTL] = SUN6I_BURST_CTL_REG,
  475. [SPI_TXD] = SUN6I_TXDATA_REG,
  476. [SPI_RXD] = SUN6I_RXDATA_REG,
  477. };
  478. static const u32 sun6i_spi_bits[] = {
  479. [SPI_GCR_TP] = BIT(7),
  480. [SPI_GCR_SRST] = BIT(31),
  481. [SPI_TCR_CPHA] = BIT(0),
  482. [SPI_TCR_CPOL] = BIT(1),
  483. [SPI_TCR_CS_ACTIVE_LOW] = BIT(2),
  484. [SPI_TCR_CS_SEL] = 4,
  485. [SPI_TCR_CS_MASK] = 0x30,
  486. [SPI_TCR_CS_MANUAL] = BIT(6),
  487. [SPI_TCR_CS_LEVEL] = BIT(7),
  488. [SPI_TCR_XCH] = BIT(31),
  489. [SPI_FCR_RF_RST] = BIT(15),
  490. [SPI_FCR_TF_RST] = BIT(31),
  491. [SPI_FSR_RF_CNT_MASK] = GENMASK(7, 0),
  492. };
  493. static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
  494. .regs = sun4i_spi_regs,
  495. .bits = sun4i_spi_bits,
  496. .fifo_depth = 64,
  497. };
  498. static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
  499. .regs = sun6i_spi_regs,
  500. .bits = sun6i_spi_bits,
  501. .fifo_depth = 128,
  502. .has_soft_reset = true,
  503. .has_burst_ctl = true,
  504. };
  505. static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
  506. .regs = sun6i_spi_regs,
  507. .bits = sun6i_spi_bits,
  508. .fifo_depth = 64,
  509. .has_soft_reset = true,
  510. .has_burst_ctl = true,
  511. };
  512. static const struct udevice_id sun4i_spi_ids[] = {
  513. {
  514. .compatible = "allwinner,sun4i-a10-spi",
  515. .data = (ulong)&sun4i_a10_spi_variant,
  516. },
  517. {
  518. .compatible = "allwinner,sun6i-a31-spi",
  519. .data = (ulong)&sun6i_a31_spi_variant,
  520. },
  521. {
  522. .compatible = "allwinner,sun8i-h3-spi",
  523. .data = (ulong)&sun8i_h3_spi_variant,
  524. },
  525. { /* sentinel */ }
  526. };
  527. U_BOOT_DRIVER(sun4i_spi) = {
  528. .name = "sun4i_spi",
  529. .id = UCLASS_SPI,
  530. .of_match = sun4i_spi_ids,
  531. .ops = &sun4i_spi_ops,
  532. .ofdata_to_platdata = sun4i_spi_ofdata_to_platdata,
  533. .platdata_auto_alloc_size = sizeof(struct sun4i_spi_platdata),
  534. .priv_auto_alloc_size = sizeof(struct sun4i_spi_priv),
  535. .probe = sun4i_spi_probe,
  536. };