spi-qup.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for Qualcomm QUP SPI controller
  4. * FIFO and Block modes supported, no DMA
  5. * mode support
  6. *
  7. * Copyright (c) 2020 Sartura Ltd.
  8. *
  9. * Author: Robert Marko <robert.marko@sartura.hr>
  10. * Author: Luka Kovacic <luka.kovacic@sartura.hr>
  11. *
  12. * Based on stock U-boot and Linux drivers
  13. */
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <clk.h>
  17. #include <common.h>
  18. #include <dm.h>
  19. #include <errno.h>
  20. #include <linux/delay.h>
  21. #include <spi.h>
  22. #define QUP_CONFIG 0x0000
  23. #define QUP_STATE 0x0004
  24. #define QUP_IO_M_MODES 0x0008
  25. #define QUP_SW_RESET 0x000c
  26. #define QUP_OPERATIONAL 0x0018
  27. #define QUP_ERROR_FLAGS 0x001c
  28. #define QUP_ERROR_FLAGS_EN 0x0020
  29. #define QUP_OPERATIONAL_MASK 0x0028
  30. #define QUP_HW_VERSION 0x0030
  31. #define QUP_MX_OUTPUT_CNT 0x0100
  32. #define QUP_OUTPUT_FIFO 0x0110
  33. #define QUP_MX_WRITE_CNT 0x0150
  34. #define QUP_MX_INPUT_CNT 0x0200
  35. #define QUP_MX_READ_CNT 0x0208
  36. #define QUP_INPUT_FIFO 0x0218
  37. #define SPI_CONFIG 0x0300
  38. #define SPI_IO_CONTROL 0x0304
  39. #define SPI_ERROR_FLAGS 0x0308
  40. #define SPI_ERROR_FLAGS_EN 0x030c
  41. /* QUP_CONFIG fields */
  42. #define QUP_CONFIG_SPI_MODE BIT(8)
  43. #define QUP_CONFIG_CLOCK_AUTO_GATE BIT(13)
  44. #define QUP_CONFIG_NO_INPUT BIT(7)
  45. #define QUP_CONFIG_NO_OUTPUT BIT(6)
  46. #define QUP_CONFIG_N 0x001f
  47. /* QUP_STATE fields */
  48. #define QUP_STATE_VALID BIT(2)
  49. #define QUP_STATE_RESET 0
  50. #define QUP_STATE_RUN 1
  51. #define QUP_STATE_PAUSE 3
  52. #define QUP_STATE_MASK 3
  53. #define QUP_STATE_CLEAR 2
  54. /* QUP_IO_M_MODES fields */
  55. #define QUP_IO_M_PACK_EN BIT(15)
  56. #define QUP_IO_M_UNPACK_EN BIT(14)
  57. #define QUP_IO_M_INPUT_MODE_MASK_SHIFT 12
  58. #define QUP_IO_M_OUTPUT_MODE_MASK_SHIFT 10
  59. #define QUP_IO_M_INPUT_MODE_MASK (3 << QUP_IO_M_INPUT_MODE_MASK_SHIFT)
  60. #define QUP_IO_M_OUTPUT_MODE_MASK (3 << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT)
  61. #define QUP_IO_M_OUTPUT_BLOCK_SIZE(x) (((x) & (0x03 << 0)) >> 0)
  62. #define QUP_IO_M_OUTPUT_FIFO_SIZE(x) (((x) & (0x07 << 2)) >> 2)
  63. #define QUP_IO_M_INPUT_BLOCK_SIZE(x) (((x) & (0x03 << 5)) >> 5)
  64. #define QUP_IO_M_INPUT_FIFO_SIZE(x) (((x) & (0x07 << 7)) >> 7)
  65. #define QUP_IO_M_MODE_FIFO 0
  66. #define QUP_IO_M_MODE_BLOCK 1
  67. #define QUP_IO_M_MODE_DMOV 2
  68. #define QUP_IO_M_MODE_BAM 3
  69. /* QUP_OPERATIONAL fields */
  70. #define QUP_OP_IN_BLOCK_READ_REQ BIT(13)
  71. #define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12)
  72. #define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
  73. #define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
  74. #define QUP_OP_IN_SERVICE_FLAG BIT(9)
  75. #define QUP_OP_OUT_SERVICE_FLAG BIT(8)
  76. #define QUP_OP_IN_FIFO_FULL BIT(7)
  77. #define QUP_OP_OUT_FIFO_FULL BIT(6)
  78. #define QUP_OP_IN_FIFO_NOT_EMPTY BIT(5)
  79. #define QUP_OP_OUT_FIFO_NOT_EMPTY BIT(4)
  80. /* QUP_ERROR_FLAGS and QUP_ERROR_FLAGS_EN fields */
  81. #define QUP_ERROR_OUTPUT_OVER_RUN BIT(5)
  82. #define QUP_ERROR_INPUT_UNDER_RUN BIT(4)
  83. #define QUP_ERROR_OUTPUT_UNDER_RUN BIT(3)
  84. #define QUP_ERROR_INPUT_OVER_RUN BIT(2)
  85. /* SPI_CONFIG fields */
  86. #define SPI_CONFIG_HS_MODE BIT(10)
  87. #define SPI_CONFIG_INPUT_FIRST BIT(9)
  88. #define SPI_CONFIG_LOOPBACK BIT(8)
  89. /* SPI_IO_CONTROL fields */
  90. #define SPI_IO_C_FORCE_CS BIT(11)
  91. #define SPI_IO_C_CLK_IDLE_HIGH BIT(10)
  92. #define SPI_IO_C_MX_CS_MODE BIT(8)
  93. #define SPI_IO_C_CS_N_POLARITY_0 BIT(4)
  94. #define SPI_IO_C_CS_SELECT(x) (((x) & 3) << 2)
  95. #define SPI_IO_C_CS_SELECT_MASK 0x000c
  96. #define SPI_IO_C_TRISTATE_CS BIT(1)
  97. #define SPI_IO_C_NO_TRI_STATE BIT(0)
  98. /* SPI_ERROR_FLAGS and SPI_ERROR_FLAGS_EN fields */
  99. #define SPI_ERROR_CLK_OVER_RUN BIT(1)
  100. #define SPI_ERROR_CLK_UNDER_RUN BIT(0)
  101. #define SPI_NUM_CHIPSELECTS 4
  102. #define SPI_DELAY_THRESHOLD 1
  103. #define SPI_DELAY_RETRY 10
  104. #define SPI_RESET_STATE 0
  105. #define SPI_RUN_STATE 1
  106. #define SPI_CORE_RESET 0
  107. #define SPI_CORE_RUNNING 1
  108. #define DUMMY_DATA_VAL 0
  109. #define TIMEOUT_CNT 100
  110. #define QUP_STATE_VALID_BIT 2
  111. #define QUP_CONFIG_MINI_CORE_MSK (0x0F << 8)
  112. #define QUP_CONFIG_MINI_CORE_SPI BIT(8)
  113. #define QUP_CONF_INPUT_MSK BIT(7)
  114. #define QUP_CONF_INPUT_ENA (0 << 7)
  115. #define QUP_CONF_NO_INPUT BIT(7)
  116. #define QUP_CONF_OUTPUT_MSK BIT(6)
  117. #define QUP_CONF_OUTPUT_ENA (0 << 6)
  118. #define QUP_CONF_NO_OUTPUT BIT(6)
  119. #define QUP_STATE_RUN_STATE 0x1
  120. #define QUP_STATE_RESET_STATE 0x0
  121. #define QUP_STATE_PAUSE_STATE 0x3
  122. #define SPI_BIT_WORD_MSK 0x1F
  123. #define SPI_8_BIT_WORD 0x07
  124. #define LOOP_BACK_MSK BIT(8)
  125. #define NO_LOOP_BACK (0 << 8)
  126. #define SLAVE_OPERATION_MSK BIT(5)
  127. #define SLAVE_OPERATION (0 << 5)
  128. #define CLK_ALWAYS_ON (0 << 9)
  129. #define MX_CS_MODE BIT(8)
  130. #define CS_POLARITY_MASK BIT(4)
  131. #define NO_TRI_STATE BIT(0)
  132. #define FORCE_CS_MSK BIT(11)
  133. #define FORCE_CS_EN BIT(11)
  134. #define FORCE_CS_DIS (0 << 11)
  135. #define OUTPUT_BIT_SHIFT_MSK BIT(16)
  136. #define OUTPUT_BIT_SHIFT_EN BIT(16)
  137. #define INPUT_BLOCK_MODE_MSK (0x03 << 12)
  138. #define INPUT_BLOCK_MODE (0x01 << 12)
  139. #define OUTPUT_BLOCK_MODE_MSK (0x03 << 10)
  140. #define OUTPUT_BLOCK_MODE (0x01 << 10)
  141. #define INPUT_BAM_MODE (0x3 << 12)
  142. #define OUTPUT_BAM_MODE (0x3 << 10)
  143. #define PACK_EN (0x1 << 15)
  144. #define UNPACK_EN (0x1 << 14)
  145. #define PACK_EN_MSK (0x1 << 15)
  146. #define UNPACK_EN_MSK (0x1 << 14)
  147. #define OUTPUT_SERVICE_MSK (0x1 << 8)
  148. #define INPUT_SERVICE_MSK (0x1 << 9)
  149. #define OUTPUT_SERVICE_DIS (0x1 << 8)
  150. #define INPUT_SERVICE_DIS (0x1 << 9)
  151. #define BLSP0_SPI_DEASSERT_WAIT_REG 0x0310
  152. #define QUP_DATA_AVAILABLE_FOR_READ BIT(5)
  153. #define SPI_INPUT_BLOCK_SIZE 4
  154. #define SPI_OUTPUT_BLOCK_SIZE 4
  155. #define SPI_BITLEN_MSK 0x07
  156. #define MAX_COUNT_SIZE 0xffff
  157. struct qup_spi_priv {
  158. phys_addr_t base;
  159. struct clk clk;
  160. u32 num_cs;
  161. struct gpio_desc cs_gpios[SPI_NUM_CHIPSELECTS];
  162. bool cs_high;
  163. u32 core_state;
  164. };
  165. static int qup_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
  166. {
  167. struct qup_spi_priv *priv = dev_get_priv(dev);
  168. debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
  169. if (cs >= SPI_NUM_CHIPSELECTS)
  170. return -ENODEV;
  171. if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
  172. return -EINVAL;
  173. if (priv->cs_high)
  174. enable = !enable;
  175. return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
  176. }
  177. /*
  178. * Function to write data to OUTPUT FIFO
  179. */
  180. static void qup_spi_write_byte(struct udevice *dev, unsigned char data)
  181. {
  182. struct udevice *bus = dev_get_parent(dev);
  183. struct qup_spi_priv *priv = dev_get_priv(bus);
  184. /* Wait for space in the FIFO */
  185. while ((readl(priv->base + QUP_OPERATIONAL) & QUP_OP_OUT_FIFO_FULL))
  186. udelay(1);
  187. /* Write the byte of data */
  188. writel(data, priv->base + QUP_OUTPUT_FIFO);
  189. }
  190. /*
  191. * Function to read data from Input FIFO
  192. */
  193. static unsigned char qup_spi_read_byte(struct udevice *dev)
  194. {
  195. struct udevice *bus = dev_get_parent(dev);
  196. struct qup_spi_priv *priv = dev_get_priv(bus);
  197. /* Wait for Data in FIFO */
  198. while (!(readl(priv->base + QUP_OPERATIONAL) & QUP_DATA_AVAILABLE_FOR_READ)) {
  199. printf("Stuck at FIFO data wait\n");
  200. udelay(1);
  201. }
  202. /* Read a byte of data */
  203. return readl(priv->base + QUP_INPUT_FIFO) & 0xff;
  204. }
  205. /*
  206. * Function to check wheather Input or Output FIFO
  207. * has data to be serviced
  208. */
  209. static int qup_spi_check_fifo_status(struct udevice *dev, u32 reg_addr)
  210. {
  211. struct udevice *bus = dev_get_parent(dev);
  212. struct qup_spi_priv *priv = dev_get_priv(bus);
  213. unsigned int count = TIMEOUT_CNT;
  214. unsigned int status_flag;
  215. unsigned int val;
  216. do {
  217. val = readl(priv->base + reg_addr);
  218. count--;
  219. if (count == 0)
  220. return -ETIMEDOUT;
  221. status_flag = ((val & QUP_OP_OUT_SERVICE_FLAG) | (val & QUP_OP_IN_SERVICE_FLAG));
  222. } while (!status_flag);
  223. return 0;
  224. }
  225. /*
  226. * Function to configure Input and Output enable/disable
  227. */
  228. static void qup_spi_enable_io_config(struct udevice *dev, u32 write_cnt, u32 read_cnt)
  229. {
  230. struct udevice *bus = dev_get_parent(dev);
  231. struct qup_spi_priv *priv = dev_get_priv(bus);
  232. if (write_cnt) {
  233. clrsetbits_le32(priv->base + QUP_CONFIG,
  234. QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
  235. } else {
  236. clrsetbits_le32(priv->base + QUP_CONFIG,
  237. QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
  238. }
  239. if (read_cnt) {
  240. clrsetbits_le32(priv->base + QUP_CONFIG,
  241. QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
  242. } else {
  243. clrsetbits_le32(priv->base + QUP_CONFIG,
  244. QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
  245. }
  246. }
  247. static int check_bit_state(struct udevice *dev, u32 reg_addr, int bit_num, int val,
  248. int us_delay)
  249. {
  250. struct udevice *bus = dev_get_parent(dev);
  251. struct qup_spi_priv *priv = dev_get_priv(bus);
  252. unsigned int count = TIMEOUT_CNT;
  253. unsigned int bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
  254. while (bit_val != val) {
  255. count--;
  256. if (count == 0)
  257. return -ETIMEDOUT;
  258. udelay(us_delay);
  259. bit_val = ((readl(priv->base + reg_addr) >> bit_num) & 0x01);
  260. }
  261. return 0;
  262. }
  263. /*
  264. * Check whether QUPn State is valid
  265. */
  266. static int check_qup_state_valid(struct udevice *dev)
  267. {
  268. return check_bit_state(dev, QUP_STATE, QUP_STATE_VALID, 1, 1);
  269. }
  270. /*
  271. * Configure QUPn Core state
  272. */
  273. static int qup_spi_config_spi_state(struct udevice *dev, unsigned int state)
  274. {
  275. struct udevice *bus = dev_get_parent(dev);
  276. struct qup_spi_priv *priv = dev_get_priv(bus);
  277. u32 val;
  278. int ret;
  279. ret = check_qup_state_valid(dev);
  280. if (ret != 0)
  281. return ret;
  282. switch (state) {
  283. case SPI_RUN_STATE:
  284. /* Set the state to RUN */
  285. val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
  286. | QUP_STATE_RUN);
  287. writel(val, priv->base + QUP_STATE);
  288. ret = check_qup_state_valid(dev);
  289. if (ret != 0)
  290. return ret;
  291. priv->core_state = SPI_CORE_RUNNING;
  292. break;
  293. case SPI_RESET_STATE:
  294. /* Set the state to RESET */
  295. val = ((readl(priv->base + QUP_STATE) & ~QUP_STATE_MASK)
  296. | QUP_STATE_RESET);
  297. writel(val, priv->base + QUP_STATE);
  298. ret = check_qup_state_valid(dev);
  299. if (ret != 0)
  300. return ret;
  301. priv->core_state = SPI_CORE_RESET;
  302. break;
  303. default:
  304. printf("Unsupported QUP SPI state: %d\n", state);
  305. ret = -EINVAL;
  306. break;
  307. }
  308. return ret;
  309. }
  310. /*
  311. * Function to read bytes number of data from the Input FIFO
  312. */
  313. static int __qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
  314. {
  315. struct udevice *bus = dev_get_parent(dev);
  316. struct qup_spi_priv *priv = dev_get_priv(bus);
  317. u32 val;
  318. unsigned int i;
  319. unsigned int read_bytes = bytes;
  320. unsigned int fifo_count;
  321. int ret = 0;
  322. int state_config;
  323. /* Configure no of bytes to read */
  324. state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
  325. if (state_config)
  326. return state_config;
  327. /* Configure input and output enable */
  328. qup_spi_enable_io_config(dev, 0, read_bytes);
  329. writel(bytes, priv->base + QUP_MX_INPUT_CNT);
  330. state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
  331. if (state_config)
  332. return state_config;
  333. while (read_bytes) {
  334. ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
  335. if (ret != 0)
  336. goto out;
  337. val = readl(priv->base + QUP_OPERATIONAL);
  338. if (val & QUP_OP_IN_SERVICE_FLAG) {
  339. /*
  340. * acknowledge to hw that software will
  341. * read input data
  342. */
  343. val &= QUP_OP_IN_SERVICE_FLAG;
  344. writel(val, priv->base + QUP_OPERATIONAL);
  345. fifo_count = ((read_bytes > SPI_INPUT_BLOCK_SIZE) ?
  346. SPI_INPUT_BLOCK_SIZE : read_bytes);
  347. for (i = 0; i < fifo_count; i++) {
  348. *data_buffer = qup_spi_read_byte(dev);
  349. data_buffer++;
  350. read_bytes--;
  351. }
  352. }
  353. }
  354. out:
  355. /*
  356. * Put the SPI Core back in the Reset State
  357. * to end the transfer
  358. */
  359. (void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
  360. return ret;
  361. }
  362. static int qup_spi_blsp_spi_read(struct udevice *dev, u8 *data_buffer, unsigned int bytes)
  363. {
  364. int length, ret;
  365. while (bytes) {
  366. length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
  367. ret = __qup_spi_blsp_spi_read(dev, data_buffer, length);
  368. if (ret != 0)
  369. return ret;
  370. data_buffer += length;
  371. bytes -= length;
  372. }
  373. return 0;
  374. }
  375. /*
  376. * Function to write data to the Output FIFO
  377. */
  378. static int __qup_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
  379. {
  380. struct udevice *bus = dev_get_parent(dev);
  381. struct qup_spi_priv *priv = dev_get_priv(bus);
  382. u32 val;
  383. unsigned int i;
  384. unsigned int write_len = bytes;
  385. unsigned int read_len = bytes;
  386. unsigned int fifo_count;
  387. int ret = 0;
  388. int state_config;
  389. state_config = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
  390. if (state_config)
  391. return state_config;
  392. writel(bytes, priv->base + QUP_MX_OUTPUT_CNT);
  393. writel(bytes, priv->base + QUP_MX_INPUT_CNT);
  394. state_config = qup_spi_config_spi_state(dev, SPI_RUN_STATE);
  395. if (state_config)
  396. return state_config;
  397. /* Configure input and output enable */
  398. qup_spi_enable_io_config(dev, write_len, read_len);
  399. /*
  400. * read_len considered to ensure that we read the dummy data for the
  401. * write we performed. This is needed to ensure with WR-RD transaction
  402. * to get the actual data on the subsequent read cycle that happens
  403. */
  404. while (write_len || read_len) {
  405. ret = qup_spi_check_fifo_status(dev, QUP_OPERATIONAL);
  406. if (ret != 0)
  407. goto out;
  408. val = readl(priv->base + QUP_OPERATIONAL);
  409. if (val & QUP_OP_OUT_SERVICE_FLAG) {
  410. /*
  411. * acknowledge to hw that software will write
  412. * expected output data
  413. */
  414. val &= QUP_OP_OUT_SERVICE_FLAG;
  415. writel(val, priv->base + QUP_OPERATIONAL);
  416. if (write_len > SPI_OUTPUT_BLOCK_SIZE)
  417. fifo_count = SPI_OUTPUT_BLOCK_SIZE;
  418. else
  419. fifo_count = write_len;
  420. for (i = 0; i < fifo_count; i++) {
  421. /* Write actual data to output FIFO */
  422. qup_spi_write_byte(dev, *cmd_buffer);
  423. cmd_buffer++;
  424. write_len--;
  425. }
  426. }
  427. if (val & QUP_OP_IN_SERVICE_FLAG) {
  428. /*
  429. * acknowledge to hw that software
  430. * will read input data
  431. */
  432. val &= QUP_OP_IN_SERVICE_FLAG;
  433. writel(val, priv->base + QUP_OPERATIONAL);
  434. if (read_len > SPI_INPUT_BLOCK_SIZE)
  435. fifo_count = SPI_INPUT_BLOCK_SIZE;
  436. else
  437. fifo_count = read_len;
  438. for (i = 0; i < fifo_count; i++) {
  439. /* Read dummy data for the data written */
  440. (void)qup_spi_read_byte(dev);
  441. /* Decrement the write count after reading the
  442. * dummy data from the device. This is to make
  443. * sure we read dummy data before we write the
  444. * data to fifo
  445. */
  446. read_len--;
  447. }
  448. }
  449. }
  450. out:
  451. /*
  452. * Put the SPI Core back in the Reset State
  453. * to end the transfer
  454. */
  455. (void)qup_spi_config_spi_state(dev, SPI_RESET_STATE);
  456. return ret;
  457. }
  458. static int qup_spi_blsp_spi_write(struct udevice *dev, const u8 *cmd_buffer, unsigned int bytes)
  459. {
  460. int length, ret;
  461. while (bytes) {
  462. length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE;
  463. ret = __qup_blsp_spi_write(dev, cmd_buffer, length);
  464. if (ret != 0)
  465. return ret;
  466. cmd_buffer += length;
  467. bytes -= length;
  468. }
  469. return 0;
  470. }
  471. static int qup_spi_set_speed(struct udevice *dev, uint speed)
  472. {
  473. return 0;
  474. }
  475. static int qup_spi_set_mode(struct udevice *dev, uint mode)
  476. {
  477. struct qup_spi_priv *priv = dev_get_priv(dev);
  478. unsigned int clk_idle_state;
  479. unsigned int input_first_mode;
  480. u32 val;
  481. switch (mode) {
  482. case SPI_MODE_0:
  483. clk_idle_state = 0;
  484. input_first_mode = SPI_CONFIG_INPUT_FIRST;
  485. break;
  486. case SPI_MODE_1:
  487. clk_idle_state = 0;
  488. input_first_mode = 0;
  489. break;
  490. case SPI_MODE_2:
  491. clk_idle_state = 1;
  492. input_first_mode = SPI_CONFIG_INPUT_FIRST;
  493. break;
  494. case SPI_MODE_3:
  495. clk_idle_state = 1;
  496. input_first_mode = 0;
  497. break;
  498. default:
  499. printf("Unsupported spi mode: %d\n", mode);
  500. return -EINVAL;
  501. }
  502. if (mode & SPI_CS_HIGH)
  503. priv->cs_high = true;
  504. else
  505. priv->cs_high = false;
  506. val = readl(priv->base + SPI_CONFIG);
  507. val |= input_first_mode;
  508. writel(val, priv->base + SPI_CONFIG);
  509. val = readl(priv->base + SPI_IO_CONTROL);
  510. if (clk_idle_state)
  511. val |= SPI_IO_C_CLK_IDLE_HIGH;
  512. else
  513. val &= ~SPI_IO_C_CLK_IDLE_HIGH;
  514. writel(val, priv->base + SPI_IO_CONTROL);
  515. return 0;
  516. }
  517. static void qup_spi_reset(struct udevice *dev)
  518. {
  519. struct udevice *bus = dev_get_parent(dev);
  520. struct qup_spi_priv *priv = dev_get_priv(bus);
  521. /* Driver may not be probed yet */
  522. if (!priv)
  523. return;
  524. writel(0x1, priv->base + QUP_SW_RESET);
  525. udelay(5);
  526. }
  527. static int qup_spi_hw_init(struct udevice *dev)
  528. {
  529. struct udevice *bus = dev_get_parent(dev);
  530. struct qup_spi_priv *priv = dev_get_priv(bus);
  531. int ret;
  532. /* QUPn module configuration */
  533. qup_spi_reset(dev);
  534. /* Set the QUPn state */
  535. ret = qup_spi_config_spi_state(dev, SPI_RESET_STATE);
  536. if (ret)
  537. return ret;
  538. /*
  539. * Configure Mini core to SPI core with Input Output enabled,
  540. * SPI master, N = 8 bits
  541. */
  542. clrsetbits_le32(priv->base + QUP_CONFIG, (QUP_CONFIG_MINI_CORE_MSK |
  543. QUP_CONF_INPUT_MSK |
  544. QUP_CONF_OUTPUT_MSK |
  545. SPI_BIT_WORD_MSK),
  546. (QUP_CONFIG_MINI_CORE_SPI |
  547. QUP_CONF_INPUT_ENA |
  548. QUP_CONF_OUTPUT_ENA |
  549. SPI_8_BIT_WORD));
  550. /*
  551. * Configure Input first SPI protocol,
  552. * SPI master mode and no loopback
  553. */
  554. clrsetbits_le32(priv->base + SPI_CONFIG, (LOOP_BACK_MSK |
  555. SLAVE_OPERATION_MSK),
  556. (NO_LOOP_BACK |
  557. SLAVE_OPERATION));
  558. /*
  559. * Configure SPI IO Control Register
  560. * CLK_ALWAYS_ON = 0
  561. * MX_CS_MODE = 0
  562. * NO_TRI_STATE = 1
  563. */
  564. writel((CLK_ALWAYS_ON | NO_TRI_STATE), priv->base + SPI_IO_CONTROL);
  565. /*
  566. * Configure SPI IO Modes.
  567. * OUTPUT_BIT_SHIFT_EN = 1
  568. * INPUT_MODE = Block Mode
  569. * OUTPUT MODE = Block Mode
  570. */
  571. clrsetbits_le32(priv->base + QUP_IO_M_MODES, (OUTPUT_BIT_SHIFT_MSK |
  572. INPUT_BLOCK_MODE_MSK |
  573. OUTPUT_BLOCK_MODE_MSK),
  574. (OUTPUT_BIT_SHIFT_EN |
  575. INPUT_BLOCK_MODE |
  576. OUTPUT_BLOCK_MODE));
  577. /* Disable Error mask */
  578. writel(0, priv->base + SPI_ERROR_FLAGS_EN);
  579. writel(0, priv->base + QUP_ERROR_FLAGS_EN);
  580. writel(0, priv->base + BLSP0_SPI_DEASSERT_WAIT_REG);
  581. return ret;
  582. }
  583. static int qup_spi_claim_bus(struct udevice *dev)
  584. {
  585. int ret;
  586. ret = qup_spi_hw_init(dev);
  587. if (ret)
  588. return -EIO;
  589. return 0;
  590. }
  591. static int qup_spi_release_bus(struct udevice *dev)
  592. {
  593. /* Reset the SPI hardware */
  594. qup_spi_reset(dev);
  595. return 0;
  596. }
  597. static int qup_spi_xfer(struct udevice *dev, unsigned int bitlen,
  598. const void *dout, void *din, unsigned long flags)
  599. {
  600. struct udevice *bus = dev_get_parent(dev);
  601. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  602. unsigned int len;
  603. const u8 *txp = dout;
  604. u8 *rxp = din;
  605. int ret = 0;
  606. if (bitlen & SPI_BITLEN_MSK) {
  607. printf("Invalid bit length\n");
  608. return -EINVAL;
  609. }
  610. len = bitlen >> 3;
  611. if (flags & SPI_XFER_BEGIN) {
  612. ret = qup_spi_hw_init(dev);
  613. if (ret != 0)
  614. return ret;
  615. ret = qup_spi_set_cs(bus, slave_plat->cs, false);
  616. if (ret != 0)
  617. return ret;
  618. }
  619. if (dout != NULL) {
  620. ret = qup_spi_blsp_spi_write(dev, txp, len);
  621. if (ret != 0)
  622. return ret;
  623. }
  624. if (din != NULL) {
  625. ret = qup_spi_blsp_spi_read(dev, rxp, len);
  626. if (ret != 0)
  627. return ret;
  628. }
  629. if (flags & SPI_XFER_END) {
  630. ret = qup_spi_set_cs(bus, slave_plat->cs, true);
  631. if (ret != 0)
  632. return ret;
  633. }
  634. return ret;
  635. }
  636. static int qup_spi_probe(struct udevice *dev)
  637. {
  638. struct qup_spi_priv *priv = dev_get_priv(dev);
  639. int ret;
  640. priv->base = dev_read_addr(dev);
  641. if (priv->base == FDT_ADDR_T_NONE)
  642. return -EINVAL;
  643. ret = clk_get_by_index(dev, 0, &priv->clk);
  644. if (ret)
  645. return ret;
  646. ret = clk_enable(&priv->clk);
  647. if (ret < 0)
  648. return ret;
  649. priv->num_cs = dev_read_u32_default(dev, "num-cs", 1);
  650. ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
  651. priv->num_cs, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  652. if (ret < 0) {
  653. printf("Can't get %s cs gpios: %d\n", dev->name, ret);
  654. return -EINVAL;
  655. }
  656. return 0;
  657. }
  658. static const struct dm_spi_ops qup_spi_ops = {
  659. .claim_bus = qup_spi_claim_bus,
  660. .release_bus = qup_spi_release_bus,
  661. .xfer = qup_spi_xfer,
  662. .set_speed = qup_spi_set_speed,
  663. .set_mode = qup_spi_set_mode,
  664. /*
  665. * cs_info is not needed, since we require all chip selects to be
  666. * in the device tree explicitly
  667. */
  668. };
  669. static const struct udevice_id qup_spi_ids[] = {
  670. { .compatible = "qcom,spi-qup-v1.1.1", },
  671. { .compatible = "qcom,spi-qup-v2.1.1", },
  672. { .compatible = "qcom,spi-qup-v2.2.1", },
  673. { }
  674. };
  675. U_BOOT_DRIVER(spi_qup) = {
  676. .name = "spi_qup",
  677. .id = UCLASS_SPI,
  678. .of_match = qup_spi_ids,
  679. .ops = &qup_spi_ops,
  680. .priv_auto_alloc_size = sizeof(struct qup_spi_priv),
  681. .probe = qup_spi_probe,
  682. };