rk_spi.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * SPI driver for rockchip
  4. *
  5. * (C) Copyright 2015 Google, Inc
  6. *
  7. * (C) Copyright 2008-2013 Rockchip Electronics
  8. * Peter, Software Engineering, <superpeter.cai@gmail.com>.
  9. */
  10. #ifndef __RK_SPI_H
  11. #define __RK_SPI_H
  12. struct rockchip_spi {
  13. u32 ctrlr0;
  14. u32 ctrlr1;
  15. u32 enr;
  16. u32 ser;
  17. u32 baudr;
  18. u32 txftlr;
  19. u32 rxftlr;
  20. u32 txflr;
  21. u32 rxflr;
  22. u32 sr;
  23. u32 ipr;
  24. u32 imr;
  25. u32 isr;
  26. u32 risr;
  27. u32 icr;
  28. u32 dmacr;
  29. u32 dmatdlr;
  30. u32 dmardlr; /* 0x44 */
  31. u32 reserved[0xef];
  32. u32 txdr[0x100]; /* 0x400 */
  33. u32 rxdr[0x100]; /* 0x800 */
  34. };
  35. /* CTRLR0 */
  36. enum {
  37. DFS_SHIFT = 0, /* Data Frame Size */
  38. DFS_MASK = 3,
  39. DFS_4BIT = 0,
  40. DFS_8BIT,
  41. DFS_16BIT,
  42. DFS_RESV,
  43. CFS_SHIFT = 2, /* Control Frame Size */
  44. CFS_MASK = 0xf,
  45. SCPH_SHIFT = 6, /* Serial Clock Phase */
  46. SCPH_MASK = 1,
  47. SCPH_TOGMID = 0, /* SCLK toggles in middle of first data bit */
  48. SCPH_TOGSTA, /* SCLK toggles at start of first data bit */
  49. SCOL_SHIFT = 7, /* Serial Clock Polarity */
  50. SCOL_MASK = 1,
  51. SCOL_LOW = 0, /* Inactive state of serial clock is low */
  52. SCOL_HIGH, /* Inactive state of serial clock is high */
  53. CSM_SHIFT = 8, /* Chip Select Mode */
  54. CSM_MASK = 0x3,
  55. CSM_KEEP = 0, /* ss_n stays low after each frame */
  56. CSM_HALF, /* ss_n high for half sclk_out cycles */
  57. CSM_ONE, /* ss_n high for one sclk_out cycle */
  58. CSM_RESV,
  59. SSN_DELAY_SHIFT = 10, /* SSN to Sclk_out delay */
  60. SSN_DELAY_MASK = 1,
  61. SSN_DELAY_HALF = 0, /* 1/2 sclk_out cycle */
  62. SSN_DELAY_ONE = 1, /* 1 sclk_out cycle */
  63. SEM_SHIFT = 11, /* Serial Endian Mode */
  64. SEM_MASK = 1,
  65. SEM_LITTLE = 0, /* little endian */
  66. SEM_BIG, /* big endian */
  67. FBM_SHIFT = 12, /* First Bit Mode */
  68. FBM_MASK = 1,
  69. FBM_MSB = 0, /* first bit is MSB */
  70. FBM_LSB, /* first bit in LSB */
  71. HALF_WORD_TX_SHIFT = 13, /* Byte and Halfword Transform */
  72. HALF_WORD_MASK = 1,
  73. HALF_WORD_ON = 0, /* apb 16bit write/read, spi 8bit write/read */
  74. HALF_WORD_OFF, /* apb 8bit write/read, spi 8bit write/read */
  75. RXDSD_SHIFT = 14, /* Rxd Sample Delay, in cycles */
  76. RXDSD_MASK = 3,
  77. FRF_SHIFT = 16, /* Frame Format */
  78. FRF_MASK = 3,
  79. FRF_SPI = 0, /* Motorola SPI */
  80. FRF_SSP, /* Texas Instruments SSP*/
  81. FRF_MICROWIRE, /* National Semiconductors Microwire */
  82. FRF_RESV,
  83. TMOD_SHIFT = 18, /* Transfer Mode */
  84. TMOD_MASK = 3,
  85. TMOD_TR = 0, /* xmit & recv */
  86. TMOD_TO, /* xmit only */
  87. TMOD_RO, /* recv only */
  88. TMOD_RESV,
  89. OMOD_SHIFT = 20, /* Operation Mode */
  90. OMOD_MASK = 1,
  91. OMOD_MASTER = 0, /* Master Mode */
  92. OMOD_SLAVE, /* Slave Mode */
  93. };
  94. /* SR */
  95. enum {
  96. SR_MASK = 0x7f,
  97. SR_BUSY = 1 << 0,
  98. SR_TF_FULL = 1 << 1,
  99. SR_TF_EMPT = 1 << 2,
  100. SR_RF_EMPT = 1 << 3,
  101. SR_RF_FULL = 1 << 4,
  102. };
  103. #define ROCKCHIP_SPI_TIMEOUT_MS 1000
  104. /*
  105. * We limit the maximum bitrate to 50MBit/s (50MHz) due to an assumed
  106. * hardware limitation... the Linux kernel source has the following
  107. * comment:
  108. * "sclk_out: spi master internal logic in rk3x can support 50Mhz"
  109. */
  110. #define ROCKCHIP_SPI_MAX_RATE 50000000
  111. #endif /* __RK_SPI_H */