pl022_spi.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012
  4. * Armando Visconti, ST Microelectronics, armando.visconti@st.com.
  5. *
  6. * (C) Copyright 2018
  7. * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
  8. *
  9. * Driver for ARM PL022 SPI Controller.
  10. */
  11. #include <clk.h>
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <dm/platform_data/spi_pl022.h>
  15. #include <linux/io.h>
  16. #include <spi.h>
  17. #define SSP_CR0 0x000
  18. #define SSP_CR1 0x004
  19. #define SSP_DR 0x008
  20. #define SSP_SR 0x00C
  21. #define SSP_CPSR 0x010
  22. #define SSP_IMSC 0x014
  23. #define SSP_RIS 0x018
  24. #define SSP_MIS 0x01C
  25. #define SSP_ICR 0x020
  26. #define SSP_DMACR 0x024
  27. #define SSP_CSR 0x030 /* vendor extension */
  28. #define SSP_ITCR 0x080
  29. #define SSP_ITIP 0x084
  30. #define SSP_ITOP 0x088
  31. #define SSP_TDR 0x08C
  32. #define SSP_PID0 0xFE0
  33. #define SSP_PID1 0xFE4
  34. #define SSP_PID2 0xFE8
  35. #define SSP_PID3 0xFEC
  36. #define SSP_CID0 0xFF0
  37. #define SSP_CID1 0xFF4
  38. #define SSP_CID2 0xFF8
  39. #define SSP_CID3 0xFFC
  40. /* SSP Control Register 0 - SSP_CR0 */
  41. #define SSP_CR0_SPO (0x1 << 6)
  42. #define SSP_CR0_SPH (0x1 << 7)
  43. #define SSP_CR0_BIT_MODE(x) ((x) - 1)
  44. #define SSP_SCR_MIN (0x00)
  45. #define SSP_SCR_MAX (0xFF)
  46. #define SSP_SCR_SHFT 8
  47. #define DFLT_CLKRATE 2
  48. /* SSP Control Register 1 - SSP_CR1 */
  49. #define SSP_CR1_MASK_SSE (0x1 << 1)
  50. #define SSP_CPSR_MIN (0x02)
  51. #define SSP_CPSR_MAX (0xFE)
  52. #define DFLT_PRESCALE (0x40)
  53. /* SSP Status Register - SSP_SR */
  54. #define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */
  55. #define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */
  56. #define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */
  57. #define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */
  58. #define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */
  59. struct pl022_spi_slave {
  60. void *base;
  61. unsigned int freq;
  62. };
  63. /*
  64. * ARM PL022 exists in different 'flavors'.
  65. * This drivers currently support the standard variant (0x00041022), that has a
  66. * 16bit wide and 8 locations deep TX/RX FIFO.
  67. */
  68. static int pl022_is_supported(struct pl022_spi_slave *ps)
  69. {
  70. /* PL022 version is 0x00041022 */
  71. if ((readw(ps->base + SSP_PID0) == 0x22) &&
  72. (readw(ps->base + SSP_PID1) == 0x10) &&
  73. ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&
  74. (readw(ps->base + SSP_PID3) == 0x00))
  75. return 1;
  76. return 0;
  77. }
  78. static int pl022_spi_probe(struct udevice *bus)
  79. {
  80. struct pl022_spi_pdata *plat = dev_get_platdata(bus);
  81. struct pl022_spi_slave *ps = dev_get_priv(bus);
  82. ps->base = ioremap(plat->addr, plat->size);
  83. ps->freq = plat->freq;
  84. /* Check the PL022 version */
  85. if (!pl022_is_supported(ps))
  86. return -ENOTSUPP;
  87. /* 8 bits per word, high polarity and default clock rate */
  88. writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);
  89. writew(DFLT_PRESCALE, ps->base + SSP_CPSR);
  90. return 0;
  91. }
  92. static void flush(struct pl022_spi_slave *ps)
  93. {
  94. do {
  95. while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
  96. readw(ps->base + SSP_DR);
  97. } while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);
  98. }
  99. static int pl022_spi_claim_bus(struct udevice *dev)
  100. {
  101. struct udevice *bus = dev->parent;
  102. struct pl022_spi_slave *ps = dev_get_priv(bus);
  103. u16 reg;
  104. /* Enable the SPI hardware */
  105. reg = readw(ps->base + SSP_CR1);
  106. reg |= SSP_CR1_MASK_SSE;
  107. writew(reg, ps->base + SSP_CR1);
  108. flush(ps);
  109. return 0;
  110. }
  111. static int pl022_spi_release_bus(struct udevice *dev)
  112. {
  113. struct udevice *bus = dev->parent;
  114. struct pl022_spi_slave *ps = dev_get_priv(bus);
  115. u16 reg;
  116. flush(ps);
  117. /* Disable the SPI hardware */
  118. reg = readw(ps->base + SSP_CR1);
  119. reg &= ~SSP_CR1_MASK_SSE;
  120. writew(reg, ps->base + SSP_CR1);
  121. return 0;
  122. }
  123. static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
  124. const void *dout, void *din, unsigned long flags)
  125. {
  126. struct udevice *bus = dev->parent;
  127. struct pl022_spi_slave *ps = dev_get_priv(bus);
  128. u32 len_tx = 0, len_rx = 0, len;
  129. u32 ret = 0;
  130. const u8 *txp = dout;
  131. u8 *rxp = din, value;
  132. if (bitlen == 0)
  133. /* Finish any previously submitted transfers */
  134. return 0;
  135. /*
  136. * TODO: The controller can do non-multiple-of-8 bit
  137. * transfers, but this driver currently doesn't support it.
  138. *
  139. * It's also not clear how such transfers are supposed to be
  140. * represented as a stream of bytes...this is a limitation of
  141. * the current SPI interface.
  142. */
  143. if (bitlen % 8) {
  144. /* Errors always terminate an ongoing transfer */
  145. flags |= SPI_XFER_END;
  146. return -1;
  147. }
  148. len = bitlen / 8;
  149. while (len_tx < len) {
  150. if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {
  151. value = txp ? *txp++ : 0;
  152. writew(value, ps->base + SSP_DR);
  153. len_tx++;
  154. }
  155. if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
  156. value = readw(ps->base + SSP_DR);
  157. if (rxp)
  158. *rxp++ = value;
  159. len_rx++;
  160. }
  161. }
  162. while (len_rx < len_tx) {
  163. if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
  164. value = readw(ps->base + SSP_DR);
  165. if (rxp)
  166. *rxp++ = value;
  167. len_rx++;
  168. }
  169. }
  170. return ret;
  171. }
  172. static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
  173. {
  174. return rate / (cpsdvsr * (1 + scr));
  175. }
  176. static int pl022_spi_set_speed(struct udevice *bus, uint speed)
  177. {
  178. struct pl022_spi_slave *ps = dev_get_priv(bus);
  179. u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr,
  180. best_cpsr = cpsr;
  181. u32 min, max, best_freq = 0, tmp;
  182. u32 rate = ps->freq;
  183. bool found = false;
  184. max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);
  185. min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX);
  186. if (speed > max || speed < min) {
  187. pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",
  188. speed, min, max);
  189. return -EINVAL;
  190. }
  191. while (cpsr <= SSP_CPSR_MAX && !found) {
  192. while (scr <= SSP_SCR_MAX) {
  193. tmp = spi_rate(rate, cpsr, scr);
  194. if (abs(speed - tmp) < abs(speed - best_freq)) {
  195. best_freq = tmp;
  196. best_cpsr = cpsr;
  197. best_scr = scr;
  198. if (tmp == speed) {
  199. found = true;
  200. break;
  201. }
  202. }
  203. scr++;
  204. }
  205. cpsr += 2;
  206. scr = SSP_SCR_MIN;
  207. }
  208. writew(best_cpsr, ps->base + SSP_CPSR);
  209. cr0 = readw(ps->base + SSP_CR0);
  210. writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);
  211. return 0;
  212. }
  213. static int pl022_spi_set_mode(struct udevice *bus, uint mode)
  214. {
  215. struct pl022_spi_slave *ps = dev_get_priv(bus);
  216. u16 reg;
  217. reg = readw(ps->base + SSP_CR0);
  218. reg &= ~(SSP_CR0_SPH | SSP_CR0_SPO);
  219. if (mode & SPI_CPHA)
  220. reg |= SSP_CR0_SPH;
  221. if (mode & SPI_CPOL)
  222. reg |= SSP_CR0_SPO;
  223. writew(reg, ps->base + SSP_CR0);
  224. return 0;
  225. }
  226. static int pl022_cs_info(struct udevice *bus, uint cs,
  227. struct spi_cs_info *info)
  228. {
  229. return 0;
  230. }
  231. static const struct dm_spi_ops pl022_spi_ops = {
  232. .claim_bus = pl022_spi_claim_bus,
  233. .release_bus = pl022_spi_release_bus,
  234. .xfer = pl022_spi_xfer,
  235. .set_speed = pl022_spi_set_speed,
  236. .set_mode = pl022_spi_set_mode,
  237. .cs_info = pl022_cs_info,
  238. };
  239. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  240. static int pl022_spi_ofdata_to_platdata(struct udevice *bus)
  241. {
  242. struct pl022_spi_pdata *plat = bus->platdata;
  243. const void *fdt = gd->fdt_blob;
  244. int node = dev_of_offset(bus);
  245. struct clk clkdev;
  246. int ret;
  247. plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);
  248. ret = clk_get_by_index(bus, 0, &clkdev);
  249. if (ret)
  250. return ret;
  251. plat->freq = clk_get_rate(&clkdev);
  252. return 0;
  253. }
  254. static const struct udevice_id pl022_spi_ids[] = {
  255. { .compatible = "arm,pl022-spi" },
  256. { }
  257. };
  258. #endif
  259. U_BOOT_DRIVER(pl022_spi) = {
  260. .name = "pl022_spi",
  261. .id = UCLASS_SPI,
  262. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  263. .of_match = pl022_spi_ids,
  264. .ofdata_to_platdata = pl022_spi_ofdata_to_platdata,
  265. #endif
  266. .ops = &pl022_spi_ops,
  267. .platdata_auto_alloc_size = sizeof(struct pl022_spi_pdata),
  268. .priv_auto_alloc_size = sizeof(struct pl022_spi_slave),
  269. .probe = pl022_spi_probe,
  270. };