nxp_fspi.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NXP FlexSPI(FSPI) controller driver.
  4. *
  5. * Copyright (c) 2019 Michael Walle <michael@walle.cc>
  6. * Copyright (c) 2019 NXP
  7. *
  8. * This driver was originally ported from the linux kernel v5.4-rc3, which had
  9. * the following notes:
  10. *
  11. * FlexSPI is a flexsible SPI host controller which supports two SPI
  12. * channels and up to 4 external devices. Each channel supports
  13. * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional
  14. * data lines).
  15. *
  16. * FlexSPI controller is driven by the LUT(Look-up Table) registers
  17. * LUT registers are a look-up-table for sequences of instructions.
  18. * A valid sequence consists of four LUT registers.
  19. * Maximum 32 LUT sequences can be programmed simultaneously.
  20. *
  21. * LUTs are being created at run-time based on the commands passed
  22. * from the spi-mem framework, thus using single LUT index.
  23. *
  24. * Software triggered Flash read/write access by IP Bus.
  25. *
  26. * Memory mapped read access by AHB Bus.
  27. *
  28. * Based on SPI MEM interface and spi-fsl-qspi.c driver.
  29. *
  30. * Author:
  31. * Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
  32. * Boris Brezillon <bbrezillon@kernel.org>
  33. * Frieder Schrempf <frieder.schrempf@kontron.de>
  34. */
  35. #include <common.h>
  36. #include <clk.h>
  37. #include <dm.h>
  38. #include <dm/device_compat.h>
  39. #include <malloc.h>
  40. #include <spi.h>
  41. #include <spi-mem.h>
  42. #include <asm/io.h>
  43. #include <linux/bitops.h>
  44. #include <linux/kernel.h>
  45. #include <linux/sizes.h>
  46. #include <linux/iopoll.h>
  47. #include <linux/bug.h>
  48. #include <linux/err.h>
  49. /*
  50. * The driver only uses one single LUT entry, that is updated on
  51. * each call of exec_op(). Index 0 is preset at boot with a basic
  52. * read operation, so let's use the last entry (31).
  53. */
  54. #define SEQID_LUT 31
  55. /* Registers used by the driver */
  56. #define FSPI_MCR0 0x00
  57. #define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
  58. #define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
  59. #define FSPI_MCR0_LEARN_EN BIT(15)
  60. #define FSPI_MCR0_SCRFRUN_EN BIT(14)
  61. #define FSPI_MCR0_OCTCOMB_EN BIT(13)
  62. #define FSPI_MCR0_DOZE_EN BIT(12)
  63. #define FSPI_MCR0_HSEN BIT(11)
  64. #define FSPI_MCR0_SERCLKDIV BIT(8)
  65. #define FSPI_MCR0_ATDF_EN BIT(7)
  66. #define FSPI_MCR0_ARDF_EN BIT(6)
  67. #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
  68. #define FSPI_MCR0_END_CFG(x) ((x) << 2)
  69. #define FSPI_MCR0_MDIS BIT(1)
  70. #define FSPI_MCR0_SWRST BIT(0)
  71. #define FSPI_MCR1 0x04
  72. #define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
  73. #define FSPI_MCR1_AHB_TIMEOUT(x) (x)
  74. #define FSPI_MCR2 0x08
  75. #define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
  76. #define FSPI_MCR2_SAMEDEVICEEN BIT(15)
  77. #define FSPI_MCR2_CLRLRPHS BIT(14)
  78. #define FSPI_MCR2_ABRDATSZ BIT(8)
  79. #define FSPI_MCR2_ABRLEARN BIT(7)
  80. #define FSPI_MCR2_ABR_READ BIT(6)
  81. #define FSPI_MCR2_ABRWRITE BIT(5)
  82. #define FSPI_MCR2_ABRDUMMY BIT(4)
  83. #define FSPI_MCR2_ABR_MODE BIT(3)
  84. #define FSPI_MCR2_ABRCADDR BIT(2)
  85. #define FSPI_MCR2_ABRRADDR BIT(1)
  86. #define FSPI_MCR2_ABR_CMD BIT(0)
  87. #define FSPI_AHBCR 0x0c
  88. #define FSPI_AHBCR_RDADDROPT BIT(6)
  89. #define FSPI_AHBCR_PREF_EN BIT(5)
  90. #define FSPI_AHBCR_BUFF_EN BIT(4)
  91. #define FSPI_AHBCR_CACH_EN BIT(3)
  92. #define FSPI_AHBCR_CLRTXBUF BIT(2)
  93. #define FSPI_AHBCR_CLRRXBUF BIT(1)
  94. #define FSPI_AHBCR_PAR_EN BIT(0)
  95. #define FSPI_INTEN 0x10
  96. #define FSPI_INTEN_SCLKSBWR BIT(9)
  97. #define FSPI_INTEN_SCLKSBRD BIT(8)
  98. #define FSPI_INTEN_DATALRNFL BIT(7)
  99. #define FSPI_INTEN_IPTXWE BIT(6)
  100. #define FSPI_INTEN_IPRXWA BIT(5)
  101. #define FSPI_INTEN_AHBCMDERR BIT(4)
  102. #define FSPI_INTEN_IPCMDERR BIT(3)
  103. #define FSPI_INTEN_AHBCMDGE BIT(2)
  104. #define FSPI_INTEN_IPCMDGE BIT(1)
  105. #define FSPI_INTEN_IPCMDDONE BIT(0)
  106. #define FSPI_INTR 0x14
  107. #define FSPI_INTR_SCLKSBWR BIT(9)
  108. #define FSPI_INTR_SCLKSBRD BIT(8)
  109. #define FSPI_INTR_DATALRNFL BIT(7)
  110. #define FSPI_INTR_IPTXWE BIT(6)
  111. #define FSPI_INTR_IPRXWA BIT(5)
  112. #define FSPI_INTR_AHBCMDERR BIT(4)
  113. #define FSPI_INTR_IPCMDERR BIT(3)
  114. #define FSPI_INTR_AHBCMDGE BIT(2)
  115. #define FSPI_INTR_IPCMDGE BIT(1)
  116. #define FSPI_INTR_IPCMDDONE BIT(0)
  117. #define FSPI_LUTKEY 0x18
  118. #define FSPI_LUTKEY_VALUE 0x5AF05AF0
  119. #define FSPI_LCKCR 0x1C
  120. #define FSPI_LCKER_LOCK 0x1
  121. #define FSPI_LCKER_UNLOCK 0x2
  122. #define FSPI_BUFXCR_INVALID_MSTRID 0xE
  123. #define FSPI_AHBRX_BUF0CR0 0x20
  124. #define FSPI_AHBRX_BUF1CR0 0x24
  125. #define FSPI_AHBRX_BUF2CR0 0x28
  126. #define FSPI_AHBRX_BUF3CR0 0x2C
  127. #define FSPI_AHBRX_BUF4CR0 0x30
  128. #define FSPI_AHBRX_BUF5CR0 0x34
  129. #define FSPI_AHBRX_BUF6CR0 0x38
  130. #define FSPI_AHBRX_BUF7CR0 0x3C
  131. #define FSPI_AHBRXBUF0CR7_PREF BIT(31)
  132. #define FSPI_AHBRX_BUF0CR1 0x40
  133. #define FSPI_AHBRX_BUF1CR1 0x44
  134. #define FSPI_AHBRX_BUF2CR1 0x48
  135. #define FSPI_AHBRX_BUF3CR1 0x4C
  136. #define FSPI_AHBRX_BUF4CR1 0x50
  137. #define FSPI_AHBRX_BUF5CR1 0x54
  138. #define FSPI_AHBRX_BUF6CR1 0x58
  139. #define FSPI_AHBRX_BUF7CR1 0x5C
  140. #define FSPI_FLSHA1CR0 0x60
  141. #define FSPI_FLSHA2CR0 0x64
  142. #define FSPI_FLSHB1CR0 0x68
  143. #define FSPI_FLSHB2CR0 0x6C
  144. #define FSPI_FLSHXCR0_SZ_KB 10
  145. #define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
  146. #define FSPI_FLSHA1CR1 0x70
  147. #define FSPI_FLSHA2CR1 0x74
  148. #define FSPI_FLSHB1CR1 0x78
  149. #define FSPI_FLSHB2CR1 0x7C
  150. #define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
  151. #define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
  152. #define FSPI_FLSHXCR1_WA BIT(10)
  153. #define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
  154. #define FSPI_FLSHXCR1_TCSS(x) (x)
  155. #define FSPI_FLSHA1CR2 0x80
  156. #define FSPI_FLSHA2CR2 0x84
  157. #define FSPI_FLSHB1CR2 0x88
  158. #define FSPI_FLSHB2CR2 0x8C
  159. #define FSPI_FLSHXCR2_CLRINSP BIT(24)
  160. #define FSPI_FLSHXCR2_AWRWAIT BIT(16)
  161. #define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
  162. #define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
  163. #define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
  164. #define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
  165. #define FSPI_IPCR0 0xA0
  166. #define FSPI_IPCR1 0xA4
  167. #define FSPI_IPCR1_IPAREN BIT(31)
  168. #define FSPI_IPCR1_SEQNUM_SHIFT 24
  169. #define FSPI_IPCR1_SEQID_SHIFT 16
  170. #define FSPI_IPCR1_IDATSZ(x) (x)
  171. #define FSPI_IPCMD 0xB0
  172. #define FSPI_IPCMD_TRG BIT(0)
  173. #define FSPI_DLPR 0xB4
  174. #define FSPI_IPRXFCR 0xB8
  175. #define FSPI_IPRXFCR_CLR BIT(0)
  176. #define FSPI_IPRXFCR_DMA_EN BIT(1)
  177. #define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
  178. #define FSPI_IPTXFCR 0xBC
  179. #define FSPI_IPTXFCR_CLR BIT(0)
  180. #define FSPI_IPTXFCR_DMA_EN BIT(1)
  181. #define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
  182. #define FSPI_DLLACR 0xC0
  183. #define FSPI_DLLACR_OVRDEN BIT(8)
  184. #define FSPI_DLLBCR 0xC4
  185. #define FSPI_DLLBCR_OVRDEN BIT(8)
  186. #define FSPI_STS0 0xE0
  187. #define FSPI_STS0_DLPHB(x) ((x) << 8)
  188. #define FSPI_STS0_DLPHA(x) ((x) << 4)
  189. #define FSPI_STS0_CMD_SRC(x) ((x) << 2)
  190. #define FSPI_STS0_ARB_IDLE BIT(1)
  191. #define FSPI_STS0_SEQ_IDLE BIT(0)
  192. #define FSPI_STS1 0xE4
  193. #define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
  194. #define FSPI_STS1_IP_ERRID(x) ((x) << 16)
  195. #define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
  196. #define FSPI_STS1_AHB_ERRID(x) (x)
  197. #define FSPI_AHBSPNST 0xEC
  198. #define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
  199. #define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
  200. #define FSPI_AHBSPNST_ACTIVE BIT(0)
  201. #define FSPI_IPRXFSTS 0xF0
  202. #define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
  203. #define FSPI_IPRXFSTS_FILL(x) (x)
  204. #define FSPI_IPTXFSTS 0xF4
  205. #define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
  206. #define FSPI_IPTXFSTS_FILL(x) (x)
  207. #define FSPI_RFDR 0x100
  208. #define FSPI_TFDR 0x180
  209. #define FSPI_LUT_BASE 0x200
  210. #define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
  211. #define FSPI_LUT_REG(idx) \
  212. (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
  213. /* register map end */
  214. /* Instruction set for the LUT register. */
  215. #define LUT_STOP 0x00
  216. #define LUT_CMD 0x01
  217. #define LUT_ADDR 0x02
  218. #define LUT_CADDR_SDR 0x03
  219. #define LUT_MODE 0x04
  220. #define LUT_MODE2 0x05
  221. #define LUT_MODE4 0x06
  222. #define LUT_MODE8 0x07
  223. #define LUT_NXP_WRITE 0x08
  224. #define LUT_NXP_READ 0x09
  225. #define LUT_LEARN_SDR 0x0A
  226. #define LUT_DATSZ_SDR 0x0B
  227. #define LUT_DUMMY 0x0C
  228. #define LUT_DUMMY_RWDS_SDR 0x0D
  229. #define LUT_JMP_ON_CS 0x1F
  230. #define LUT_CMD_DDR 0x21
  231. #define LUT_ADDR_DDR 0x22
  232. #define LUT_CADDR_DDR 0x23
  233. #define LUT_MODE_DDR 0x24
  234. #define LUT_MODE2_DDR 0x25
  235. #define LUT_MODE4_DDR 0x26
  236. #define LUT_MODE8_DDR 0x27
  237. #define LUT_WRITE_DDR 0x28
  238. #define LUT_READ_DDR 0x29
  239. #define LUT_LEARN_DDR 0x2A
  240. #define LUT_DATSZ_DDR 0x2B
  241. #define LUT_DUMMY_DDR 0x2C
  242. #define LUT_DUMMY_RWDS_DDR 0x2D
  243. /*
  244. * Calculate number of required PAD bits for LUT register.
  245. *
  246. * The pad stands for the number of IO lines [0:7].
  247. * For example, the octal read needs eight IO lines,
  248. * so you should use LUT_PAD(8). This macro
  249. * returns 3 i.e. use eight (2^3) IP lines for read.
  250. */
  251. #define LUT_PAD(x) (fls(x) - 1)
  252. /*
  253. * Macro for constructing the LUT entries with the following
  254. * register layout:
  255. *
  256. * ---------------------------------------------------
  257. * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
  258. * ---------------------------------------------------
  259. */
  260. #define PAD_SHIFT 8
  261. #define INSTR_SHIFT 10
  262. #define OPRND_SHIFT 16
  263. /* Macros for constructing the LUT register. */
  264. #define LUT_DEF(idx, ins, pad, opr) \
  265. ((((ins) << INSTR_SHIFT) | ((pad) << PAD_SHIFT) | \
  266. (opr)) << (((idx) % 2) * OPRND_SHIFT))
  267. #define POLL_TOUT 5000
  268. #define NXP_FSPI_MAX_CHIPSELECT 4
  269. struct nxp_fspi_devtype_data {
  270. unsigned int rxfifo;
  271. unsigned int txfifo;
  272. unsigned int ahb_buf_size;
  273. unsigned int quirks;
  274. bool little_endian;
  275. };
  276. static const struct nxp_fspi_devtype_data lx2160a_data = {
  277. .rxfifo = SZ_512, /* (64 * 64 bits) */
  278. .txfifo = SZ_1K, /* (128 * 64 bits) */
  279. .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
  280. .quirks = 0,
  281. .little_endian = true, /* little-endian */
  282. };
  283. struct nxp_fspi {
  284. struct udevice *dev;
  285. void __iomem *iobase;
  286. void __iomem *ahb_addr;
  287. u32 memmap_phy;
  288. u32 memmap_phy_size;
  289. struct clk clk, clk_en;
  290. const struct nxp_fspi_devtype_data *devtype_data;
  291. };
  292. /*
  293. * R/W functions for big- or little-endian registers:
  294. * The FSPI controller's endianness is independent of
  295. * the CPU core's endianness. So far, although the CPU
  296. * core is little-endian the FSPI controller can use
  297. * big-endian or little-endian.
  298. */
  299. static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem *addr)
  300. {
  301. if (f->devtype_data->little_endian)
  302. out_le32(addr, val);
  303. else
  304. out_be32(addr, val);
  305. }
  306. static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr)
  307. {
  308. if (f->devtype_data->little_endian)
  309. return in_le32(addr);
  310. else
  311. return in_be32(addr);
  312. }
  313. static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width)
  314. {
  315. switch (width) {
  316. case 1:
  317. case 2:
  318. case 4:
  319. case 8:
  320. return 0;
  321. }
  322. return -ENOTSUPP;
  323. }
  324. static bool nxp_fspi_supports_op(struct spi_slave *slave,
  325. const struct spi_mem_op *op)
  326. {
  327. struct nxp_fspi *f;
  328. struct udevice *bus;
  329. int ret;
  330. bus = slave->dev->parent;
  331. f = dev_get_priv(bus);
  332. ret = nxp_fspi_check_buswidth(f, op->cmd.buswidth);
  333. if (op->addr.nbytes)
  334. ret |= nxp_fspi_check_buswidth(f, op->addr.buswidth);
  335. if (op->dummy.nbytes)
  336. ret |= nxp_fspi_check_buswidth(f, op->dummy.buswidth);
  337. if (op->data.nbytes)
  338. ret |= nxp_fspi_check_buswidth(f, op->data.buswidth);
  339. if (ret)
  340. return false;
  341. /*
  342. * The number of address bytes should be equal to or less than 4 bytes.
  343. */
  344. if (op->addr.nbytes > 4)
  345. return false;
  346. /*
  347. * If requested address value is greater than controller assigned
  348. * memory mapped space, return error as it didn't fit in the range
  349. * of assigned address space.
  350. */
  351. if (op->addr.val >= f->memmap_phy_size)
  352. return false;
  353. /* Max 64 dummy clock cycles supported */
  354. if (op->dummy.buswidth &&
  355. (op->dummy.nbytes * 8 / op->dummy.buswidth > 64))
  356. return false;
  357. /* Max data length, check controller limits and alignment */
  358. if (op->data.dir == SPI_MEM_DATA_IN &&
  359. (op->data.nbytes > f->devtype_data->ahb_buf_size ||
  360. (op->data.nbytes > f->devtype_data->rxfifo - 4 &&
  361. !IS_ALIGNED(op->data.nbytes, 8))))
  362. return false;
  363. if (op->data.dir == SPI_MEM_DATA_OUT &&
  364. op->data.nbytes > f->devtype_data->txfifo)
  365. return false;
  366. return true;
  367. }
  368. /* Instead of busy looping invoke readl_poll_sleep_timeout functionality. */
  369. static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem *base,
  370. u32 mask, u32 delay_us,
  371. u32 timeout_us, bool c)
  372. {
  373. u32 reg;
  374. if (!f->devtype_data->little_endian)
  375. mask = (u32)cpu_to_be32(mask);
  376. if (c)
  377. return readl_poll_sleep_timeout(base, reg, (reg & mask),
  378. delay_us, timeout_us);
  379. else
  380. return readl_poll_sleep_timeout(base, reg, !(reg & mask),
  381. delay_us, timeout_us);
  382. }
  383. /*
  384. * If the slave device content being changed by Write/Erase, need to
  385. * invalidate the AHB buffer. This can be achieved by doing the reset
  386. * of controller after setting MCR0[SWRESET] bit.
  387. */
  388. static inline void nxp_fspi_invalid(struct nxp_fspi *f)
  389. {
  390. u32 reg;
  391. int ret;
  392. reg = fspi_readl(f, f->iobase + FSPI_MCR0);
  393. fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
  394. /* w1c register, wait unit clear */
  395. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
  396. FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
  397. WARN_ON(ret);
  398. }
  399. static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
  400. const struct spi_mem_op *op)
  401. {
  402. void __iomem *base = f->iobase;
  403. u32 lutval[4] = {};
  404. int lutidx = 1, i;
  405. /* cmd */
  406. lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
  407. op->cmd.opcode);
  408. /* addr bytes */
  409. if (op->addr.nbytes) {
  410. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
  411. LUT_PAD(op->addr.buswidth),
  412. op->addr.nbytes * 8);
  413. lutidx++;
  414. }
  415. /* dummy bytes, if needed */
  416. if (op->dummy.nbytes) {
  417. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
  418. /*
  419. * Due to FlexSPI controller limitation number of PAD for dummy
  420. * buswidth needs to be programmed as equal to data buswidth.
  421. */
  422. LUT_PAD(op->data.buswidth),
  423. op->dummy.nbytes * 8 /
  424. op->dummy.buswidth);
  425. lutidx++;
  426. }
  427. /* read/write data bytes */
  428. if (op->data.nbytes) {
  429. lutval[lutidx / 2] |= LUT_DEF(lutidx,
  430. op->data.dir == SPI_MEM_DATA_IN ?
  431. LUT_NXP_READ : LUT_NXP_WRITE,
  432. LUT_PAD(op->data.buswidth),
  433. 0);
  434. lutidx++;
  435. }
  436. /* stop condition. */
  437. lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0);
  438. /* unlock LUT */
  439. fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
  440. fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
  441. /* fill LUT */
  442. for (i = 0; i < ARRAY_SIZE(lutval); i++)
  443. fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
  444. dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n",
  445. op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]);
  446. /* lock LUT */
  447. fspi_writel(f, FSPI_LUTKEY_VALUE, f->iobase + FSPI_LUTKEY);
  448. fspi_writel(f, FSPI_LCKER_LOCK, f->iobase + FSPI_LCKCR);
  449. }
  450. #if CONFIG_IS_ENABLED(CLK)
  451. static int nxp_fspi_clk_prep_enable(struct nxp_fspi *f)
  452. {
  453. int ret;
  454. ret = clk_enable(&f->clk_en);
  455. if (ret)
  456. return ret;
  457. ret = clk_enable(&f->clk);
  458. if (ret) {
  459. clk_disable(&f->clk_en);
  460. return ret;
  461. }
  462. return 0;
  463. }
  464. static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *f)
  465. {
  466. clk_disable(&f->clk);
  467. clk_disable(&f->clk_en);
  468. }
  469. #endif
  470. /*
  471. * In FlexSPI controller, flash access is based on value of FSPI_FLSHXXCR0
  472. * register and start base address of the slave device.
  473. *
  474. * (Higher address)
  475. * -------- <-- FLSHB2CR0
  476. * | B2 |
  477. * | |
  478. * B2 start address --> -------- <-- FLSHB1CR0
  479. * | B1 |
  480. * | |
  481. * B1 start address --> -------- <-- FLSHA2CR0
  482. * | A2 |
  483. * | |
  484. * A2 start address --> -------- <-- FLSHA1CR0
  485. * | A1 |
  486. * | |
  487. * A1 start address --> -------- (Lower address)
  488. *
  489. *
  490. * Start base address defines the starting address range for given CS and
  491. * FSPI_FLSHXXCR0 defines the size of the slave device connected at given CS.
  492. *
  493. * But, different targets are having different combinations of number of CS,
  494. * some targets only have single CS or two CS covering controller's full
  495. * memory mapped space area.
  496. * Thus, implementation is being done as independent of the size and number
  497. * of the connected slave device.
  498. * Assign controller memory mapped space size as the size to the connected
  499. * slave device.
  500. * Mark FLSHxxCR0 as zero initially and then assign value only to the selected
  501. * chip-select Flash configuration register.
  502. *
  503. * For e.g. to access CS2 (B1), FLSHB1CR0 register would be equal to the
  504. * memory mapped size of the controller.
  505. * Value for rest of the CS FLSHxxCR0 register would be zero.
  506. *
  507. */
  508. static void nxp_fspi_select_mem(struct nxp_fspi *f, int chip_select)
  509. {
  510. u64 size_kb;
  511. /* Reset FLSHxxCR0 registers */
  512. fspi_writel(f, 0, f->iobase + FSPI_FLSHA1CR0);
  513. fspi_writel(f, 0, f->iobase + FSPI_FLSHA2CR0);
  514. fspi_writel(f, 0, f->iobase + FSPI_FLSHB1CR0);
  515. fspi_writel(f, 0, f->iobase + FSPI_FLSHB2CR0);
  516. /* Assign controller memory mapped space as size, KBytes, of flash. */
  517. size_kb = FSPI_FLSHXCR0_SZ(f->memmap_phy_size);
  518. fspi_writel(f, size_kb, f->iobase + FSPI_FLSHA1CR0 +
  519. 4 * chip_select);
  520. dev_dbg(f->dev, "Slave device [CS:%x] selected\n", chip_select);
  521. }
  522. static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op)
  523. {
  524. u32 len = op->data.nbytes;
  525. /* Read out the data directly from the AHB buffer. */
  526. memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len);
  527. }
  528. static void nxp_fspi_fill_txfifo(struct nxp_fspi *f,
  529. const struct spi_mem_op *op)
  530. {
  531. void __iomem *base = f->iobase;
  532. int i, ret;
  533. u8 *buf = (u8 *)op->data.buf.out;
  534. /* clear the TX FIFO. */
  535. fspi_writel(f, FSPI_IPTXFCR_CLR, base + FSPI_IPTXFCR);
  536. /*
  537. * Default value of water mark level is 8 bytes, hence in single
  538. * write request controller can write max 8 bytes of data.
  539. */
  540. for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 8); i += 8) {
  541. /* Wait for TXFIFO empty */
  542. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  543. FSPI_INTR_IPTXWE, 0,
  544. POLL_TOUT, true);
  545. WARN_ON(ret);
  546. fspi_writel(f, *(u32 *)(buf + i), base + FSPI_TFDR);
  547. fspi_writel(f, *(u32 *)(buf + i + 4), base + FSPI_TFDR + 4);
  548. fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
  549. }
  550. if (i < op->data.nbytes) {
  551. u32 data = 0;
  552. int j;
  553. /* Wait for TXFIFO empty */
  554. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  555. FSPI_INTR_IPTXWE, 0,
  556. POLL_TOUT, true);
  557. WARN_ON(ret);
  558. for (j = 0; j < ALIGN(op->data.nbytes - i, 4); j += 4) {
  559. memcpy(&data, buf + i + j, 4);
  560. fspi_writel(f, data, base + FSPI_TFDR + j);
  561. }
  562. fspi_writel(f, FSPI_INTR_IPTXWE, base + FSPI_INTR);
  563. }
  564. }
  565. static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
  566. const struct spi_mem_op *op)
  567. {
  568. void __iomem *base = f->iobase;
  569. int i, ret;
  570. int len = op->data.nbytes;
  571. u8 *buf = (u8 *)op->data.buf.in;
  572. /*
  573. * Default value of water mark level is 8 bytes, hence in single
  574. * read request controller can read max 8 bytes of data.
  575. */
  576. for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
  577. /* Wait for RXFIFO available */
  578. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  579. FSPI_INTR_IPRXWA, 0,
  580. POLL_TOUT, true);
  581. WARN_ON(ret);
  582. *(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
  583. *(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
  584. /* move the FIFO pointer */
  585. fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
  586. }
  587. if (i < len) {
  588. u32 tmp;
  589. int size, j;
  590. buf = op->data.buf.in + i;
  591. /* Wait for RXFIFO available */
  592. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
  593. FSPI_INTR_IPRXWA, 0,
  594. POLL_TOUT, true);
  595. WARN_ON(ret);
  596. len = op->data.nbytes - i;
  597. for (j = 0; j < op->data.nbytes - i; j += 4) {
  598. tmp = fspi_readl(f, base + FSPI_RFDR + j);
  599. size = min(len, 4);
  600. memcpy(buf + j, &tmp, size);
  601. len -= size;
  602. }
  603. }
  604. /* invalid the RXFIFO */
  605. fspi_writel(f, FSPI_IPRXFCR_CLR, base + FSPI_IPRXFCR);
  606. /* move the FIFO pointer */
  607. fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
  608. }
  609. static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
  610. {
  611. void __iomem *base = f->iobase;
  612. int seqnum = 0;
  613. int err = 0;
  614. u32 reg;
  615. reg = fspi_readl(f, base + FSPI_IPRXFCR);
  616. /* invalid RXFIFO first */
  617. reg &= ~FSPI_IPRXFCR_DMA_EN;
  618. reg = reg | FSPI_IPRXFCR_CLR;
  619. fspi_writel(f, reg, base + FSPI_IPRXFCR);
  620. fspi_writel(f, op->addr.val, base + FSPI_IPCR0);
  621. /*
  622. * Always start the sequence at the same index since we update
  623. * the LUT at each exec_op() call. And also specify the DATA
  624. * length, since it's has not been specified in the LUT.
  625. */
  626. fspi_writel(f, op->data.nbytes |
  627. (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
  628. (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
  629. base + FSPI_IPCR1);
  630. /* Trigger the LUT now. */
  631. fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
  632. /* Wait for the completion. */
  633. err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
  634. FSPI_STS0_ARB_IDLE, 1, 1000 * 1000, true);
  635. /* Invoke IP data read, if request is of data read. */
  636. if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN)
  637. nxp_fspi_read_rxfifo(f, op);
  638. return err;
  639. }
  640. static int nxp_fspi_exec_op(struct spi_slave *slave,
  641. const struct spi_mem_op *op)
  642. {
  643. struct nxp_fspi *f;
  644. struct udevice *bus;
  645. int err = 0;
  646. bus = slave->dev->parent;
  647. f = dev_get_priv(bus);
  648. /* Wait for controller being ready. */
  649. err = fspi_readl_poll_tout(f, f->iobase + FSPI_STS0,
  650. FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
  651. WARN_ON(err);
  652. nxp_fspi_prepare_lut(f, op);
  653. /*
  654. * If we have large chunks of data, we read them through the AHB bus
  655. * by accessing the mapped memory. In all other cases we use
  656. * IP commands to access the flash.
  657. */
  658. if (op->data.nbytes > (f->devtype_data->rxfifo - 4) &&
  659. op->data.dir == SPI_MEM_DATA_IN) {
  660. nxp_fspi_read_ahb(f, op);
  661. } else {
  662. if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
  663. nxp_fspi_fill_txfifo(f, op);
  664. err = nxp_fspi_do_op(f, op);
  665. }
  666. /* Invalidate the data in the AHB buffer. */
  667. nxp_fspi_invalid(f);
  668. return err;
  669. }
  670. static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
  671. struct spi_mem_op *op)
  672. {
  673. struct nxp_fspi *f;
  674. struct udevice *bus;
  675. bus = slave->dev->parent;
  676. f = dev_get_priv(bus);
  677. if (op->data.dir == SPI_MEM_DATA_OUT) {
  678. if (op->data.nbytes > f->devtype_data->txfifo)
  679. op->data.nbytes = f->devtype_data->txfifo;
  680. } else {
  681. if (op->data.nbytes > f->devtype_data->ahb_buf_size)
  682. op->data.nbytes = f->devtype_data->ahb_buf_size;
  683. else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
  684. op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8);
  685. }
  686. return 0;
  687. }
  688. static int nxp_fspi_default_setup(struct nxp_fspi *f)
  689. {
  690. void __iomem *base = f->iobase;
  691. int ret, i;
  692. u32 reg;
  693. #if CONFIG_IS_ENABLED(CLK)
  694. /* disable and unprepare clock to avoid glitch pass to controller */
  695. nxp_fspi_clk_disable_unprep(f);
  696. /* the default frequency, we will change it later if necessary. */
  697. ret = clk_set_rate(&f->clk, 20000000);
  698. if (ret)
  699. return ret;
  700. ret = nxp_fspi_clk_prep_enable(f);
  701. if (ret)
  702. return ret;
  703. #endif
  704. /* Reset the module */
  705. /* w1c register, wait unit clear */
  706. ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
  707. FSPI_MCR0_SWRST, 0, POLL_TOUT, false);
  708. WARN_ON(ret);
  709. /* Disable the module */
  710. fspi_writel(f, FSPI_MCR0_MDIS, base + FSPI_MCR0);
  711. /* Reset the DLL register to default value */
  712. fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
  713. fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
  714. /* enable module */
  715. fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
  716. base + FSPI_MCR0);
  717. /*
  718. * Disable same device enable bit and configure all slave devices
  719. * independently.
  720. */
  721. reg = fspi_readl(f, f->iobase + FSPI_MCR2);
  722. reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
  723. fspi_writel(f, reg, base + FSPI_MCR2);
  724. /* AHB configuration for access buffer 0~7. */
  725. for (i = 0; i < 7; i++)
  726. fspi_writel(f, 0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
  727. /*
  728. * Set ADATSZ with the maximum AHB buffer size to improve the read
  729. * performance.
  730. */
  731. fspi_writel(f, (f->devtype_data->ahb_buf_size / 8 |
  732. FSPI_AHBRXBUF0CR7_PREF), base + FSPI_AHBRX_BUF7CR0);
  733. /* prefetch and no start address alignment limitation */
  734. fspi_writel(f, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT,
  735. base + FSPI_AHBCR);
  736. /* AHB Read - Set lut sequence ID for all CS. */
  737. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
  738. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
  739. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
  740. fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
  741. return 0;
  742. }
  743. static int nxp_fspi_probe(struct udevice *bus)
  744. {
  745. struct nxp_fspi *f = dev_get_priv(bus);
  746. f->devtype_data =
  747. (struct nxp_fspi_devtype_data *)dev_get_driver_data(bus);
  748. nxp_fspi_default_setup(f);
  749. return 0;
  750. }
  751. static int nxp_fspi_claim_bus(struct udevice *dev)
  752. {
  753. struct nxp_fspi *f;
  754. struct udevice *bus;
  755. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  756. bus = dev->parent;
  757. f = dev_get_priv(bus);
  758. nxp_fspi_select_mem(f, slave_plat->cs);
  759. return 0;
  760. }
  761. static int nxp_fspi_set_speed(struct udevice *bus, uint speed)
  762. {
  763. #if CONFIG_IS_ENABLED(CLK)
  764. struct nxp_fspi *f = dev_get_priv(bus);
  765. int ret;
  766. nxp_fspi_clk_disable_unprep(f);
  767. ret = clk_set_rate(&f->clk, speed);
  768. if (ret)
  769. return ret;
  770. ret = nxp_fspi_clk_prep_enable(f);
  771. if (ret)
  772. return ret;
  773. #endif
  774. return 0;
  775. }
  776. static int nxp_fspi_set_mode(struct udevice *bus, uint mode)
  777. {
  778. /* Nothing to do */
  779. return 0;
  780. }
  781. static int nxp_fspi_ofdata_to_platdata(struct udevice *bus)
  782. {
  783. struct nxp_fspi *f = dev_get_priv(bus);
  784. #if CONFIG_IS_ENABLED(CLK)
  785. int ret;
  786. #endif
  787. fdt_addr_t iobase;
  788. fdt_addr_t iobase_size;
  789. fdt_addr_t ahb_addr;
  790. fdt_addr_t ahb_size;
  791. f->dev = bus;
  792. iobase = devfdt_get_addr_size_name(bus, "fspi_base", &iobase_size);
  793. if (iobase == FDT_ADDR_T_NONE) {
  794. dev_err(bus, "fspi_base regs missing\n");
  795. return -ENODEV;
  796. }
  797. f->iobase = map_physmem(iobase, iobase_size, MAP_NOCACHE);
  798. ahb_addr = devfdt_get_addr_size_name(bus, "fspi_mmap", &ahb_size);
  799. if (ahb_addr == FDT_ADDR_T_NONE) {
  800. dev_err(bus, "fspi_mmap regs missing\n");
  801. return -ENODEV;
  802. }
  803. f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE);
  804. f->memmap_phy_size = ahb_size;
  805. #if CONFIG_IS_ENABLED(CLK)
  806. ret = clk_get_by_name(bus, "fspi_en", &f->clk_en);
  807. if (ret) {
  808. dev_err(bus, "failed to get fspi_en clock\n");
  809. return ret;
  810. }
  811. ret = clk_get_by_name(bus, "fspi", &f->clk);
  812. if (ret) {
  813. dev_err(bus, "failed to get fspi clock\n");
  814. return ret;
  815. }
  816. #endif
  817. dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr);
  818. return 0;
  819. }
  820. static const struct spi_controller_mem_ops nxp_fspi_mem_ops = {
  821. .adjust_op_size = nxp_fspi_adjust_op_size,
  822. .supports_op = nxp_fspi_supports_op,
  823. .exec_op = nxp_fspi_exec_op,
  824. };
  825. static const struct dm_spi_ops nxp_fspi_ops = {
  826. .claim_bus = nxp_fspi_claim_bus,
  827. .set_speed = nxp_fspi_set_speed,
  828. .set_mode = nxp_fspi_set_mode,
  829. .mem_ops = &nxp_fspi_mem_ops,
  830. };
  831. static const struct udevice_id nxp_fspi_ids[] = {
  832. { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
  833. { }
  834. };
  835. U_BOOT_DRIVER(nxp_fspi) = {
  836. .name = "nxp_fspi",
  837. .id = UCLASS_SPI,
  838. .of_match = nxp_fspi_ids,
  839. .ops = &nxp_fspi_ops,
  840. .ofdata_to_platdata = nxp_fspi_ofdata_to_platdata,
  841. .priv_auto_alloc_size = sizeof(struct nxp_fspi),
  842. .probe = nxp_fspi_probe,
  843. };