mxs_spi.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 SPI driver
  4. *
  5. * Copyright (C) 2019 DENX Software Engineering
  6. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  7. *
  8. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  9. * on behalf of DENX Software Engineering GmbH
  10. *
  11. * NOTE: This driver only supports the SPI-controller chipselects,
  12. * GPIO driven chipselects are not supported.
  13. */
  14. #include <common.h>
  15. #include <dm.h>
  16. #include <dt-structs.h>
  17. #include <cpu_func.h>
  18. #include <errno.h>
  19. #include <log.h>
  20. #include <malloc.h>
  21. #include <memalign.h>
  22. #include <spi.h>
  23. #include <asm/cache.h>
  24. #include <linux/bitops.h>
  25. #include <linux/errno.h>
  26. #include <asm/io.h>
  27. #include <asm/arch/clock.h>
  28. #include <asm/arch/imx-regs.h>
  29. #include <asm/arch/sys_proto.h>
  30. #include <asm/mach-imx/dma.h>
  31. #define MXS_SPI_MAX_TIMEOUT 1000000
  32. #define MXS_SPI_PORT_OFFSET 0x2000
  33. #define MXS_SSP_CHIPSELECT_MASK 0x00300000
  34. #define MXS_SSP_CHIPSELECT_SHIFT 20
  35. #define MXSSSP_SMALL_TRANSFER 512
  36. /* Base numbers of i.MX2[38] clk for ssp0 IP block */
  37. #define MXS_SSP_IMX23_CLKID_SSP0 33
  38. #define MXS_SSP_IMX28_CLKID_SSP0 46
  39. struct mxs_spi_platdata {
  40. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  41. struct dtd_fsl_imx23_spi dtplat;
  42. #endif
  43. s32 frequency; /* Default clock frequency, -1 for none */
  44. fdt_addr_t base; /* SPI IP block base address */
  45. int num_cs; /* Number of CSes supported */
  46. int dma_id; /* ID of the DMA channel */
  47. int clk_id; /* ID of the SSP clock */
  48. };
  49. struct mxs_spi_priv {
  50. struct mxs_ssp_regs *regs;
  51. unsigned int dma_channel;
  52. unsigned int max_freq;
  53. unsigned int clk_id;
  54. unsigned int mode;
  55. };
  56. static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
  57. {
  58. writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
  59. writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
  60. }
  61. static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
  62. {
  63. writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
  64. writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
  65. }
  66. static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
  67. char *data, int length, int write,
  68. unsigned long flags)
  69. {
  70. struct mxs_ssp_regs *ssp_regs = priv->regs;
  71. if (flags & SPI_XFER_BEGIN)
  72. mxs_spi_start_xfer(ssp_regs);
  73. while (length--) {
  74. /* We transfer 1 byte */
  75. #if defined(CONFIG_MX23)
  76. writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
  77. writel(1, &ssp_regs->hw_ssp_ctrl0_set);
  78. #elif defined(CONFIG_MX28)
  79. writel(1, &ssp_regs->hw_ssp_xfer_size);
  80. #endif
  81. if ((flags & SPI_XFER_END) && !length)
  82. mxs_spi_end_xfer(ssp_regs);
  83. if (write)
  84. writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
  85. else
  86. writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
  87. writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
  88. if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
  89. SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
  90. printf("MXS SPI: Timeout waiting for start\n");
  91. return -ETIMEDOUT;
  92. }
  93. if (write)
  94. writel(*data++, &ssp_regs->hw_ssp_data);
  95. writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
  96. if (!write) {
  97. if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
  98. SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
  99. printf("MXS SPI: Timeout waiting for data\n");
  100. return -ETIMEDOUT;
  101. }
  102. *data = readl(&ssp_regs->hw_ssp_data);
  103. data++;
  104. }
  105. if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
  106. SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
  107. printf("MXS SPI: Timeout waiting for finish\n");
  108. return -ETIMEDOUT;
  109. }
  110. }
  111. return 0;
  112. }
  113. static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
  114. char *data, int length, int write,
  115. unsigned long flags)
  116. { struct mxs_ssp_regs *ssp_regs = priv->regs;
  117. const int xfer_max_sz = 0xff00;
  118. const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
  119. struct mxs_dma_desc *dp;
  120. uint32_t ctrl0;
  121. uint32_t cache_data_count;
  122. const uint32_t dstart = (uint32_t)data;
  123. int dmach;
  124. int tl;
  125. int ret = 0;
  126. #if defined(CONFIG_MX23)
  127. const int mxs_spi_pio_words = 1;
  128. #elif defined(CONFIG_MX28)
  129. const int mxs_spi_pio_words = 4;
  130. #endif
  131. ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
  132. memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
  133. ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
  134. ctrl0 |= SSP_CTRL0_DATA_XFER;
  135. if (flags & SPI_XFER_BEGIN)
  136. ctrl0 |= SSP_CTRL0_LOCK_CS;
  137. if (!write)
  138. ctrl0 |= SSP_CTRL0_READ;
  139. if (length % ARCH_DMA_MINALIGN)
  140. cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
  141. else
  142. cache_data_count = length;
  143. /* Flush data to DRAM so DMA can pick them up */
  144. if (write)
  145. flush_dcache_range(dstart, dstart + cache_data_count);
  146. /* Invalidate the area, so no writeback into the RAM races with DMA */
  147. invalidate_dcache_range(dstart, dstart + cache_data_count);
  148. dmach = priv->dma_channel;
  149. dp = desc;
  150. while (length) {
  151. dp->address = (dma_addr_t)dp;
  152. dp->cmd.address = (dma_addr_t)data;
  153. /*
  154. * This is correct, even though it does indeed look insane.
  155. * I hereby have to, wholeheartedly, thank Freescale Inc.,
  156. * for always inventing insane hardware and keeping me busy
  157. * and employed ;-)
  158. */
  159. if (write)
  160. dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
  161. else
  162. dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
  163. /*
  164. * The DMA controller can transfer large chunks (64kB) at
  165. * time by setting the transfer length to 0. Setting tl to
  166. * 0x10000 will overflow below and make .data contain 0.
  167. * Otherwise, 0xff00 is the transfer maximum.
  168. */
  169. if (length >= 0x10000)
  170. tl = 0x10000;
  171. else
  172. tl = min(length, xfer_max_sz);
  173. dp->cmd.data |=
  174. ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
  175. (mxs_spi_pio_words << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
  176. MXS_DMA_DESC_HALT_ON_TERMINATE |
  177. MXS_DMA_DESC_TERMINATE_FLUSH;
  178. data += tl;
  179. length -= tl;
  180. if (!length) {
  181. dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
  182. if (flags & SPI_XFER_END) {
  183. ctrl0 &= ~SSP_CTRL0_LOCK_CS;
  184. ctrl0 |= SSP_CTRL0_IGNORE_CRC;
  185. }
  186. }
  187. /*
  188. * Write CTRL0, CMD0, CMD1 and XFER_SIZE registers in
  189. * case of MX28, write only CTRL0 in case of MX23 due
  190. * to the difference in register layout. It is utterly
  191. * essential that the XFER_SIZE register is written on
  192. * a per-descriptor basis with the same size as is the
  193. * descriptor!
  194. */
  195. dp->cmd.pio_words[0] = ctrl0;
  196. #ifdef CONFIG_MX28
  197. dp->cmd.pio_words[1] = 0;
  198. dp->cmd.pio_words[2] = 0;
  199. dp->cmd.pio_words[3] = tl;
  200. #endif
  201. mxs_dma_desc_append(dmach, dp);
  202. dp++;
  203. }
  204. if (mxs_dma_go(dmach))
  205. ret = -EINVAL;
  206. /* The data arrived into DRAM, invalidate cache over them */
  207. if (!write)
  208. invalidate_dcache_range(dstart, dstart + cache_data_count);
  209. return ret;
  210. }
  211. int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
  212. const void *dout, void *din, unsigned long flags)
  213. {
  214. struct udevice *bus = dev_get_parent(dev);
  215. struct mxs_spi_priv *priv = dev_get_priv(bus);
  216. struct mxs_ssp_regs *ssp_regs = priv->regs;
  217. int len = bitlen / 8;
  218. char dummy;
  219. int write = 0;
  220. char *data = NULL;
  221. int dma = 1;
  222. if (bitlen == 0) {
  223. if (flags & SPI_XFER_END) {
  224. din = (void *)&dummy;
  225. len = 1;
  226. } else
  227. return 0;
  228. }
  229. /* Half-duplex only */
  230. if (din && dout)
  231. return -EINVAL;
  232. /* No data */
  233. if (!din && !dout)
  234. return 0;
  235. if (dout) {
  236. data = (char *)dout;
  237. write = 1;
  238. } else if (din) {
  239. data = (char *)din;
  240. write = 0;
  241. }
  242. /*
  243. * Check for alignment, if the buffer is aligned, do DMA transfer,
  244. * PIO otherwise. This is a temporary workaround until proper bounce
  245. * buffer is in place.
  246. */
  247. if (dma) {
  248. if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
  249. dma = 0;
  250. if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
  251. dma = 0;
  252. }
  253. if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
  254. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
  255. return mxs_spi_xfer_pio(priv, data, len, write, flags);
  256. } else {
  257. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
  258. return mxs_spi_xfer_dma(priv, data, len, write, flags);
  259. }
  260. }
  261. static int mxs_spi_probe(struct udevice *bus)
  262. {
  263. struct mxs_spi_platdata *plat = dev_get_platdata(bus);
  264. struct mxs_spi_priv *priv = dev_get_priv(bus);
  265. int ret;
  266. debug("%s: probe\n", __func__);
  267. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  268. struct dtd_fsl_imx23_spi *dtplat = &plat->dtplat;
  269. struct phandle_1_arg *p1a = &dtplat->clocks[0];
  270. priv->regs = (struct mxs_ssp_regs *)dtplat->reg[0];
  271. priv->dma_channel = dtplat->dmas[1];
  272. priv->clk_id = p1a->arg[0];
  273. priv->max_freq = dtplat->spi_max_frequency;
  274. plat->num_cs = dtplat->num_cs;
  275. debug("OF_PLATDATA: regs: 0x%x max freq: %d clkid: %d\n",
  276. (unsigned int)priv->regs, priv->max_freq, priv->clk_id);
  277. #else
  278. priv->regs = (struct mxs_ssp_regs *)plat->base;
  279. priv->max_freq = plat->frequency;
  280. priv->dma_channel = plat->dma_id;
  281. priv->clk_id = plat->clk_id;
  282. #endif
  283. mxs_reset_block(&priv->regs->hw_ssp_ctrl0_reg);
  284. ret = mxs_dma_init_channel(priv->dma_channel);
  285. if (ret) {
  286. printf("%s: DMA init channel error %d\n", __func__, ret);
  287. return ret;
  288. }
  289. return 0;
  290. }
  291. static int mxs_spi_claim_bus(struct udevice *dev)
  292. {
  293. struct udevice *bus = dev_get_parent(dev);
  294. struct mxs_spi_priv *priv = dev_get_priv(bus);
  295. struct mxs_ssp_regs *ssp_regs = priv->regs;
  296. int cs = spi_chip_select(dev);
  297. /*
  298. * i.MX28 supports up to 3 CS (SSn0, SSn1, SSn2)
  299. * To set them it uses following tuple (WAIT_FOR_IRQ,WAIT_FOR_CMD),
  300. * where:
  301. *
  302. * WAIT_FOR_IRQ is bit 21 of HW_SSP_CTRL0
  303. * WAIT_FOR_CMD is bit 20 (#defined as MXS_SSP_CHIPSELECT_SHIFT here) of
  304. * HW_SSP_CTRL0
  305. * SSn0 b00
  306. * SSn1 b01
  307. * SSn2 b10 (which require setting WAIT_FOR_IRQ)
  308. *
  309. * However, for now i.MX28 SPI driver will support up till 2 CSes
  310. * (SSn0, and SSn1).
  311. */
  312. /* Ungate SSP clock and set active CS */
  313. clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
  314. BIT(MXS_SSP_CHIPSELECT_SHIFT) |
  315. SSP_CTRL0_CLKGATE, (cs << MXS_SSP_CHIPSELECT_SHIFT));
  316. return 0;
  317. }
  318. static int mxs_spi_release_bus(struct udevice *dev)
  319. {
  320. struct udevice *bus = dev_get_parent(dev);
  321. struct mxs_spi_priv *priv = dev_get_priv(bus);
  322. struct mxs_ssp_regs *ssp_regs = priv->regs;
  323. /* Gate SSP clock */
  324. setbits_le32(&ssp_regs->hw_ssp_ctrl0, SSP_CTRL0_CLKGATE);
  325. return 0;
  326. }
  327. static int mxs_spi_set_speed(struct udevice *bus, uint speed)
  328. {
  329. struct mxs_spi_priv *priv = dev_get_priv(bus);
  330. #ifdef CONFIG_MX28
  331. int clkid = priv->clk_id - MXS_SSP_IMX28_CLKID_SSP0;
  332. #else /* CONFIG_MX23 */
  333. int clkid = priv->clk_id - MXS_SSP_IMX23_CLKID_SSP0;
  334. #endif
  335. if (speed > priv->max_freq)
  336. speed = priv->max_freq;
  337. debug("%s speed: %u [Hz] clkid: %d\n", __func__, speed, clkid);
  338. mxs_set_ssp_busclock(clkid, speed / 1000);
  339. return 0;
  340. }
  341. static int mxs_spi_set_mode(struct udevice *bus, uint mode)
  342. {
  343. struct mxs_spi_priv *priv = dev_get_priv(bus);
  344. struct mxs_ssp_regs *ssp_regs = priv->regs;
  345. u32 reg;
  346. priv->mode = mode;
  347. debug("%s: mode 0x%x\n", __func__, mode);
  348. reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
  349. reg |= (priv->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
  350. reg |= (priv->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
  351. writel(reg, &ssp_regs->hw_ssp_ctrl1);
  352. /* Single bit SPI support */
  353. writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
  354. return 0;
  355. }
  356. static const struct dm_spi_ops mxs_spi_ops = {
  357. .claim_bus = mxs_spi_claim_bus,
  358. .release_bus = mxs_spi_release_bus,
  359. .xfer = mxs_spi_xfer,
  360. .set_speed = mxs_spi_set_speed,
  361. .set_mode = mxs_spi_set_mode,
  362. /*
  363. * cs_info is not needed, since we require all chip selects to be
  364. * in the device tree explicitly
  365. */
  366. };
  367. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  368. static int mxs_ofdata_to_platdata(struct udevice *bus)
  369. {
  370. struct mxs_spi_platdata *plat = bus->platdata;
  371. u32 prop[2];
  372. int ret;
  373. plat->base = dev_read_addr(bus);
  374. plat->frequency =
  375. dev_read_u32_default(bus, "spi-max-frequency", 40000000);
  376. plat->num_cs = dev_read_u32_default(bus, "num-cs", 2);
  377. ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
  378. if (ret) {
  379. printf("%s: Reading 'dmas' property failed!\n", __func__);
  380. return ret;
  381. }
  382. plat->dma_id = prop[1];
  383. ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
  384. if (ret) {
  385. printf("%s: Reading 'clocks' property failed!\n", __func__);
  386. return ret;
  387. }
  388. plat->clk_id = prop[1];
  389. debug("%s: base=0x%x, max-frequency=%d num-cs=%d dma_id=%d clk_id=%d\n",
  390. __func__, (uint)plat->base, plat->frequency, plat->num_cs,
  391. plat->dma_id, plat->clk_id);
  392. return 0;
  393. }
  394. static const struct udevice_id mxs_spi_ids[] = {
  395. { .compatible = "fsl,imx23-spi" },
  396. { .compatible = "fsl,imx28-spi" },
  397. { }
  398. };
  399. #endif
  400. U_BOOT_DRIVER(fsl_imx23_spi) = {
  401. .name = "fsl_imx23_spi",
  402. .id = UCLASS_SPI,
  403. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  404. .of_match = mxs_spi_ids,
  405. .ofdata_to_platdata = mxs_ofdata_to_platdata,
  406. #endif
  407. .platdata_auto_alloc_size = sizeof(struct mxs_spi_platdata),
  408. .ops = &mxs_spi_ops,
  409. .priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
  410. .probe = mxs_spi_probe,
  411. };
  412. U_BOOT_DRIVER_ALIAS(fsl_imx23_spi, fsl_imx28_spi)