mxc_spi.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <malloc.h>
  9. #include <spi.h>
  10. #include <dm/device_compat.h>
  11. #include <linux/bitops.h>
  12. #include <linux/delay.h>
  13. #include <linux/errno.h>
  14. #include <asm/io.h>
  15. #include <asm/gpio.h>
  16. #include <asm/arch/imx-regs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/mach-imx/spi.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #ifdef CONFIG_MX27
  21. /* i.MX27 has a completely wrong register layout and register definitions in the
  22. * datasheet, the correct one is in the Freescale's Linux driver */
  23. #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
  24. "See linux mxc_spi driver from Freescale for details."
  25. #endif
  26. __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
  27. {
  28. return -1;
  29. }
  30. #define OUT MXC_GPIO_DIRECTION_OUT
  31. #define reg_read readl
  32. #define reg_write(a, v) writel(v, a)
  33. #if !defined(CONFIG_SYS_SPI_MXC_WAIT)
  34. #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
  35. #endif
  36. #define MAX_CS_COUNT 4
  37. struct mxc_spi_slave {
  38. struct spi_slave slave;
  39. unsigned long base;
  40. u32 ctrl_reg;
  41. #if defined(MXC_ECSPI)
  42. u32 cfg_reg;
  43. #endif
  44. int gpio;
  45. int ss_pol;
  46. unsigned int max_hz;
  47. unsigned int mode;
  48. struct gpio_desc ss;
  49. struct gpio_desc cs_gpios[MAX_CS_COUNT];
  50. struct udevice *dev;
  51. };
  52. static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
  53. {
  54. return container_of(slave, struct mxc_spi_slave, slave);
  55. }
  56. static void mxc_spi_cs_activate(struct mxc_spi_slave *mxcs)
  57. {
  58. #if CONFIG_IS_ENABLED(DM_SPI)
  59. struct udevice *dev = mxcs->dev;
  60. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  61. u32 cs = slave_plat->cs;
  62. if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
  63. return;
  64. dm_gpio_set_value(&mxcs->cs_gpios[cs], 1);
  65. #else
  66. if (mxcs->gpio > 0)
  67. gpio_set_value(mxcs->gpio, mxcs->ss_pol);
  68. #endif
  69. }
  70. static void mxc_spi_cs_deactivate(struct mxc_spi_slave *mxcs)
  71. {
  72. #if CONFIG_IS_ENABLED(DM_SPI)
  73. struct udevice *dev = mxcs->dev;
  74. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  75. u32 cs = slave_plat->cs;
  76. if (!dm_gpio_is_valid(&mxcs->cs_gpios[cs]))
  77. return;
  78. dm_gpio_set_value(&mxcs->cs_gpios[cs], 0);
  79. #else
  80. if (mxcs->gpio > 0)
  81. gpio_set_value(mxcs->gpio, !(mxcs->ss_pol));
  82. #endif
  83. }
  84. u32 get_cspi_div(u32 div)
  85. {
  86. int i;
  87. for (i = 0; i < 8; i++) {
  88. if (div <= (4 << i))
  89. return i;
  90. }
  91. return i;
  92. }
  93. #ifdef MXC_CSPI
  94. static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
  95. {
  96. unsigned int ctrl_reg;
  97. u32 clk_src;
  98. u32 div;
  99. unsigned int max_hz = mxcs->max_hz;
  100. unsigned int mode = mxcs->mode;
  101. clk_src = mxc_get_clock(MXC_CSPI_CLK);
  102. div = DIV_ROUND_UP(clk_src, max_hz);
  103. div = get_cspi_div(div);
  104. debug("clk %d Hz, div %d, real clk %d Hz\n",
  105. max_hz, div, clk_src / (4 << div));
  106. ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
  107. MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
  108. MXC_CSPICTRL_DATARATE(div) |
  109. MXC_CSPICTRL_EN |
  110. #ifdef CONFIG_MX35
  111. MXC_CSPICTRL_SSCTL |
  112. #endif
  113. MXC_CSPICTRL_MODE;
  114. if (mode & SPI_CPHA)
  115. ctrl_reg |= MXC_CSPICTRL_PHA;
  116. if (mode & SPI_CPOL)
  117. ctrl_reg |= MXC_CSPICTRL_POL;
  118. if (mode & SPI_CS_HIGH)
  119. ctrl_reg |= MXC_CSPICTRL_SSPOL;
  120. mxcs->ctrl_reg = ctrl_reg;
  121. return 0;
  122. }
  123. #endif
  124. #ifdef MXC_ECSPI
  125. static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
  126. {
  127. u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
  128. s32 reg_ctrl, reg_config;
  129. u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
  130. u32 pre_div = 0, post_div = 0;
  131. struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
  132. unsigned int max_hz = mxcs->max_hz;
  133. unsigned int mode = mxcs->mode;
  134. /*
  135. * Reset SPI and set all CSs to master mode, if toggling
  136. * between slave and master mode we might see a glitch
  137. * on the clock line
  138. */
  139. reg_ctrl = MXC_CSPICTRL_MODE_MASK;
  140. reg_write(&regs->ctrl, reg_ctrl);
  141. reg_ctrl |= MXC_CSPICTRL_EN;
  142. reg_write(&regs->ctrl, reg_ctrl);
  143. if (clk_src > max_hz) {
  144. pre_div = (clk_src - 1) / max_hz;
  145. /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
  146. post_div = fls(pre_div);
  147. if (post_div > 4) {
  148. post_div -= 4;
  149. if (post_div >= 16) {
  150. printf("Error: no divider for the freq: %d\n",
  151. max_hz);
  152. return -1;
  153. }
  154. pre_div >>= post_div;
  155. } else {
  156. post_div = 0;
  157. }
  158. }
  159. debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
  160. reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
  161. MXC_CSPICTRL_SELCHAN(cs);
  162. reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
  163. MXC_CSPICTRL_PREDIV(pre_div);
  164. reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
  165. MXC_CSPICTRL_POSTDIV(post_div);
  166. if (mode & SPI_CS_HIGH)
  167. ss_pol = 1;
  168. if (mode & SPI_CPOL) {
  169. sclkpol = 1;
  170. sclkctl = 1;
  171. }
  172. if (mode & SPI_CPHA)
  173. sclkpha = 1;
  174. reg_config = reg_read(&regs->cfg);
  175. /*
  176. * Configuration register setup
  177. * The MX51 supports different setup for each SS
  178. */
  179. reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
  180. (ss_pol << (cs + MXC_CSPICON_SSPOL));
  181. reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
  182. (sclkpol << (cs + MXC_CSPICON_POL));
  183. reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
  184. (sclkctl << (cs + MXC_CSPICON_CTL));
  185. reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
  186. (sclkpha << (cs + MXC_CSPICON_PHA));
  187. debug("reg_ctrl = 0x%x\n", reg_ctrl);
  188. reg_write(&regs->ctrl, reg_ctrl);
  189. debug("reg_config = 0x%x\n", reg_config);
  190. reg_write(&regs->cfg, reg_config);
  191. /* save config register and control register */
  192. mxcs->ctrl_reg = reg_ctrl;
  193. mxcs->cfg_reg = reg_config;
  194. /* clear interrupt reg */
  195. reg_write(&regs->intr, 0);
  196. reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
  197. return 0;
  198. }
  199. #endif
  200. int spi_xchg_single(struct mxc_spi_slave *mxcs, unsigned int bitlen,
  201. const u8 *dout, u8 *din, unsigned long flags)
  202. {
  203. int nbytes = DIV_ROUND_UP(bitlen, 8);
  204. u32 data, cnt, i;
  205. struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
  206. u32 ts;
  207. int status;
  208. debug("%s: bitlen %d dout 0x%lx din 0x%lx\n",
  209. __func__, bitlen, (ulong)dout, (ulong)din);
  210. mxcs->ctrl_reg = (mxcs->ctrl_reg &
  211. ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
  212. MXC_CSPICTRL_BITCOUNT(bitlen - 1);
  213. reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
  214. #ifdef MXC_ECSPI
  215. reg_write(&regs->cfg, mxcs->cfg_reg);
  216. #endif
  217. /* Clear interrupt register */
  218. reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
  219. /*
  220. * The SPI controller works only with words,
  221. * check if less than a word is sent.
  222. * Access to the FIFO is only 32 bit
  223. */
  224. if (bitlen % 32) {
  225. data = 0;
  226. cnt = (bitlen % 32) / 8;
  227. if (dout) {
  228. for (i = 0; i < cnt; i++) {
  229. data = (data << 8) | (*dout++ & 0xFF);
  230. }
  231. }
  232. debug("Sending SPI 0x%x\n", data);
  233. reg_write(&regs->txdata, data);
  234. nbytes -= cnt;
  235. }
  236. data = 0;
  237. while (nbytes > 0) {
  238. data = 0;
  239. if (dout) {
  240. /* Buffer is not 32-bit aligned */
  241. if ((unsigned long)dout & 0x03) {
  242. data = 0;
  243. for (i = 0; i < 4; i++)
  244. data = (data << 8) | (*dout++ & 0xFF);
  245. } else {
  246. data = *(u32 *)dout;
  247. data = cpu_to_be32(data);
  248. dout += 4;
  249. }
  250. }
  251. debug("Sending SPI 0x%x\n", data);
  252. reg_write(&regs->txdata, data);
  253. nbytes -= 4;
  254. }
  255. /* FIFO is written, now starts the transfer setting the XCH bit */
  256. reg_write(&regs->ctrl, mxcs->ctrl_reg |
  257. MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
  258. ts = get_timer(0);
  259. status = reg_read(&regs->stat);
  260. /* Wait until the TC (Transfer completed) bit is set */
  261. while ((status & MXC_CSPICTRL_TC) == 0) {
  262. if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
  263. printf("spi_xchg_single: Timeout!\n");
  264. return -1;
  265. }
  266. status = reg_read(&regs->stat);
  267. }
  268. /* Transfer completed, clear any pending request */
  269. reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
  270. nbytes = DIV_ROUND_UP(bitlen, 8);
  271. cnt = nbytes % 32;
  272. if (bitlen % 32) {
  273. data = reg_read(&regs->rxdata);
  274. cnt = (bitlen % 32) / 8;
  275. data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
  276. debug("SPI Rx unaligned: 0x%x\n", data);
  277. if (din) {
  278. memcpy(din, &data, cnt);
  279. din += cnt;
  280. }
  281. nbytes -= cnt;
  282. }
  283. while (nbytes > 0) {
  284. u32 tmp;
  285. tmp = reg_read(&regs->rxdata);
  286. data = cpu_to_be32(tmp);
  287. debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
  288. cnt = min_t(u32, nbytes, sizeof(data));
  289. if (din) {
  290. memcpy(din, &data, cnt);
  291. din += cnt;
  292. }
  293. nbytes -= cnt;
  294. }
  295. return 0;
  296. }
  297. static int mxc_spi_xfer_internal(struct mxc_spi_slave *mxcs,
  298. unsigned int bitlen, const void *dout,
  299. void *din, unsigned long flags)
  300. {
  301. int n_bytes = DIV_ROUND_UP(bitlen, 8);
  302. int n_bits;
  303. int ret;
  304. u32 blk_size;
  305. u8 *p_outbuf = (u8 *)dout;
  306. u8 *p_inbuf = (u8 *)din;
  307. if (!mxcs)
  308. return -EINVAL;
  309. if (flags & SPI_XFER_BEGIN)
  310. mxc_spi_cs_activate(mxcs);
  311. while (n_bytes > 0) {
  312. if (n_bytes < MAX_SPI_BYTES)
  313. blk_size = n_bytes;
  314. else
  315. blk_size = MAX_SPI_BYTES;
  316. n_bits = blk_size * 8;
  317. ret = spi_xchg_single(mxcs, n_bits, p_outbuf, p_inbuf, 0);
  318. if (ret)
  319. return ret;
  320. if (dout)
  321. p_outbuf += blk_size;
  322. if (din)
  323. p_inbuf += blk_size;
  324. n_bytes -= blk_size;
  325. }
  326. if (flags & SPI_XFER_END) {
  327. mxc_spi_cs_deactivate(mxcs);
  328. }
  329. return 0;
  330. }
  331. static int mxc_spi_claim_bus_internal(struct mxc_spi_slave *mxcs, int cs)
  332. {
  333. struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
  334. int ret;
  335. reg_write(&regs->rxdata, 1);
  336. udelay(1);
  337. ret = spi_cfg_mxc(mxcs, cs);
  338. if (ret) {
  339. printf("mxc_spi: cannot setup SPI controller\n");
  340. return ret;
  341. }
  342. reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
  343. reg_write(&regs->intr, 0);
  344. return 0;
  345. }
  346. #if !CONFIG_IS_ENABLED(DM_SPI)
  347. int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
  348. void *din, unsigned long flags)
  349. {
  350. struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
  351. return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
  352. }
  353. /*
  354. * Some SPI devices require active chip-select over multiple
  355. * transactions, we achieve this using a GPIO. Still, the SPI
  356. * controller has to be configured to use one of its own chipselects.
  357. * To use this feature you have to implement board_spi_cs_gpio() to assign
  358. * a gpio value for each cs (-1 if cs doesn't need to use gpio).
  359. * You must use some unused on this SPI controller cs between 0 and 3.
  360. */
  361. static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
  362. unsigned int bus, unsigned int cs)
  363. {
  364. int ret;
  365. mxcs->gpio = board_spi_cs_gpio(bus, cs);
  366. if (mxcs->gpio == -1)
  367. return 0;
  368. gpio_request(mxcs->gpio, "spi-cs");
  369. ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
  370. if (ret) {
  371. printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
  372. return -EINVAL;
  373. }
  374. return 0;
  375. }
  376. static unsigned long spi_bases[] = {
  377. MXC_SPI_BASE_ADDRESSES
  378. };
  379. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  380. unsigned int max_hz, unsigned int mode)
  381. {
  382. struct mxc_spi_slave *mxcs;
  383. int ret;
  384. if (bus >= ARRAY_SIZE(spi_bases))
  385. return NULL;
  386. if (max_hz == 0) {
  387. printf("Error: desired clock is 0\n");
  388. return NULL;
  389. }
  390. mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
  391. if (!mxcs) {
  392. puts("mxc_spi: SPI Slave not allocated !\n");
  393. return NULL;
  394. }
  395. mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
  396. ret = setup_cs_gpio(mxcs, bus, cs);
  397. if (ret < 0) {
  398. free(mxcs);
  399. return NULL;
  400. }
  401. mxcs->base = spi_bases[bus];
  402. mxcs->max_hz = max_hz;
  403. mxcs->mode = mode;
  404. return &mxcs->slave;
  405. }
  406. void spi_free_slave(struct spi_slave *slave)
  407. {
  408. struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
  409. free(mxcs);
  410. }
  411. int spi_claim_bus(struct spi_slave *slave)
  412. {
  413. struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
  414. return mxc_spi_claim_bus_internal(mxcs, slave->cs);
  415. }
  416. void spi_release_bus(struct spi_slave *slave)
  417. {
  418. /* TODO: Shut the controller down */
  419. }
  420. #else
  421. static int mxc_spi_probe(struct udevice *bus)
  422. {
  423. struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
  424. int node = dev_of_offset(bus);
  425. const void *blob = gd->fdt_blob;
  426. int ret;
  427. int i;
  428. ret = gpio_request_list_by_name(bus, "cs-gpios", mxcs->cs_gpios,
  429. ARRAY_SIZE(mxcs->cs_gpios), 0);
  430. if (ret < 0) {
  431. pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
  432. return ret;
  433. }
  434. for (i = 0; i < ARRAY_SIZE(mxcs->cs_gpios); i++) {
  435. if (!dm_gpio_is_valid(&mxcs->cs_gpios[i]))
  436. continue;
  437. ret = dm_gpio_set_dir_flags(&mxcs->cs_gpios[i],
  438. GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
  439. if (ret) {
  440. dev_err(bus, "Setting cs %d error\n", i);
  441. return ret;
  442. }
  443. }
  444. mxcs->base = dev_read_addr(bus);
  445. if (mxcs->base == FDT_ADDR_T_NONE)
  446. return -ENODEV;
  447. mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
  448. 20000000);
  449. return 0;
  450. }
  451. static int mxc_spi_xfer(struct udevice *dev, unsigned int bitlen,
  452. const void *dout, void *din, unsigned long flags)
  453. {
  454. struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
  455. return mxc_spi_xfer_internal(mxcs, bitlen, dout, din, flags);
  456. }
  457. static int mxc_spi_claim_bus(struct udevice *dev)
  458. {
  459. struct mxc_spi_slave *mxcs = dev_get_platdata(dev->parent);
  460. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  461. mxcs->dev = dev;
  462. return mxc_spi_claim_bus_internal(mxcs, slave_plat->cs);
  463. }
  464. static int mxc_spi_release_bus(struct udevice *dev)
  465. {
  466. return 0;
  467. }
  468. static int mxc_spi_set_speed(struct udevice *bus, uint speed)
  469. {
  470. /* Nothing to do */
  471. return 0;
  472. }
  473. static int mxc_spi_set_mode(struct udevice *bus, uint mode)
  474. {
  475. struct mxc_spi_slave *mxcs = dev_get_platdata(bus);
  476. mxcs->mode = mode;
  477. mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
  478. return 0;
  479. }
  480. static const struct dm_spi_ops mxc_spi_ops = {
  481. .claim_bus = mxc_spi_claim_bus,
  482. .release_bus = mxc_spi_release_bus,
  483. .xfer = mxc_spi_xfer,
  484. .set_speed = mxc_spi_set_speed,
  485. .set_mode = mxc_spi_set_mode,
  486. };
  487. static const struct udevice_id mxc_spi_ids[] = {
  488. { .compatible = "fsl,imx51-ecspi" },
  489. { }
  490. };
  491. U_BOOT_DRIVER(mxc_spi) = {
  492. .name = "mxc_spi",
  493. .id = UCLASS_SPI,
  494. .of_match = mxc_spi_ids,
  495. .ops = &mxc_spi_ops,
  496. .platdata_auto_alloc_size = sizeof(struct mxc_spi_slave),
  497. .probe = mxc_spi_probe,
  498. };
  499. #endif