mvebu_a3700_spi.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Marvell International Ltd.
  4. *
  5. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <spi.h>
  12. #include <clk.h>
  13. #include <wait_bit.h>
  14. #include <asm/io.h>
  15. #include <dm/device_compat.h>
  16. #include <linux/bitops.h>
  17. #include <asm/gpio.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define MVEBU_SPI_A3700_XFER_RDY BIT(1)
  20. #define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9)
  21. #define MVEBU_SPI_A3700_BYTE_LEN BIT(5)
  22. #define MVEBU_SPI_A3700_CLK_PHA BIT(6)
  23. #define MVEBU_SPI_A3700_CLK_POL BIT(7)
  24. #define MVEBU_SPI_A3700_FIFO_EN BIT(17)
  25. #define MVEBU_SPI_A3700_SPI_EN_0 BIT(16)
  26. #define MVEBU_SPI_A3700_CLK_PRESCALE_MASK 0x1f
  27. #define MAX_CS_COUNT 4
  28. /* SPI registers */
  29. struct spi_reg {
  30. u32 ctrl; /* 0x10600 */
  31. u32 cfg; /* 0x10604 */
  32. u32 dout; /* 0x10608 */
  33. u32 din; /* 0x1060c */
  34. };
  35. struct mvebu_spi_platdata {
  36. struct spi_reg *spireg;
  37. struct clk clk;
  38. struct gpio_desc cs_gpios[MAX_CS_COUNT];
  39. };
  40. static void spi_cs_activate(struct mvebu_spi_platdata *plat, int cs)
  41. {
  42. if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&plat->cs_gpios[cs]))
  43. dm_gpio_set_value(&plat->cs_gpios[cs], 1);
  44. else
  45. setbits_le32(&plat->spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
  46. }
  47. static void spi_cs_deactivate(struct mvebu_spi_platdata *plat, int cs)
  48. {
  49. if (CONFIG_IS_ENABLED(DM_GPIO) && dm_gpio_is_valid(&plat->cs_gpios[cs]))
  50. dm_gpio_set_value(&plat->cs_gpios[cs], 0);
  51. else
  52. clrbits_le32(&plat->spireg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
  53. }
  54. /**
  55. * spi_legacy_shift_byte() - triggers the real SPI transfer
  56. * @bytelen: Indicate how many bytes to transfer.
  57. * @dout: Buffer address of what to send.
  58. * @din: Buffer address of where to receive.
  59. *
  60. * This function triggers the real SPI transfer in legacy mode. It
  61. * will shift out char buffer from @dout, and shift in char buffer to
  62. * @din, if necessary.
  63. *
  64. * This function assumes that only one byte is shifted at one time.
  65. * However, it is not its responisbility to set the transfer type to
  66. * one-byte. Also, it does not guarantee that it will work if transfer
  67. * type becomes two-byte. See spi_set_legacy() for details.
  68. *
  69. * In legacy mode, simply write to the SPI_DOUT register will trigger
  70. * the transfer.
  71. *
  72. * If @dout == NULL, which means no actual data needs to be sent out,
  73. * then the function will shift out 0x00 in order to shift in data.
  74. * The XFER_RDY flag is checked every time before accessing SPI_DOUT
  75. * and SPI_DIN register.
  76. *
  77. * The number of transfers to be triggerred is decided by @bytelen.
  78. *
  79. * Return: 0 - cool
  80. * -ETIMEDOUT - XFER_RDY flag timeout
  81. */
  82. static int spi_legacy_shift_byte(struct spi_reg *reg, unsigned int bytelen,
  83. const void *dout, void *din)
  84. {
  85. const u8 *dout_8;
  86. u8 *din_8;
  87. int ret;
  88. /* Use 0x00 as dummy dout */
  89. const u8 dummy_dout = 0x0;
  90. u32 pending_dout = 0x0;
  91. /* dout_8: pointer of current dout */
  92. dout_8 = dout;
  93. /* din_8: pointer of current din */
  94. din_8 = din;
  95. while (bytelen) {
  96. ret = wait_for_bit_le32(&reg->ctrl,
  97. MVEBU_SPI_A3700_XFER_RDY,
  98. true,100, false);
  99. if (ret)
  100. return ret;
  101. if (dout)
  102. pending_dout = (u32)*dout_8;
  103. else
  104. pending_dout = (u32)dummy_dout;
  105. /* Trigger the xfer */
  106. writel(pending_dout, &reg->dout);
  107. if (din) {
  108. ret = wait_for_bit_le32(&reg->ctrl,
  109. MVEBU_SPI_A3700_XFER_RDY,
  110. true, 100, false);
  111. if (ret)
  112. return ret;
  113. /* Read what is transferred in */
  114. *din_8 = (u8)readl(&reg->din);
  115. }
  116. /* Don't increment the current pointer if NULL */
  117. if (dout)
  118. dout_8++;
  119. if (din)
  120. din_8++;
  121. bytelen--;
  122. }
  123. return 0;
  124. }
  125. static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
  126. const void *dout, void *din, unsigned long flags)
  127. {
  128. struct udevice *bus = dev->parent;
  129. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  130. struct spi_reg *reg = plat->spireg;
  131. unsigned int bytelen;
  132. int ret;
  133. bytelen = bitlen / 8;
  134. if (dout && din)
  135. debug("This is a duplex transfer.\n");
  136. /* Activate CS */
  137. if (flags & SPI_XFER_BEGIN) {
  138. debug("SPI: activate cs.\n");
  139. spi_cs_activate(plat, spi_chip_select(dev));
  140. }
  141. /* Send and/or receive */
  142. if (dout || din) {
  143. ret = spi_legacy_shift_byte(reg, bytelen, dout, din);
  144. if (ret)
  145. return ret;
  146. }
  147. /* Deactivate CS */
  148. if (flags & SPI_XFER_END) {
  149. ret = wait_for_bit_le32(&reg->ctrl,
  150. MVEBU_SPI_A3700_XFER_RDY,
  151. true, 100, false);
  152. if (ret)
  153. return ret;
  154. debug("SPI: deactivate cs.\n");
  155. spi_cs_deactivate(plat, spi_chip_select(dev));
  156. }
  157. return 0;
  158. }
  159. static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
  160. {
  161. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  162. struct spi_reg *reg = plat->spireg;
  163. u32 data, prescale;
  164. data = readl(&reg->cfg);
  165. prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
  166. if (prescale > 0xf)
  167. prescale = 0x10 + (prescale + 1) / 2;
  168. prescale = min(prescale, 0x1fu);
  169. data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
  170. data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
  171. writel(data, &reg->cfg);
  172. return 0;
  173. }
  174. static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
  175. {
  176. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  177. struct spi_reg *reg = plat->spireg;
  178. /*
  179. * Set SPI polarity
  180. * 0: Serial interface clock is low when inactive
  181. * 1: Serial interface clock is high when inactive
  182. */
  183. if (mode & SPI_CPOL)
  184. setbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_POL);
  185. else
  186. clrbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_POL);
  187. if (mode & SPI_CPHA)
  188. setbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_PHA);
  189. else
  190. clrbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_PHA);
  191. return 0;
  192. }
  193. static int mvebu_spi_probe(struct udevice *bus)
  194. {
  195. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  196. struct spi_reg *reg = plat->spireg;
  197. u32 data;
  198. int ret;
  199. /*
  200. * Settings SPI controller to be working in legacy mode, which
  201. * means use only DO pin (I/O 1) for Data Out, and DI pin (I/O 0)
  202. * for Data In.
  203. */
  204. /* Flush read/write FIFO */
  205. data = readl(&reg->cfg);
  206. writel(data | MVEBU_SPI_A3700_FIFO_FLUSH, &reg->cfg);
  207. ret = wait_for_bit_le32(&reg->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
  208. false, 1000, false);
  209. if (ret)
  210. return ret;
  211. /* Disable FIFO mode */
  212. data &= ~MVEBU_SPI_A3700_FIFO_EN;
  213. /* Always shift 1 byte at a time */
  214. data &= ~MVEBU_SPI_A3700_BYTE_LEN;
  215. writel(data, &reg->cfg);
  216. /* Set up CS GPIOs in device tree, if any */
  217. if (CONFIG_IS_ENABLED(DM_GPIO) && gpio_get_list_count(bus, "cs-gpios") > 0) {
  218. int i;
  219. for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) {
  220. ret = gpio_request_by_name(bus, "cs-gpios", i, &plat->cs_gpios[i], 0);
  221. if (ret < 0 || !dm_gpio_is_valid(&plat->cs_gpios[i])) {
  222. /* Use the native CS function for this line */
  223. continue;
  224. }
  225. ret = dm_gpio_set_dir_flags(&plat->cs_gpios[i],
  226. GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
  227. if (ret) {
  228. dev_err(bus, "Setting cs %d error\n", i);
  229. return ret;
  230. }
  231. }
  232. }
  233. return 0;
  234. }
  235. static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
  236. {
  237. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  238. int ret;
  239. plat->spireg = dev_read_addr_ptr(bus);
  240. ret = clk_get_by_index(bus, 0, &plat->clk);
  241. if (ret) {
  242. dev_err(bus, "cannot get clock\n");
  243. return ret;
  244. }
  245. return 0;
  246. }
  247. static int mvebu_spi_remove(struct udevice *bus)
  248. {
  249. struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
  250. clk_free(&plat->clk);
  251. return 0;
  252. }
  253. static const struct dm_spi_ops mvebu_spi_ops = {
  254. .xfer = mvebu_spi_xfer,
  255. .set_speed = mvebu_spi_set_speed,
  256. .set_mode = mvebu_spi_set_mode,
  257. /*
  258. * cs_info is not needed, since we require all chip selects to be
  259. * in the device tree explicitly
  260. */
  261. };
  262. static const struct udevice_id mvebu_spi_ids[] = {
  263. { .compatible = "marvell,armada-3700-spi" },
  264. { }
  265. };
  266. U_BOOT_DRIVER(mvebu_spi) = {
  267. .name = "mvebu_spi",
  268. .id = UCLASS_SPI,
  269. .of_match = mvebu_spi_ids,
  270. .ops = &mvebu_spi_ops,
  271. .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
  272. .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
  273. .probe = mvebu_spi_probe,
  274. .remove = mvebu_spi_remove,
  275. };