mpc8xx_spi.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2001 Navin Boppuri / Prashant Patel
  4. * <nboppuri@trinetcommunication.com>,
  5. * <pmpatel@trinetcommunication.com>
  6. * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
  7. * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
  8. */
  9. /*
  10. * MPC8xx CPM SPI interface.
  11. *
  12. * Parts of this code are probably not portable and/or specific to
  13. * the board which I used for the tests. Please send fixes/complaints
  14. * to wd@denx.de
  15. *
  16. */
  17. #include <common.h>
  18. #include <dm.h>
  19. #include <mpc8xx.h>
  20. #include <spi.h>
  21. #include <linux/delay.h>
  22. #include <asm/cpm_8xx.h>
  23. #include <asm/io.h>
  24. #define CPM_SPI_BASE_RX CPM_SPI_BASE
  25. #define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
  26. #define MAX_BUFFER 0x104
  27. static int mpc8xx_spi_probe(struct udevice *dev)
  28. {
  29. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  30. cpm8xx_t __iomem *cp = &immr->im_cpm;
  31. spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
  32. cbd_t __iomem *tbdf, *rbdf;
  33. /* Disable relocation */
  34. out_be16(&spi->spi_rpbase, 0);
  35. /* 1 */
  36. /* ------------------------------------------------
  37. * Initialize Port B SPI pins -> page 34-8 MPC860UM
  38. * (we are only in Master Mode !)
  39. * ------------------------------------------------ */
  40. /* --------------------------------------------
  41. * GPIO or per. Function
  42. * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
  43. * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
  44. * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
  45. * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
  46. * -------------------------------------------- */
  47. clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */
  48. /* ----------------------------------------------
  49. * In/Out or per. Function 0/1
  50. * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
  51. * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
  52. * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
  53. * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
  54. * ---------------------------------------------- */
  55. setbits_be32(&cp->cp_pbdir, 0x0000000F);
  56. /* ----------------------------------------------
  57. * open drain or active output
  58. * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
  59. * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
  60. * PBODR[30] = 0 [0x00000002] -> active output: SPICLK
  61. * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
  62. * ---------------------------------------------- */
  63. clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
  64. /* Initialize the parameter ram.
  65. * We need to make sure many things are initialized to zero
  66. */
  67. out_be32(&spi->spi_rstate, 0);
  68. out_be32(&spi->spi_rdp, 0);
  69. out_be16(&spi->spi_rbptr, 0);
  70. out_be16(&spi->spi_rbc, 0);
  71. out_be32(&spi->spi_rxtmp, 0);
  72. out_be32(&spi->spi_tstate, 0);
  73. out_be32(&spi->spi_tdp, 0);
  74. out_be16(&spi->spi_tbptr, 0);
  75. out_be16(&spi->spi_tbc, 0);
  76. out_be32(&spi->spi_txtmp, 0);
  77. /* 3 */
  78. /* Set up the SPI parameters in the parameter ram */
  79. out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
  80. out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
  81. /***********IMPORTANT******************/
  82. /*
  83. * Setting transmit and receive buffer descriptor pointers
  84. * initially to rbase and tbase. Only the microcode patches
  85. * documentation talks about initializing this pointer. This
  86. * is missing from the sample I2C driver. If you dont
  87. * initialize these pointers, the kernel hangs.
  88. */
  89. out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
  90. out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
  91. /* 4 */
  92. /* Init SPI Tx + Rx Parameters */
  93. while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
  94. ;
  95. out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
  96. CPM_CR_FLG);
  97. while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
  98. ;
  99. /* 5 */
  100. /* Set SDMA configuration register */
  101. out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
  102. /* 6 */
  103. /* Set to big endian. */
  104. out_8(&spi->spi_tfcr, SMC_EB);
  105. out_8(&spi->spi_rfcr, SMC_EB);
  106. /* 7 */
  107. /* Set maximum receive size. */
  108. out_be16(&spi->spi_mrblr, MAX_BUFFER);
  109. /* 8 + 9 */
  110. /* tx and rx buffer descriptors */
  111. tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
  112. rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
  113. clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
  114. clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
  115. /* 10 + 11 */
  116. out_8(&cp->cp_spim, 0); /* Mask all SPI events */
  117. out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
  118. return 0;
  119. }
  120. static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
  121. const void *dout, void *din, unsigned long flags)
  122. {
  123. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  124. cpm8xx_t __iomem *cp = &immr->im_cpm;
  125. cbd_t __iomem *tbdf, *rbdf;
  126. int tm;
  127. size_t count = (bitlen + 7) / 8;
  128. if (count > MAX_BUFFER)
  129. return -EINVAL;
  130. tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
  131. rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
  132. /* Set CS for device */
  133. clrbits_be32(&cp->cp_pbdat, 0x0001);
  134. /* Setting tx bd status and data length */
  135. out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
  136. out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
  137. out_be16(&tbdf->cbd_datlen, count);
  138. /* Setting rx bd status and data length */
  139. out_be32(&rbdf->cbd_bufaddr, (ulong)din);
  140. out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
  141. out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
  142. clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
  143. SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
  144. out_8(&cp->cp_spim, 0); /* Mask all SPI events */
  145. out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
  146. /* start spi transfer */
  147. setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
  148. /* --------------------------------
  149. * Wait for SPI transmit to get out
  150. * or time out (1 second = 1000 ms)
  151. * -------------------------------- */
  152. for (tm = 0; tm < 1000; ++tm) {
  153. if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
  154. break;
  155. if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
  156. break;
  157. udelay(1000);
  158. }
  159. if (tm >= 1000)
  160. printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
  161. /* Clear CS for device */
  162. setbits_be32(&cp->cp_pbdat, 0x0001);
  163. return count;
  164. }
  165. static const struct dm_spi_ops mpc8xx_spi_ops = {
  166. .xfer = mpc8xx_spi_xfer,
  167. };
  168. static const struct udevice_id mpc8xx_spi_ids[] = {
  169. { .compatible = "fsl,mpc8xx-spi" },
  170. { }
  171. };
  172. U_BOOT_DRIVER(mpc8xx_spi) = {
  173. .name = "mpc8xx_spi",
  174. .id = UCLASS_SPI,
  175. .of_match = mpc8xx_spi_ids,
  176. .ops = &mpc8xx_spi_ops,
  177. .probe = mpc8xx_spi_probe,
  178. };